WO2015188594A1

WO2015188594A1 - Preparation method for polycrystalline silicon layer and display substrate, and display substrate

Info

Publication number: WO2015188594A1
Application number: PCT/CN2014/092061
Authority: WO
Inventors: 张慧娟; 亢澎涛
Original assignee: 京东方科技集团股份有限公司
Priority date: 2014-06-11
Filing date: 2014-11-24
Publication date: 2015-12-17
Also published as: CN104037127A

Abstract

A preparation method for a polycrystalline silicon layer and a display substrate, and a display substrate. The preparation method for a polycrystalline silicon layer comprises: forming an amorphous silicon layer (10) on a substrate through a patterning process, wherein the amorphous silicon layer (10) comprises an amorphous silicon bottom part (101) and a plurality of first bulge structures (102) and a plurality of second bulge structures (103) located on the amorphous silicon bottom part (101), the plurality of first bulge structures (102) being located in a first region A, the plurality of second bulge structures (103) being located in a second region B, and the spacing among the plurality of first bulge structures (102) being less than that among the plurality of second bulge structures (103); and conducting excimer laser crystallization on the amorphous silicon layer (10) to form a polycrystalline silicon layer. The method can simultaneously integrate requirements of different devices for the migration rate.

Description

Polysilicon layer and display substrate manufacturing method, display substrate

Technical field

Embodiments of the present invention relate to a method of preparing a polysilicon layer, a method of preparing a display substrate, and a display substrate.

Background technique

Thin Film Transistors (TFTs) can be generally classified into amorphous silicon (a-si) and polycrystalline (poly-si) according to the properties of silicon thin films. Compared with amorphous silicon thin film transistors, polysilicon thin film transistors have higher electron mobility and lower off-state leakage current. Therefore, displays made using polysilicon thin film transistors have higher resolution and faster response speed. .

Amorphous silicon crystallization technology mainly includes Solid Phase Crystallization (SPC), Metal-Induced Lateral Crystallization (MILC), and Excimer Laser Crystallization (ELC). And other technologies. ELC technology is commonly used for the crystallization of amorphous silicon with its high mobility and yield.

Summary of the invention

Embodiments of the present invention provide a method for preparing a polysilicon layer, a method for preparing the display substrate, and a display substrate.

According to an embodiment of the present invention, there is provided a method of fabricating a polysilicon layer, comprising: forming an amorphous silicon layer on a substrate by a patterning process, the amorphous silicon layer comprising an amorphous silicon substrate and being located on the amorphous silicon substrate a plurality of first raised structures and a plurality of second raised structures; wherein the plurality of first raised structures are located in the first area, the plurality of second raised structures are located in the second area, and a spacing between the plurality of first raised structures is less than a spacing between the plurality of second raised structures; and excimer laser crystallization of the amorphous silicon layer to form the polysilicon layer.

In one example, the first region corresponds to a region in which a first thin film transistor is formed, and the second region corresponds to a region in which a second thin film transistor is formed.

In one example, the first thin film transistor includes a switching thin film transistor, and the second thin film transistor includes a driving thin film transistor.

In one example, the spacing between the plurality of first raised structures is 1000-2000 nm. The spacing between the plurality of second raised structures is 1500-2500 nm.

In one example, the plurality of first bump structures located in the first thin film transistor region are equally spaced, and the plurality of second bump structures located in the second thin film transistor region are equally spaced.

In one example, forming an amorphous silicon layer by a patterning process on the substrate includes:

Forming an amorphous silicon film on the substrate, and applying a photoresist on the amorphous silicon film;

Exposing the substrate to which the photoresist is applied by using a half-order mask or a gray-scale mask, and forming a fully-retained portion of the photoresist and a semi-reserved portion of the photoresist after development; wherein the photoresist is completely retained a portion corresponding at least to a region of the plurality of first protrusion structures and the plurality of second protrusion structures to be formed, the photoresist semi-retained portion corresponding to the remaining regions;

Removing the photoresist of the semi-retained portion of the photoresist by an ashing process, and etching the exposed amorphous silicon film to form the first convex structure, the second convex structure, and the Amorphous silicon substrate;

A photoresist that completely retains a portion of the photoresist is removed using a lift-off process.

In one example, the thickness of the bottom portion of the amorphous silicon is

In one example, the thickness of the first raised structure and the second raised structure is

According to an embodiment of the present invention, there is provided a polysilicon layer including a first region and a second region, the first region having a grain size smaller than a grain size of the second region.

According to an embodiment of the present invention, an array substrate is provided, the array substrate includes a polysilicon layer, the polysilicon layer includes a first region and a second region, and the first region has a grain size smaller than that of the second region Grain size.

In one example, the first region includes a first thin film transistor and the second region includes a second thin film transistor.

In one example, the first thin film transistor is a switching thin film transistor, and the second thin film transistor is a driving thin film transistor.

According to an embodiment of the present invention, a method of preparing a display substrate is also provided. The method includes forming an active layer on a region of a base substrate where a first thin film transistor is to be formed and a region where a second thin film transistor is to be formed, a gate insulating layer, a gate electrode, and a source electrode over the active layer And a drain electrode, and forming an electrode structure; the active layer includes a source region, a drain region, a channel region between the source region and the drain region; wherein, the first thin film transistor region is located The active layer of the domain and the second thin film transistor region is obtained by doping a region of the polysilicon layer according to any one of the above, corresponding to the source region and the drain region.

In one example, the electrode structure includes an anode and a cathode.

The method also includes forming a functional layer of organic material between the anode and the cathode.

In one example, the first thin film transistor includes a switching thin film transistor, and the second thin film transistor includes a driving thin film transistor;

Forming the active layer on the first thin film transistor region and the second thin film transistor region of the base substrate includes forming the active layer in a switching thin film transistor region and a driving thin film transistor region of each of the sub-pixel units.

In one example, the method further includes forming a buffer layer on a surface of the base substrate.

In one example, the buffer layer is formed by depositing a single layer of silicon oxide, silicon nitride, or a stack of both on a substrate.

In one example, the doping process includes ion implantation of a region of the polysilicon layer corresponding to the source region and the drain region.

According to an embodiment of the present invention, there is further provided a display substrate prepared by the method of any of the above.

According to an embodiment of the present invention, there is provided a display device including the display substrate.

DRAWINGS

The embodiments of the present invention will be described in more detail below with reference to the accompanying drawings, in which FIG.

1 is a schematic structural diagram of an amorphous silicon layer according to an embodiment of the present invention;

2 is a schematic view showing a grain size of a polysilicon layer according to an embodiment of the present invention;

3, FIG. 4a and FIG. 5 are schematic diagrams showing a process for preparing an amorphous silicon layer according to an embodiment of the present invention;

4b, FIG. 6a, FIG. 6b, and FIG. 6c are schematic diagrams of a process for preparing a patterned amorphous silicon layer according to an embodiment of the present invention;

FIG. 7 is a schematic structural diagram 1 of a backplane of an OLED according to an embodiment of the present disclosure;

FIG. 8 is a schematic structural diagram 2 of a backplane of an OLED according to an embodiment of the present disclosure;

FIG. 9 is a circuit diagram showing a connection relationship between a switching thin film transistor and a driving thin film transistor in a sub-pixel unit of an OLED according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without the need for creative work are within the scope of the present invention.

Unless otherwise defined, technical terms or scientific terms used herein shall be taken to mean the ordinary meaning of the ordinary skill in the art to which the invention pertains. The words "first", "second" and similar terms used in the specification and claims of the present invention do not denote any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the words "a", "an", "the" The word "comprising" or "comprises" or the like means that the element or item preceding the word is intended to be in the "Upper", "lower", etc. are only used to indicate the relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship may also change accordingly.

The inventors have noted that mobility is a very important parameter for thin-film transistors for display substrates of displays, however, even the use of excimer laser crystallization (ELC) for the preparation of polysilicon films has corresponding disadvantages because When the polysilicon film is applied to a thin film transistor of a display substrate, for some thin film transistors such as a switching thin film transistor, it is desirable that the mobility is relatively small to reduce the off-state leakage current, and for other thin film transistors such as a driving thin film transistor, it is desirable The mobility is relatively large, which makes it difficult to integrate the above two reasons in the actual application process, which may affect the performance of the product.

Embodiments of the present invention provide a method for preparing a polysilicon layer, and the method for preparing the polysilicon layer includes the following steps:

S10, forming an amorphous silicon layer 10 as shown in FIG. 1 by a patterning process on a substrate, the amorphous silicon layer 10 including an amorphous silicon bottom portion 101 and a plurality of portions on the amorphous silicon bottom portion 101 A raised structure 102 and a plurality of second raised structures 103. The plurality of first protruding structures 102 are located in the first area A. The first region is, for example, a region where a first thin film transistor is to be formed. The plurality of second protruding structures 103 are located in the second region B. The second area is, for example, to form a second thin The area of the film transistor. A spacing between the plurality of first raised structures 102 is less than a spacing between the plurality of second raised structures 103.

The polysilicon layer may be applied to a display substrate including at least two thin film transistors each of the sub-pixel units, and the at least two thin film transistors include at least one first thin film transistor and at least one second thin film transistor.

Here, the substrate may be a substrate that does not form any film layer, such as a transparent glass substrate or other substrate, or may be a substrate on which a film layer is formed.

S20, performing quasi-molecular laser crystallization on the amorphous silicon layer 10 to obtain the polysilicon layer.

In the process of performing excimer laser crystallization on the amorphous silicon layer 10, since the thickness of the amorphous silicon layer 10 is undulating, the critical full melting energy density of the amorphous silicon layers having different thicknesses is inevitably different. There is necessarily an energy density interval above the critical melting energy density of the lower thickness region (ie, the bottom portion 101 of the amorphous silicon layer in which the raised structure is not formed), such that a higher thickness region (ie, a convex structure is formed) The convex structure of the portion of the amorphous silicon layer 10 is in an incompletely molten state, so that the convex structures can be uniformly nucleated during the crystallization process, ensuring uniform distribution of polycrystalline silicon crystal grains in each thin film transistor region, and increasing The size of the grain is large.

In other words, in the embodiment of the present invention, the first convex structure 102 and the second convex structure 103 can serve as a nucleation center during crystallization, so that the nucleation is more uniform, thereby ensuring each thin film transistor. Uniform distribution of polycrystalline silicon grains in the region.

Here, since the pitch between the plurality of first bump structures 102 located in the first thin film transistor region A is smaller than the pitch between the plurality of second bump structures 103 of the second thin film transistor region B, after crystallization In the formed polysilicon layer, as shown in FIG. 2, the grain size in the first thin film transistor region is relatively small, and the grain size in the second thin film transistor region is relatively large.

It should be noted that the embodiment of the present invention does not specifically define the shapes of the first protruding structure 102 and the second protruding structure 103. For example, the protruding structure may have a square, rectangular or circular cross section to facilitate the shape. Nuclear, but the invention is not limited thereto.

The spacing between the plurality of first protruding structures 102 and the spacing between the plurality of second protruding structures 103 can be set according to actual conditions, so that the mobility requirements of different thin film transistors can be simultaneously integrated, thereby Product performance is guaranteed.

The amorphous silicon layer 10 includes an amorphous silicon bottom portion 101 and a plurality of first protruding structures 102 and a plurality of second protruding structures 103 on the amorphous silicon bottom portion 101. That is, in the region A where the first thin film transistor is to be formed, including the amorphous silicon bottom portion 101 and the amorphous silicon substrate a plurality of first bump structures 102 on the portion 101; a region B where the second thin film transistor is to be formed, including an amorphous silicon bottom portion 101 and a plurality of second bumps on the amorphous silicon bottom portion 101 Structure 103.

In one example of the present invention, the thicknesses of the amorphous silicon bottom portions 101 of all of the thin film transistor regions are equal, and all of the first raised structures 102 and the second raised structures 103 are equal in thickness. The thickness of the amorphous silicon bottom portion 101, the first raised structure 102, and the second raised structure 103 may vary as needed.

When the amorphous silicon layer 10 is subjected to an excimer laser crystallization treatment, the excimer may be selected once, twice or more for the amorphous silicon layer 10 according to characteristics such as thickness and material of the amorphous silicon layer. Laser annealing to form a polysilicon layer.

Embodiments of the present invention provide a method of fabricating a polysilicon layer, the method comprising: forming an amorphous silicon layer 10 on a substrate by a patterning process, the amorphous silicon layer 10 including an amorphous silicon bottom portion 101 and located at the A plurality of first raised structures 102 and a plurality of second raised structures 103 on the amorphous silicon bottom portion 101. The first raised structure 102 is located at a first area A of the substrate, such as a region where a first thin film transistor is to be formed. The second raised structure 103 is located in a second region B of the substrate, such as a region where a second thin film transistor is to be formed. The spacing between the first raised structures 102 is less than the spacing between the second raised structures 103. The method further includes performing excimer laser crystallization on the amorphous silicon layer 10 to obtain a polysilicon layer.

Embodiments of the present invention also provide a polysilicon layer including a first region and a second region, the first region having a grain size smaller than a grain size of the second region.

Embodiments of the present invention also provide an array substrate including a polysilicon layer, the polysilicon layer including a first region and a second region, wherein the first region has a grain size smaller than that of the second region Grain size.

In one aspect, by etching the amorphous silicon layer 10 into an amorphous silicon bottom portion 101 and the first raised structure 102 and the second raised structure 103 on the amorphous silicon bottom portion 101, The amorphous silicon layer 10 is uniformly nucleated during the crystallization process, thereby ensuring uniform distribution of polycrystalline silicon crystal grains in each thin film transistor region, thereby preparing a polycrystalline silicon layer having good uniformity. On the other hand, since the grain size of the polysilicon layer is proportional to the mobility, when the first region A is located When the pitch between the raised structures 102 is smaller than the pitch between the second raised structures 103 of the second region B, the grain size of the polysilicon layer formed in the first region A can be relatively small, so that the first The grain size of the polysilicon layer of the second region B is relatively large. This allows simultaneous integration of different devices, such as thin-film transistors, with mobility requirements to ensure product performance.

For example, the first thin film transistor formed in the first region includes a switching thin film transistor, and the second thin film transistor formed in the second region includes a driving thin film transistor.

Thus, by making the crystal grain size of the polysilicon layer formed in the switching thin film transistor region relatively small, the grain size of the polysilicon layer formed in the driving thin film transistor region is relatively large, and the mobility of the switching thin film transistor region is controlled. It is relatively small to reduce the off-state leakage current while ensuring a relatively large mobility of the driving thin film transistor region.

It should be noted that those skilled in the art should understand that after continuing the other necessary processing, the amorphous silicon bottom portion 101 and the first bump structure 102 located in the switching thin film transistor region will be used as a switching thin film transistor after being crystallized. The active layer, while the amorphous silicon bottom portion 101 and the second bump structure 103 located in the driving thin film transistor region are crystallized, will serve as an active layer for driving the thin film transistor. For example, a corresponding ion implantation process is performed on the formed polysilicon layer to form an active layer as a thin film transistor.

For example, the spacing between the plurality of first protruding structures 102 is 1000-2000 nm, and the spacing between the plurality of second protruding structures 103 is 1500-2500 nm.

In this way, the mobility of the appropriate switching thin film transistor can be ensured, and the off-state leakage current of the switching thin film transistor can be limited to a reasonable range, and the mobility of other thin film transistors can be relatively high.

For example, the plurality of first protruding structures 102 located in the first thin film transistor region are equally spaced, and the plurality of second protruding structures 103 located in the second thin film transistor region are equally spaced.

Thus, after the crystallization treatment, the uniform distribution of the polycrystalline silicon crystal grains located in the respective thin film transistor regions can be further ensured, so that the polysilicon layer formed in each of the thin film transistor regions is more uniform.

Forming the amorphous silicon layer 10 on the substrate by a patterning process can be achieved by the following steps:

S101. As shown in FIG. 3, an amorphous silicon film 10a is formed on a substrate, and a photoresist 20 is applied on the amorphous silicon film 10a.

In this step, for example, a Plasma Enhanced Chemical Vapor Deposition (PECVD) method can be used to form a non-deposit on the substrate. Crystalline silicon film 10a. For example, under a pressure of 2000 mtor, a chamber temperature of 390 ° C, and a radio frequency power of 100 W, SiH 4 reacts with H 2 to deposit an amorphous silicon film 10 a on a substrate.

The thickness of the amorphous silicon film 10a can be, for example,

However, the present invention is not limited thereto, and the thickness of the amorphous silicon film 10a may be set according to actual needs.

S102. As shown in FIG. 4a, the substrate to which the photoresist 20 is applied is exposed by using a half-order mask 30 or a gray-scale mask. After the development, the photoresist completely retained portion 201 and the photoresist are semi-retained. Section 202. The photoresist completely remaining portion 201 corresponds at least to regions of the first bump structure 102 and the second bump structure 103 to be formed, and the photoresist half-retaining portion 202 corresponds to the remaining regions.

Referring to FIG. 4a, the half-order mask 30 can include a fully opaque portion 301, a translucent portion 302. That is, the half-order mask 30 refers to a light-shielding metal layer that forms an opaque light in some areas on the transparent substrate material, and a semi-transmissive light-shielding metal layer in other areas; wherein the semi-transmissive layer The thickness of the light-shielding metal layer is smaller than the thickness of the light-shielding metal layer that is completely opaque; in addition, the semi-transmissive light-shielding metal layer may be changed to ultraviolet light by adjusting the thickness of the semi-transmissive light-shielding metal layer. Transmittance.

Based on this, the working principle of the half-order mask 30 is explained as follows: by controlling the thickness of the light-shielding metal layer at different regions on the half-step mask 30, the intensity of transmitted light in different regions is different. Thus, after selectively exposing and developing the photoresist 20, a photoresist completely remaining portion 201 corresponding to the completely opaque portion 301 and the translucent portion 302 of the half-order mask 30 is formed, and lithography is formed. The glue half retains portion 202.

The principle of the gray scale mask is similar to that of the half mask 90.

The photoresists 20 referred to in all embodiments of the present invention are positive gels.

S103, as shown in FIG. 5, removing the photoresist of the photoresist semi-retaining portion 202 by an ashing process, and etching the exposed amorphous silicon film 10a to form a plurality of first protruding structures 102, A plurality of second raised structures 103, and an amorphous silicon bottom portion 101.

For example, when the thickness of the amorphous silicon film 10a is

When the thickness of the amorphous silicon substrate 101 formed after the etching can be made

The shape of the first protruding structure 102 and the second protruding structure 103 may be a shape of a cube, a cylinder or the like.

S104, removing the photoresist of the photoresist completely remaining portion 201 by a lift-off process to form an amorphous silicon layer 10 as shown in FIG.

On the basis of the above steps S101-S104, when the polysilicon layer obtained by crystallizing the amorphous silicon layer 10 is applied to the active layer, the polysilicon layer of the non-thin film transistor region can be removed by a patterning process, and then passed through corresponding The ion implantation process results in an active layer as a thin film transistor.

Alternatively, on the basis of the above step S101, the patterned amorphous silicon layer only in the thin film transistor region can be directly formed by the following steps, so that the crystallization and corresponding ion implantation processes can be directly obtained on the basis of the above steps. As an active layer of a thin film transistor, for example,

S105. As shown in FIG. 4b, the substrate to which the photoresist 20 is applied is exposed by using a half-order mask 30 or a gray-scale mask. After the development, a photoresist completely remaining portion 201 is formed, and the photoresist is semi-reserved. Portion 202 and photoresist completely remove portion 203. The photoresist completely remaining portion 201 corresponds at least to a region of the first protruding structure 102 and the second protruding structure 103 to be formed, and the photoresist half-retaining portion 202 corresponds to the first to be formed. The amorphous silicon bottom portion 101 between the raised structures 102 and the second raised structures 103, and the photoresist completely removed portions 203 correspond to other regions.

The half-order mask 30 may include a fully opaque portion 301, a translucent portion 302, and a fully transparent portion 303. That is, the half-order mask 30 means that a light-shielding metal layer which is opaque is formed in some areas on the transparent substrate material, a light-shielding metal layer which is semi-transparent is formed in other areas, and no light-shielding metal layer is formed in other areas. . The semi-transmissive light-shielding metal layer has a thickness smaller than a thickness of the completely opaque light-shielding metal layer. Further, the transmittance of the semi-transmissive light-shielding metal layer to ultraviolet light can be changed by adjusting the thickness of the semi-transmissive light-shielding metal layer.

Based on this, the working principle of the half-order mask 30 is explained as follows: by controlling the thickness of the light-shielding metal layer at different regions on the half-step mask 30, the intensity of transmitted light in different regions is different. Thus, after the selective exposure and development of the photoresist 20, the photoresist corresponding to the completely opaque portion 301, the translucent portion 302, and the completely transparent portion 303 of the half-order mask 30 is completely retained. The portion 201, the photoresist half-retained portion 202, and the photoresist completely removed portion 203.

The principle of the gray scale mask is similar to that of the half mask 90.

S106, as shown in FIG. 6a, the amorphous silicon film 10a of the photoresist completely removed portion 203 is removed by an etching process.

S107, as shown in FIG. 6b, removing the photoresist of the photoresist semi-retaining portion 202 by an ashing process, and etching the exposed amorphous silicon film 10a to form the first protruding structure 102, The second raised structure 103 and the amorphous silicon substrate 101.

S108, removing the photoresist of the photoresist completely remaining portion 201 by a lift-off process to form a patterned amorphous silicon layer as shown in FIG. 6c.

On the basis of the above steps S101-S104 or S105-S108, in order to avoid the crystallization treatment of the amorphous silicon layer 10 by the excimer laser crystallization method, a problem of hydrogen explosion occurs. In the embodiment of the present invention, the amorphous silicon layer 10 is preferably subjected to a dehydrogenation process before the crystallization of the amorphous silicon layer 10 by using excimer laser crystallization, for example, by a conventional annealing furnace at 450 ° C. The hydrogen in the amorphous silicon layer was removed by holding for 1.5 hours.

Further, in consideration of the inclusion of harmful substances such as alkali metal ions in the glass substrate, the performance of the amorphous silicon layer 10 may be affected. Therefore, the present invention may select, for example, a buffer layer formed on the substrate. The buffer layer may be a single layer of silicon oxide, silicon nitride or a laminate of the two.

On the basis of the polysilicon layer formed above, the embodiment of the present invention further provides a method for preparing a display substrate. As shown in FIG. 7, the method includes: a first thin film transistor region A and a second surface of the base substrate 40. The thin film transistor regions B each form an active layer 50, a gate insulating layer 60 over the active layer 50, a gate electrode 70, a source electrode 801, and a drain electrode 802, and form an electrode structure. The active layer 50 includes a source region 501, a drain region 502, and a channel region 503 between the source region 501 and the drain region 502. The active layer 50 located in the first thin film transistor region A and the second thin film transistor region B is doped by the region corresponding to the source region 501 and the drain region 502 of the above polysilicon layer. Miscellaneous crafts are obtained.

It should be noted that, in FIG. 7, only two thin film transistors and corresponding electrode structures are schematically illustrated, and the connection between the two thin film transistors is not illustrated, but those skilled in the art should clearly The difference in the type of the display substrate, in either of the sub-pixel units, whether there are two thin film transistors or two or more thin film transistors, there is a corresponding connection relationship, which may be determined according to actual conditions.

In one aspect, the amorphous silicon layer 10 is etched into an amorphous silicon bottom portion 101 and the plurality of first raised structures 102 and the plurality of second raised structures 103 on the amorphous silicon bottom portion 101. The nucleation can be uniformly performed during the crystallization of the amorphous silicon layer 10, thereby ensuring uniform distribution of polycrystalline silicon crystal grains in each thin film transistor region, thereby preparing a polycrystalline silicon layer having good uniformity. On the other hand, since the grain size of the polysilicon layer is proportional to the mobility, the pitch between the plurality of first bump structures 102 located in the first switching thin film transistor region is smaller than the plurality of second portions located in the second thin film transistor region When the pitch between the bump structures 103 is increased, the crystal grain size of the polysilicon layer formed in the first thin film transistor region may be relatively small to be formed in the second thin film transistor region. The grain size of the polysilicon layer is relatively large, so that the mobility requirements of different thin film transistors can be integrated at the same time, thereby ensuring product performance.

For example, as shown in FIG. 8, in consideration of harmful substances contained in the glass substrate, such as alkali metal ions, it is possible to affect the performance of the amorphous silicon layer 10 before the formation of the polysilicon layer, and therefore, the implementation of the present invention can be selected. The buffer layer 200 is formed, for example, on the base substrate 40. The buffer layer 200 may be a single layer of silicon oxide, silicon nitride, or a laminate of the two.

Optionally, the display substrate may be a back plate of an Organic Light-Emitting Diode (OLED). In this case, as shown in FIG. 7, the electrode structure includes an anode 901 and a cathode 902. The method further includes forming an organic material functional layer 903 between the anode 901 and the cathode 902.

The organic material functional layer 903 may include an electron transport layer, a light emitting layer, and a hole transport layer. In order to increase the efficiency of the electrons and the hole injection into the light-emitting layer, the organic material functional layer 903 may further include an electron injection layer disposed between the cathode and the electron transport layer, and at the anode a hole injection layer with the hole transport layer.

Considering the particularity of the organic material functional layer material 903, after the back sheet of the organic electroluminescent diode is fabricated, an encapsulation layer for encapsulating the organic material is formed to block water and oxygen, thereby forming an organic electroluminescent diode display device. .

Here, depending on the materials of the anode 901 and the cathode 902 used, the display device can be classified into a single-sided light-emitting type display device and a double-sided light-emitting type display device. That is, when the material of one of the anode 901 and the cathode 902 is an opaque material, the display device is of a single-sided illumination type; and when the material of the anode 901 and the cathode 902 is transparent or semi- In the case of a transparent material, the display device is of a double-sided illumination type.

The single-sided light-emitting display device can be further classified into an upper light-emitting type and a lower light-emitting type depending on the materials of the anode 901 and the cathode 902. When the anode 901 is disposed adjacent to the base substrate 40, the cathode 902 is disposed away from the base substrate 40, and the material of the anode 901 is a transparent conductive material, and the material of the cathode 902 is an opaque conductive material. Since the light is emitted from the anode 901 and the side of the base substrate 40, such a single-sided light-emitting display device can be referred to as a lower light-emitting type. When the material of the anode 901 is an opaque conductive material, and the material of the cathode 902 is a transparent or translucent conductive material, since light is emitted from the cathode 902 and then through the encapsulation layer disposed opposite to the substrate 40, Such a single-sided light-emitting type display device can be referred to as an upper light-emitting type.

For the double-sided light-emitting type display device, when the anode 901 is disposed close to the base substrate 40, the cathode 902 is disposed away from the base substrate 40, or when the anode 901 is disposed away from the base substrate 40, The cathode 902 is disposed adjacent to the base substrate 40, and when the material of the anode 904 and the cathode 902 is a transparent or translucent conductive material, since light is from the anode 901 and the substrate substrate 40 side The emission device is emitted from the cathode 902 and the encapsulation layer disposed opposite to the substrate 40, and thus the display device can be referred to as a double-sided illumination type.

For example, the first thin film transistor includes a switching thin film transistor, and the second thin film transistor includes a driving thin film transistor. On the basis of this, referring to FIG. 7, forming the active layer 50 on the first thin film transistor region and the second thin film transistor region of the base substrate 40 includes forming in the switching thin film transistor region and the driving thin film transistor region of each sub-pixel unit. The active layer 50.

For example, as shown in FIG. 9, it is an equivalent circuit diagram of a connection relationship between a switching thin film transistor and a driving thin film transistor. The gate electrode 70 of the switching thin film transistor is electrically connected to the gate line, the source electrode 801 of the switching thin film transistor is electrically connected to the data line, the drain electrode 802 of the switching thin film transistor is electrically connected to the gate electrode 70 of the driving thin film transistor, and the source electrode of the thin film transistor is driven. The 801 is electrically connected to the power line of the OLED, and the drain electrode 802 of the driving thin film transistor is electrically connected to the anode 901 of the OLED.

Referring to FIG. 8, an example is provided below to describe in detail a method for preparing a backplane of the OLED, the method comprising the following steps:

S201. Optionally, a buffer layer 200 is formed on the base substrate 40.

The buffer layer 200 can be formed by depositing a single layer of silicon oxide, silicon nitride, or a combination of both on a substrate. The thickness of the buffer layer 200 can be

S202. On the basis of completing S201, an amorphous silicon layer 10 is formed on the buffer layer 200 by a patterning process.

The amorphous silicon layer 10 includes an amorphous silicon substrate 101 and a plurality of first protruding structures 102 and a plurality of second protruding structures 103 on the amorphous silicon substrate 101. The first raised structure 102 is located in a switching thin film transistor region of each sub-pixel unit, and the second raised structure 103 is located in a driving thin film transistor region of each sub-pixel unit. The spacing between the plurality of first protruding structures 102 is 1000-2000 nm, and the spacing between the plurality of second protruding structures 103 is 1500-2500 nm.

The thickness of the amorphous silicon substrate 101 may be

The thickness of the first protrusion structure 102 and the second protrusion structure 103 may be

S203. On the basis of completing S202, the substrate on which the amorphous silicon layer 10 is formed is placed on the annealing. Dehydrogenation treatment is carried out in the furnace.

For example, hydrogen in the amorphous silicon layer can be removed by heating at 450 ° C for 1.5 hours in a conventional annealing furnace.

S204. Performing excimer laser crystallization on the amorphous silicon layer 10 to complete the S203, to obtain the polysilicon layer.

S205. On the basis of completing S204, a gate insulating layer 60 and a gate electrode 70 are formed.

The gate insulating layer 40 may be a single layer of silicon oxide, silicon nitride, or a laminate of the two. The thickness of the gate insulating layer 40 may be

The gate electrode 50 may be made of a conductive material such as a metal or a metal alloy such as molybdenum or molybdenum alloy. Thickness can be

S206. On the basis of completing S205, an ion implantation process is performed on a region of the polysilicon layer corresponding to the source region 501 and the drain region 502 to form the active layer 50. The active layer 50 includes a source region 501, a drain region 502, and a channel region 503 between the source region 501 and the drain region 502.

S207. On the basis of completing S206, an interlayer insulating layer is formed, and a source electrode 801 and a drain electrode 802 are formed on the interlayer insulating layer. The source electrode 801 and the drain electrode 802 are in contact with the source region 501 and the drain region 502 through via holes formed on the interlayer insulating layer and the gate insulating layer 60, respectively.

The interlayer insulating layer may be a single layer of silicon oxide or a stack of silicon oxide and silicon nitride. The thickness of the interlayer insulating layer can be

The source electrode 801 and the drain electrode 802 may be made of a conductive material such as a metal or a metal alloy such as molybdenum, molybdenum alloy, aluminum, aluminum alloy, or titanium. Thickness can be

Thus far, a switching thin film transistor and a driving thin film transistor have been formed in which the drain electrode 802 of the switching thin film transistor is electrically connected to the gate electrode 70 of the driving thin film transistor.

S208. On the basis of completing S207, a planarization layer is formed, and an anode 901 electrically connected to the drain electrode 802 of the driving thin film transistor, and an organic material functional layer 903 and a cathode 902 are formed on the planarization layer.

So far, the back sheet of the OLED has been prepared. In view of the particularity of the organic material functional layer material 903, after the back sheet of the above OLED is fabricated, an encapsulation layer for encapsulating an organic material is formed to block water and oxygen, thereby forming an organic electroluminescent diode display device.

The embodiment of the invention further provides a display substrate, which is passed through the display base described above. The preparation method of the board is obtained.

The display substrate may be any display substrate in which each of the sub-pixel units includes two or more thin film transistors and the two or more thin film transistors have different mobility requirements, such as a back sheet of an OLED.

Embodiments of the present invention also provide a display device including the display substrate.

Embodiments of the present invention provide a method for fabricating a polysilicon layer and a display substrate, and a display substrate, the polysilicon layer being applied to a display substrate each including at least two thin film transistors, wherein the at least two thin film transistors include There are at least one first thin film transistor and at least one second thin film transistor. The method includes forming an amorphous silicon layer on a substrate by a patterning process, the amorphous silicon layer including an amorphous silicon bottom portion and a plurality of first convex structures and a plurality of first portions on the amorphous silicon substrate a second raised structure, the first raised structure is located in a first thin film transistor region, the second raised structure is located in a second thin film transistor region, and a spacing between the first raised structures is smaller than the second The pitch between the raised structures and the quasi-molecular laser crystallization of the amorphous silicon layer are performed to obtain the polysilicon layer.

In one aspect, the amorphous silicon layer can be formed by etching the amorphous silicon layer into an amorphous silicon bottom portion and the first protruding structure and the second protruding structure on the amorphous silicon bottom portion. Uniform nucleation during crystallization ensures uniform distribution of polycrystalline silicon grains in each thin film transistor region, thereby preparing polycrystalline silicon with better uniformity. On the other hand, since the grain size of the polysilicon layer is proportional to the mobility, when the pitch between the first bump structures located in the first thin film transistor region is smaller than between the second bump structures located in the second thin film transistor region In the case of spacing, the crystal grain size of the polysilicon layer formed in the first thin film transistor region can be relatively small, so that the crystal grain size of the polysilicon layer formed in the second thin film transistor region is relatively large, so that different thin film transistor pairs can be simultaneously integrated Mobility requirements to ensure product performance.

The above is only the exemplary embodiments and examples of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of each within the scope of the present disclosure. Such changes or substitutions are omitted or added, and such changes or modifications and equivalents thereof are intended to be included within the scope of the present invention.

The present application claims priority to Chinese Patent Application No. 201410258999.X filed on Jun. 11, 2014, the disclosure of which is incorporated herein by reference. .

Claims

A method for preparing a polysilicon layer, comprising:

Forming an amorphous silicon layer on the substrate by a patterning process, the amorphous silicon layer including an amorphous silicon bottom portion and a plurality of first protruding structures and a plurality of second protruding structures on the amorphous silicon bottom portion Wherein the plurality of first raised structures are located in a first region on the substrate, the plurality of second raised structures are located in a second region on the substrate, and the plurality of first raised structures a spacing between them is less than a spacing between the plurality of second raised structures;

The amorphous silicon layer is subjected to excimer laser crystallization to form the polysilicon layer.
The method of claim 1, wherein the first region corresponds to a region in which a first thin film transistor is formed, and the second region corresponds to a region in which a second thin film transistor is formed.
The method of claim 2 wherein said first thin film transistor comprises a switching thin film transistor and said second thin film transistor comprises a driving thin film transistor.
The method according to any one of claims 1 to 3, wherein a pitch between the plurality of first convex structures is 1000-2000 nm, and a pitch between the second raised structures is 1500-2500 nm.
The method according to any one of claims 1 to 4, wherein the plurality of first convex structures located in the first region are equally spaced, and the plurality of second protrusions located in the second region The structure is equally spaced.
The method according to any one of claims 1 to 5, wherein the forming an amorphous silicon layer by a patterning process on a substrate comprises:

Forming an amorphous silicon film on the substrate, and applying a photoresist on the amorphous silicon film;

Exposing the substrate to which the photoresist is applied by using a half-order mask or a gray-scale mask, and forming a fully-retained portion of the photoresist and a semi-reserved portion of the photoresist after development; wherein the photoresist is completely retained The portion at least corresponds to the region of the plurality of first protrusion structures and the plurality of second protrusion structures to be formed, and the photoresist semi-reserved portion corresponds to the remaining regions;

Removing the photoresist of the semi-retained portion of the photoresist by an ashing process, and etching the exposed amorphous silicon film to form the plurality of first protruding structures and the plurality of second protruding structures And the amorphous silicon substrate;

A photoresist that completely retains a portion of the photoresist is removed using a lift-off process.
The method according to any one of claims 1 to 6, wherein the thickness of the bottom portion of the amorphous silicon is
The method of claims 1-7, wherein the thickness of the first raised structure and the second raised structure is
A polysilicon layer includes a first region and a second region, the first region having a grain size smaller than a grain size of the second region.
An array substrate comprising a polysilicon layer, the polysilicon layer comprising a first region and a second region, the first region having a grain size smaller than a grain size of the second region.
The array substrate of claim 10, wherein the first region comprises a first thin film transistor and the second region comprises a second thin film transistor.
The array substrate according to claim 11, wherein the first thin film transistor is a switching thin film transistor, and the second thin film transistor is a driving thin film transistor.
A method for preparing a display substrate, comprising:

An active layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode over the active layer are formed on both a region of the base substrate where the first thin film transistor is to be formed and a region where the second thin film transistor is to be formed, and Forming an electrode structure; the active layer includes a source region, a drain region, and a channel region between the source region and the drain region;

The active layer in the first thin film transistor region and the second thin film transistor region is the source region and the drain of the polysilicon layer obtained by the preparation method according to any one of claims 2-8 The corresponding regions of the polar regions are obtained by a doping process.
The method of claim 13 wherein said electrode structure comprises an anode and a cathode;

The method also includes forming a functional layer of organic material between the anode and the cathode.
The method according to claim 13 or 14, wherein

The first thin film transistor includes a switching thin film transistor, and the second thin film transistor includes a driving thin film transistor;

Forming the active layer on the first thin film transistor region and the second thin film transistor region of the base substrate includes forming the active layer in the switching thin film transistor region and the driving thin film transistor region.
The method according to any one of claims 13 to 15, further comprising forming a buffer layer on a surface of the base substrate.
The method of claim 16 wherein said buffer layer is deposited on a substrate A single layer of silicon oxide, silicon nitride, or a combination of both is formed.
The method of any of claims 13-17, wherein the doping process comprises ion implantation of a region of the polysilicon layer corresponding to the source region and the drain region.
A display substrate, wherein the display substrate is prepared by the method of any one of claims 13-18.
A display device comprising the display substrate of claim 19.