WO1999016078A1

WO1999016078A1 - Synchronous integrated circuit device

Info

Publication number: WO1999016078A1
Application number: PCT/JP1997/003327
Authority: WO
Inventors: Takashi Akioka; Seigo Yukutake; Hiroshi Toyoshima
Original assignee: Hitachi, Ltd.; Hitachi Ulsi Enginnering Corp.
Priority date: 1997-09-19
Filing date: 1997-09-19
Publication date: 1999-04-01
Also published as: AU4222197A; TW363186B

Abstract

A synchronous semiconductor circuit device is constituted so that the time margin of a sense amplifier section can be reduced correspondingly to the reduction of cycle time by determining the activating timing of a positive feedback sense amplifier by using a clock edge which is different from a clock edge used for determining timing required for data to be input to the sense amplifier after the data has been transmitted to a bit line from a word line.

Description

Specification

Synchronous integrated circuit device

Technical field

The present invention relates to an integrated circuit device, and more particularly to a technique for improving the performance of a synchronous integrated circuit device whose operation timing is controlled by a clock signal.

Background art

A positive feedback sense amplifier is generally used for a sense amplifier circuit of a memory included in an integrated circuit such as an SRAM, a DRAM, and a microcomputer. The positive feedback sense amplifier uses a positive feedback circuit to amplify small amplitude data. Once a positive feedback sense amplifier starts amplification, it is faster and requires less power than other types of circuits, and requires a signal to activate it.

The signal for activation is a signal for specifying a time at which the positive feedback starts. If the signal for activation is slow, the delay time of the sense amplifier increases. However, if it is too fast, there is a danger that erroneous data will be amplified and the delay time will increase significantly. Positive feedback sense amplifiers do not have a means to restore erroneous data once it has begun to amplify, so amplifying erroneous data can quickly lead to malfunction.

The characteristics of integrated circuit devices in product specifications are based on a certain range of environmental conditions. Therefore, when designing an integrated circuit device, it is necessary to design such that the characteristics always fall within the product specifications under the environmental conditions within this range. To do so, it is necessary to design with a sufficient margin so that the characteristics can be satisfied even under the worst operating environment conditions for the characteristics of the integrated circuit or even under the worst manufacturing process conditions .

It is clear from the above that the characteristics of integrated circuit devices with respect to product specifications depend on the product specifications, manufacturing processes, and margins at the design stage. Is fixedly determined. That is, no changes are possible after the design is complete.

Therefore, in the clock control circuit of the integrated circuit device, a sufficient timing margin is required between the clock signal generating side and the receiving side for normal operation, and even under the worst condition, this margin is required. It is designed to be secured.

Disclosure of the invention

In a high-speed sense amplifier circuit, a positive feedback circuit is generally used to keep current consumption small. The power consumption of the positive feedback circuit is small because the current can be cut off until the activation signal arrives. However, in order to avoid malfunction of the sense amplifier, its activation signal must always be sufficiently delayed from the input signal to the sense amplifier, which has hindered the speeding up of the sense amplifier circuit.

An object of the present invention is to provide a high-speed positive feedback type sense amplifier activation method which does not require a magazine to be set at the time of design.

The earlier the activation time of the sense amplifier is, the shorter the delay time when it operates is. Therefore, to obtain a high-speed sense amplifier, the activation time may be set earlier. However, if the speed is too fast, the device will malfunction. If the device characteristics of individual transistors, etc., do not vary to the better side, a good product that will operate normally can be obtained. Therefore, in high-performance products that must be designed with the highest device performance among the variations in device conditions, many failures may occur. Therefore, there was a problem that the price of high-speed products became very expensive.

Another object of the present invention is to eliminate a defective product that malfunctions due to device variation even in a design using a positive feedback type sense amplifier circuit for the highest speed. In general, in the design stage of an integrated circuit device, since there is a certain range of environmental conditions and manufacturing process conditions for which operation must be guaranteed, it is necessary to set an operation margin so that operation can be performed even under the worst conditions. For that purpose, information on the manufacturing process conditions at which the individual characteristics of the integrated circuit device become the worst is required. This information is not clear at the beginning of the design. Circuit design and element (device) design often proceed in parallel, in which case the exact device conditions are not known at the beginning of the design.

However, in the design of the activation signal of the positive feedback type sense amplifier, the margin of the activation signal is fixed at the time of design, so it is necessary to increase the margin to cope with unknown device characteristics. There is a problem that the circuit speed cannot be increased.

Another object of the present invention is to provide a circuit system which can obtain the highest performance of a device even when the boundary conditions of the design change as described above in the design of a synchronous integrated circuit device.

In order to achieve the above object, according to the present invention, when two synchronization signals in a synchronous integrated circuit device are synchronized, each synchronization signal is referred to a different time point (timing). , The time between these signals is changed according to the frequency of the synchronization signal.

More specifically, by forming a clock edge used for generating the sense amplifier activation signal separately from a clock edge that determines data to be amplified by the sense amplifier, the clock frequency is improved. In other words, when the time between these edges decreases, the time between the data to be amplified by the sense amplifier and the sense amplifier activation signal automatically becomes shorter, and a magazine corresponding to the increase in the clock frequency can be obtained. it can.

By the above means, it is not necessary to set a magazine at the time of designing, and a high-speed positive feedback sense amplifier activation method can be obtained. Further, the above-described means makes it possible to design the sense amplifier circuit for the highest high-speed performance even if the devices vary, and the number of malfunctioning defective products does not increase.

In addition, even if the device characteristics change from those assumed when designing a synchronous integrated circuit by the above-described means, the highest performance of the device can be obtained because the margin changes as the device speed increases. A circuit system can be obtained.

One embodiment of the present invention includes a clock terminal to which a clock signal is input, and an internal circuit to which a signal to be processed is input. A signal to be processed on the basis of the rising edge of the pulse is input to the internal circuit, and the synchronous integrated circuit operates the internal circuit on the basis of the second time of the clock signal (eg, the rising edge of the second pulse). is there. With such a configuration, the input timing of the signal to be processed and the operation timing of the internal circuit can be set independently, and the timing interval can be easily changed.

By processing the clock signal with a DLL circuit, SMD circuit, or PLL circuit, these evenings can be set from the clock. In these DLL circuits or PLL circuits, a first delay circuit whose delay time changes according to the frequency of the clock signal and a second delay circuit whose delay time is constant regardless of the frequency of the clock signal are included in the loop. By having two delay circuits, a simple configuration can be achieved.

The present invention is also suitable for use in a semiconductor memory device. In this case, the semiconductor memory device operates based on a clock signal, and includes a plurality of memory cells for storing information, and at least a memory cell. A decoder that decodes an address signal for specifying one and an output signal that reflects information stored in the memory cell specified by the address signal An output line, and an amplifier for amplifying the output signal, wherein the decoder decodes an address signal of the first time of the clock signal, and the output line is a second time after a predetermined time of the first time. An output signal is output at the time, and the amplifier is activated at a fourth time shifted by a predetermined time from a third time different from the first time. With such a configuration, the operation margin of the device can be flexibly changed.

Here, for example, the first time is the rising or falling of the first pulse of the close signal, and the third time is the second time after the first pulse of the clock signal. The rising or falling edge of the pulse.

Further, the amplifier may be activated at a fourth time that is a predetermined time before a third time different from the first time, and the amplifier may be activated at a fourth time different from the first time. It may be activated at a fourth time which is a predetermined time after the time of 3.

In such a semiconductor memory device, a plurality of memory cells are respectively connected to a lead line, and the lead line can be unselected on the basis of the third time.

In another embodiment of the synchronous integrated circuit of the present invention, in a synchronous integrated circuit including a sense amplifier to which an activation time is input from the outside, the reference time is based on the input time of a signal to be amplified by the sense amplifier. Activating the sense amplifier based on another time.

According to another embodiment of the synchronous integrated circuit of the present invention, in a synchronous integrated circuit having a sense amplifier whose activation time is designated by an external clock signal, the amount of change in the clock cycle of the clock signal is reduced. The absolute value, the time interval between the activation time of the sense amplifier and the input time of the signal to be amplified to the sense amplifier, change correspondingly. That is, the frequency of the input clock signal The machine's magazine changes automatically depending on the situation.

In another ocean of the present invention, in a synchronous cook signal generating circuit having a phase comparator and a variable delay circuit controlled by the phase comparator, an input signal of the phase comparator includes a synchronous mirror delay circuit. The input and output signals are used, and a variable delay circuit controlled by the output of the phase comparator is used as a part of the delay circuit in the synchronous mirror delay circuit. The present invention also relates to a semiconductor memory device that operates based on a clock signal, comprising a plurality of memory cells for storing information, a data line and a pad line connected to the memory cells, and an output signal of the data line. When reading information from the memory cell, the data line outputs an output signal at a second time which is a predetermined time after the first time of the clock signal. The semiconductor memory device may be configured to be activated at a fourth time shifted by a predetermined time from a third time different from the first time.

As an operation timing of this device, for example, when information is written to a memory cell, the data line is started at a fifth time which is different from the first time of the clock signal by a predetermined time, and the second line of the clock signal is raised. At a sixth time which is different from the time of the clock signal by a predetermined time, and the lead line is raised at a seventh time which is different from the first time of the above-mentioned mouth signal by a predetermined time, and It falls at the eighth time, which is different from the second time by a predetermined time.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is an activation timing diagram of a sense amplifier according to the present invention. Figure 2 is a block diagram of a synchronous SRAM according to the present invention. Fig. 3 is a timing diagram showing an example of conventional activation timing. Figure 4 is a circuit diagram of the positive feedback type sense amplifier. FIG. 5 is a circuit diagram of a clock synchronous circuit for a synchronous integrated circuit of the present invention. FIG. 6 is a timing diagram of the clock synchronous circuit for the synchronous integrated circuit of the present invention. FIG. 7 is another circuit diagram of the clock synchronization circuit for the synchronous integrated circuit of the present invention. Figure FIG. 8 is a sunset view of another circuit of the clock synchronous circuit for the synchronous integrated circuit of the present invention. FIG. 9 is another activation timing diagram of the sense amplifier according to the present invention. FIG. 10 is another activation timing diagram of the sense amplifier according to the present invention. Figure 11 shows another block diagram of a synchronous SRAM. FIG. 12 is a timing diagram of a synchronous DRAM to which the present invention is applied. FIG. 13 is another timing diagram of the synchronous DRAM to which the present invention is applied. FIG. 14 is another timing diagram of the synchronous DRAM to which the present invention is applied. FIG. 15 is another timing diagram of the synchronous DRA to which the present invention is applied. FIG. 16 is another timing diagram of the synchronous DRAM to which the present invention is applied. FIG. 17 is a circuit layout diagram in a chip using the present invention. Figure 18 is a timing diagram showing an example of application to a Register-Latch (R / L) type synchronous DRAM. Figure 19 is a timing diagram showing an example of application to Register-Through (R / T) type synchronous memory. FIG. 20 is a timing diagram showing the relationship between a lead line and a bit line during writing to a synchronous memory. Figure 21 is a block diagram showing a typical SMD circuit. 2 2 is a block diagram showing the improved circuit of SMD

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the timing of an embodiment when the present invention is applied to an SRAM will be described with reference to FIG. The circuit configuration will be described later with reference to FIG.

FIG. 1 shows the timing of the operation of the memory circuit to which the present invention is applied. Each row is a schematic diagram of the signal voltage waveform of the circuit section showing its name.

CLK is a clock signal input to the sense amplifier and the activation signal generation circuit from outside the integrated circuit or from another circuit in the integrated circuit. Similarly, Address is the voltage waveform of the address signal input from outside the memory circuit to this memory circuit, Word line is the voltage waveform of the signal on the first line of the memory cell, and SACK is the memory circuit. Activation of positive feedback type sense amplifier The voltage waveform of the signal, the SA output shows the voltage waveform of a node that latches the signal of the positive feedback type sense amplifier, and the Data output shows the voltage waveform of the output signal of the data read out from the memory circuit of this embodiment.

The memory that realizes such operation has a register for address input, and reads out memory cell data corresponding to the address information at the rising edge of the clock CLK of the input address signal (time A in this case). Works. That is, the data corresponding to address A is taken into the input register at time A, the data corresponding to this address is output to the output node within a certain time from time B, and the output signal is output after time C is input. There is a need to hold for a certain period of time.

At the time A when the CLK signal rises, the address information A of the memory cell from outside the memory circuit is decoded by the decoder. Next, a Word line corresponding to the decoded address is set up. When the word line rises, the data from the selected memory cell reaches the sense amplifier and generates a small voltage amplitude at the SA output node in Fig. 1. In other words, in the series of events up to this point, the timing is determined from the rising time A of the CLK.

After that, the SACK signal rises. That is, the sense amplifier is activated to amplify the signal having the small voltage amplitude, and the output register circuit at the subsequent stage of the sense amplifier circuit converts the data into a voltage that can latch data.

In this embodiment, as shown in the figure, the rise of the SACK, that is, the activation timing of the sense amplifier is determined based on the rise of the clock at time B. This meaning will be described more specifically below.

When the clock frequency decreases, that is, when the time B measured from the time A is delayed, in the present embodiment, the rising time of the SACK measured based on the time A is also delayed by the same amount. For example, based on time A, If the measured time B is delayed by Ins, the SACK will also be delayed by Ins.

With this setting, the margin 1 shown in the figure changes depending on the frequency of the clock, and the SACK can be advanced to the limit value determined by this device.

Conventionally, this margin 1 is used to prevent the positive feedback type sense amplifier from malfunctioning even under the worst conditions such as environmental conditions (temperature, power supply voltage) and device conditions (variation in the characteristics of the M0S transistor). It had to be set. That is, when environmental conditions such as device conditions change, a very large margin may be wasted too much.

In the case of a memory circuit, the number of memory cells is large, and the worst condition is determined by the worst memory cell among many memory cells. Therefore, it is inevitable to take a large margin to secure a normally operating product. According to the present embodiment, it is possible to set the minimum margin required according to the manufacturing process of the memory cell and the operating environment.

Fig. 2 shows an example of a memory block configuration for realizing the timing shown in Fig. 1. FIG. 2 shows an example of the configuration of an 8 Mbit synchronous SRAM circuit to which the present invention is applied, and accesses a memory cell array 200. AO-ΑΠ is address input, / SS is synchronous select signal input, / SWE is synchronous write signal, / SWEx is synchronous bit line signal input, / G is asynchronous output control signal, CK, / CK Is a clock signal input, VREF is a reference voltage input terminal for an I / O interface, ZQ is an output impedance programming terminal, and DQ0-DQ35 are data input / output terminals.

The address, / SS, / SWE, and / SWEx are registered in each of the registers 21 to 24 after the input buffer when the clock signal is switched. If it is a write cycle, the address is registered in W-Add register 25. In the case of a write cycle, the previous write address is selected and MUX 26 It is output, and in the case of reading, the input address is directly input from MUX 26 to Row deocder 27 or Column decoder 28.

WRC 29 is a circuit that controls switching between a read state and a write state, and controls WA (write circuit) 30, SA (sense amplifier) 31, and the like. The EXN0R circuit 32 at the MUX input of the address always checks whether the input address is the same as the previous write address, and if they match, the MUX 33 output by the Match signal outputs the write data as it is. You. After that, the output data is temporarily stored in the Dout register 34, and this data is output from the output buffer 0B35. Input data! ) -In register 36, passed to WA 30.

A Data Output Control (DOC) circuit 37 controls the high impedance state of the output buffer. CLK Ctrl 38 is a clock control circuit, and a clock control circuit such as a DLL is included therein.

Returning to the timing diagram of Fig. 1, the reference time of the falling edge of the Word line, which is another point shown in Fig. 1, will be described. Conventionally, as shown in Fig. 3, the word line was turned off after a certain delay time from time A. However, when the Word line is dropped as in the conventional method, when the sense amplifier is activated at the timing of the present invention, the cycle time (the interval between time A and time B) becomes longer. After the word line falls, the sense amplifier is activated, and the data of the sense amplifier cannot be correctly captured.

Therefore, when the sense amplifier is to be operated at high speed using the present invention and it is necessary to operate normally even with a long cycle time, (1) the sense amplifier activation control is returned to be determined from time A as before. Or (2) As shown in Fig. 1, there is a method in which the fall time of the Word line is also determined from the clock edge at time B. This will increase the cycle time Even so, the time at which the word line falls will never be earlier than the sense amplifier activation time, and it will operate normally.

In this specification, when it is referred to as clock edge, it refers to a time that is generally called a switching time of the clock in the specifications of the integrated circuit. For example, in the case of a memory whose clock input is differential, the definition may change depending on the specifications of the integrated circuit, such as indicating the time at which the differential signal is crossed.

After explaining the margin setting method in the comparative example with reference to FIG. 3, the effect obtained by the present embodiment will be described. The timing shown in FIG. 3 is different from that of the present invention in that the SACK, that is, the timing of the activation of the sense amplifier is determined based on time B in the case of FIG. 1, whereas the timing in FIG. It is determined based on A. In the case of SRAM, for example, the sense amplifier is started after a certain delay time from when the far-end lead line rises. In the method of Fig. 2, the margin 1 in the figure is always fixed because it is determined at the time of circuit design, and the best sense amplifier performance that matches the device performance cannot be obtained. Conversely, according to the present invention, since this margin 1 is not fixed at the time of design, a high-speed sense amplifier can be obtained. In addition, in order to obtain the highest performance that can be selected by the device in the conventional design, the margin 1 in Fig. 3 must be reduced as much as possible.However, if a malfunction occurs in the sense amplifier, it becomes a defective product. Become. This is due to the characteristics of the positive feedback sense amplifier. That is, according to this embodiment, it can be said that there is an advantage that it is possible to manufacture at low cost without increasing the ratio of defective products even in the case of the design aiming for the highest performance.

Figure 4 shows an example of a positive feedback type sense amplifier used in SRAM. Bit line 40 is directly connected to memory cell 41. Multiple bit line pairs are connected to one set of common bit lines using Y switches (MOS M13 and MOS M14). Connected to CDT and CDB. At the same time, when only one of these Y switches is turned ON, this sense amplifier amplifies the data of the selected bit line.

The operation of this circuit will be described below. When the SACM power is low, the MOS M10 power is off and the MOS Ml, M2, M3 are turned on, so that the output terminals 0UT1 and 0UT2 of this sense amplifier both go high. Next, when data from the memory cell is input to the gates of M0S M8 and MOS M9, the gate terminal turns on the M0S (eg, MOS M9) on the high side. The charge shear due to the parasitic capacitance of the source and drain of the MOS M9 causes the potential of 0UT1 to drop slightly, resulting in a small potential difference with 0UT2. The potential difference between 0UT1 and 0UT2 increases as the difference in gate potential between MOS M8 and M0S9 increases. M0S transistor amplifiers have offsets due to VTH device variation.To avoid malfunction, turn on the SACM after this voltage amplitude becomes as large as possible to prevent malfunction. There is a need. The amplitude voltage of the common bit line is determined by the current of the memory cell and the common bit line load circuit 43.

Normally, as shown in Fig. 1, it is impossible to generate a signal that precedes the reference time.However, in the case of a synchronous memory or the like, by taking advantage of the feature that the frequency in normal operation is constant, for example, Using a DLL (Delay Locked Loop) circuit, a PLL (Phase Locked Loop) circuit, or an SD (Synchronous Mirror Delay) circuit, it is possible to generate a signal that goes back from the reference time.

An example of clock signal generation according to the present invention will be described with reference to FIGS.

Figure 5 shows a block diagram when a DLL circuit is used. A first delay circuit 51 whose delay time varies according to the clock frequency; A constant second delay circuit 52 is used regardless of the frequency. From the clock input signal, the signal delayed by the delay time dl by the first delay circuit and the delay time determined by the delay time d2 by the second delay circuit is compared with the original clock signal by the phase comparator. CLK2 is output in phase with CLK1. Here, the phase is adjusted by the delay circuit dl whose delay time changes according to the information on the phase difference represented by VF output from the phase comparator 53, that is, the delay time changes according to the clock frequency. If the phase of clock CLK2 lags behind clock CLK1, the delay time of dl decreases, and vice versa. Here, the output time of CLK1 is always ahead of CLK2 by the amount corresponding to the delay time dl, and therefore, as shown in Fig. 1, the clock that is earlier than the given clock signal by a fixed time is used. A signal can be obtained.

Fig. 6 shows the operation timing of the configuration in Fig. 5. The phases of the clock input CLK and the clock signal CLK2 coincide with each other by the phase comparator and the delay circuit dl. It can be seen that the delay dl to CLK1 changes, but the delay time d2 from CLK1 to CLK2 is kept constant, and a signal CLK2 earlier than CLK by the delay time of d2 is obtained. In practice, it is common for a delay to be introduced between the external clock CLK and the phase comparator in the circuit of Fig. 5, and examples of this case are shown in Figs.

FIGS. 7 and 8 show examples in which the delay of the circuit 70 between the external clock CLK and the phase comparator in the circuit of FIG. 5 is considered. This delay time is denoted by dl in FIG. Other circuit configurations are denoted by the same reference numerals as in FIG. 5 and description thereof is omitted. In FIG. 7, the delay time changed by the phase information is d2, and the constant delay time included in the loop is d3. In this case, the time going back from the external clock is d3-1 dl as shown in the timing diagram of Fig. 8.

Figure 9 illustrates an example of SRAM timing without using a DLL. In the example of Figure 1 It is necessary to activate the sense amplifier retroactively from the reference clock time of DLL, SMD, etc., but the example in FIG. 9 is an example where such a special circuit is not required.

That is, since the rising edge of SACK for activating the sense amplifier is later than the reference clock edge, the SACK can be generated from the rising edge of the clock by a normal delay element. In addition, there is an advantage that the cycle time may be faster than or equal to the case of Fig. 1 and so on. However, in the case of the present embodiment, since the subsequent processing of the SA output starts after the time B, the time from the time B to the data output is longer than in the example of FIG. Conversely, in the example of Fig. 1, it can be said that this defect can be compensated for by using a circuit such as a DLL. Also in the example of FIG. 9, it can be seen that the magazine 1 is variable depending on the clock cycle time.

FIG. 10 shows an embodiment in which the present invention is applied to an SRAM having the functions of Double Data Rate (DDR) and Echo Clock. DDR is a memory that outputs Data at each rising edge and falling edge of the clock input, that is, a memory that outputs data at twice the frequency of inputs such as addresses. Furthermore, in the example of Fig. 10, the Echo Clock is used to suppress the skew of data and clock when the speed becomes high. Echo Clock aims to reduce the skew between the data itself and the reference clock for the data receiver by simultaneously outputting the reference signal that is the reference signal from the data output side. And

The operation of the SRAM using DDR and Echo Clock is basically the same as the SRAM in Fig. 1. The activation signal of the sense amplifier is determined based on the rising edge of the clock following time 1 (time 3). If time 2 is used for this, the activation of the sense amplifier will affect not only the frequency but also the duty of the input clock. It is better to use the time 3 or another start-up edge, as in this example, because the number of power parameters increases.

CLK0UT represents the output of the Echo Clock from the SRAM, and the rise time and fall time of each clock are determined by the rise time and fall time of the input clock CLK. The output is output in synchronization with each edge (Data output).

FIG. 11 shows an example of a block configuration for realizing the operation of the DDR SRAM of FIG. 10 described above. This is almost the same as the normal SRAM shown in Fig. 2, but the explanation focuses on the parts that have changed.

B1, B2, and B3 indicate Burst Control signal input terminals. Functions such as writing and chip selection are controlled by a combination of these signals. These signals are input to buffers 111 to 113.

BC110 indicates a burst control circuit. Burst refers to the function of internally generating multiple (for example, four) addresses for a single address received from the outside and accessing each address. The function of the BC is to generate an internal address for this purpose. In FIG. 11, the burst addresses are two bits, AO and A1, so four addresses are accessed.

In the example of Fig. 11, twice as many memory cells are accessed at the same time as in Fig. 2, and the read data is output twice consecutively. If a MUX is provided for each of the lowest addresses AO as shown in Fig. 11, a circuit that can function normally even in the case of DDR can be obtained.

FIG. 12 shows an embodiment in which the present invention is applied to a synchronous DRAM. The timing of input / output is determined according to the edge of CLK input from the outside as in the case of SRAM.

Synchronous DRAM (SDRAM) generally has multiple banks, When data is alternately read from banks, the switching time between banks is very short. The RAS signal falls at time 1 in the figure, and the word line address (Address) is input in synchronization with this. Therefore, it is determined based on time 1 as shown in the figure until the memory cell reaches the rising edge of the ド -line and the sense amplifier (SA output).

In the example in Figure 12, CAS input from the outside is input in the third cycle counting from time 1. The SACK signal should be raised before this CAS input. In this example, the reference clock edge is the rising edge of CLK at time 4; however, this time may be set in consideration of the following restrictions.

In the example shown in Fig. 12, the data output corresponding to the address input is output based on the clock at time 5. In other words, if the SACK is too slow, that is, if the SA output is too slow, subsequent processing may not be able to keep up with this Data output. However, if this timing is delayed with respect to time 4 (clock time of the reference clock edge), the ability of the cycle time up to this point, that is, the cycle time up to the latch of the sense amplifier, is improved. Therefore, the value of this delay time is a delay time that determines the trade-off between the access time from the clock to the data output and the cycle time.

The Word line is set to fall upon receiving the next bank selection signal (RAS goes low). In other words, normal operation can be assured by setting the falling timing of the Word line to a different edge from the rising edge of the clock that determines the timing of the rising edge.

Figure 13 shows the operation timing of the SDRAM using the present invention. FIG. 13 is also substantially the same as FIG. 12 except that the activation timing of the sense amplifier uses one cycle earlier than the case of FIG. As a result, the cycle time is faster than in the case of Fig. 12. Can respond.

In the current SDRAM, minimum time is specified as the interval between RAS and CAS input. However, in the case of the sense amplifier having the configuration according to the present invention, the absolute value of the time is not specified, but the number of cycles, that is, the minimum number of cycles after the RAS input before the CAS can be input and the specification. do it.

An advantage of the present embodiment is that it is possible to obtain an SDRAM having a short delay time from the access from the RAS, that is, the supply of bank information to the output of data.

Figure 14 shows another example. This timing example shows a timing example when the number of cycles from RAS to CAS is further reduced. According to this example, an SDRAM having a smaller number of access cycles than in FIGS. 12 and 13 can be obtained.

In the case of Fig. 12, Fig. 13, and Fig. 14, it is necessary to make the activation time of the sense amplifier backward from the reference time by the clock circuit such as DLL. It may be activated.

FIG. 15 shows an example in which the sense amplifier is activated after the reference clock. Even with such a configuration, if the peak frequency increases, the illustrated margins are automatically reduced, and the highest cycle performance determined by memory cell characteristics, decoder characteristics, sense amplifier characteristics, etc. There is an advantage that can be obtained. In addition, in this example, there is an advantage that it is not necessary to incorporate a somewhat complicated clock circuit such as a DLL or a PLL.

Figure 16 shows another SDRAM timing example. This figure shows the timing of the internal operation when there is a switch between two banks. An example is shown in which the clock access, time, and switching time between banks have the minimum number of cycles under the condition that no data collision occurs at the output pin. Next, an example in which the present invention is applied to a cache memory built in a microcomputer will be considered. In a microcomputer, it is generally controlled by a PLL, and is controlled by a signal with a fixed phase. In the PLL used in the present invention, a PLL including both a delay circuit whose delay time varies depending on the frequency in the loop and a delay circuit having a constant delay time without changing the delay time is required. .

A microcomputer incorporating such a PLL can incorporate the cache memory of the present invention.

By incorporating the cache memory according to the present invention into a microcomputer, the high-speed cycle performance of the cache memory, which is determined only by the limitations of the device, can be obtained.

As another embodiment of the present invention, a DRAM with built-in logic can be configured. That is, the present invention can be applied to a microcomputer or a DRAM integrated with a logic circuit such as a graphic circuit.

According to this example, the cycle time of the microcomputer is limited, and the cycle time of the cache memory is improved. As a result, the operation time of the microcomputer can be improved.

Next, another example of the arrangement of the clock synchronization circuit will be described.

FIG. 17 shows an example of a chip layout in an SRAM. There are three rows of input / output pads on the center and on both sides of the chip. The input of address and control signals is mainly from the center pad row, data output, and Echo Clock output. Pad rows. As a result, the signal propagation distance from the data input to the output is shortened, and the cycle time can be shortened.

Clock synchronization circuits such as DLL and SMD are located at the center of the pad on both sides. Provide. This reduces the distance to the output pad and reduces the skew between clock and data.

Figure 18 shows an example of application to Register-Latch (R / I type synchronous DRAM).

An RZL type synchronous DRAM is a type in which the input to the memory is a register type, that is, the value at the edge of the rising or falling edge of the clock input is fetched, and the output from the memory is the data when the clock signal is high. This type of synchronous memory is fixed to the output color and the output color is in a through state when the clock signal is low.

In this case, unlike the case of Fig. 1, the sense amplifier makes the output pin undefined based on the time 2, that is, the falling edge of the clock signal in Fig. 18. Unlike this, the operation may be performed based on the falling time 2 of the clock signal. As a result, as in the other embodiments of the present invention, the time between time 1 and time 2 in FIG. 18 fluctuates, and this causes the SACK to go back and forth as it is. The time from the activation of the line to the activation of the sense amplifier can be controlled in proportion. For this reason, the sense amplifier activation time shifts forward with an increase in the cycle time, so that the sense amplifier activation margin can be increased or decreased with an increase in the clock speed.

Figure 19 shows an example of application to Register-Through (R / T) type synchronous memory.

R / T type synchronous memory is a type of memory that uses registers for signal input but does not use registers or latches for output. In this case, as shown in Figure 19, only the time determined by the input register That is, valid output data is held only while valid data is held on the lead line. Therefore, compared with the R / L type and R / R type, the output data holding time is shorter, but the absolute time from address to data output can be shortened.

As shown in Fig. 19, the activation time of the sense amplifier, that is, the reference time of SACK is the edge of the clock signal, but the input signal is fetched and the next edge occurs, during which the clock signal is high. The shorter the time, the shorter the time from the rise of the lead line to SACK.

FIG. 20 shows the relationship between the lead line and the bit line when writing to the synchronous memory. As shown in FIG. 20, according to the present invention, when the gate line rises based on time 1 and falls based on time 3, according to the present invention, the bit line also falls based on the same time as the word line. . According to this method, the time of the word line and the bit line can be relatively synchronized, and the time between the word line and the bit line can be changed due to process changes, power supply voltage changes, temperature changes, and other conditions. This enables a design in which a change in relative time is small. This has the effect that the circuit operates at higher speed and malfunctions are less likely to occur due to variations in characteristics of the MOS device and the like.

FIG. 21 shows another embodiment of the present invention in which a synchronous mirror delay (SMD) circuit is used. SMD is a circuit for generating an internal clock signal synchronized with a supplied external clock signal, and has been announced at conferences such as ISSCC'96. Compared to other synchronous clock signal generation circuits such as PLL and DLL, it has the feature that a synchronized internal circuit can be obtained with as few as two cycles.

Figure 21 shows a typical SMD circuit. Internal clock signal whose phase is synchronized with the external clock two cycles (2tCK) later than the external input clock Occurs. One of the problems of this method is its accuracy. In order to improve the accuracy of the synchronization of the internal clock signal with the external clock signal, the delay time per stage of the delay circuit constituting the foward delay 2 12 and backward delay 2 14 shown in Fig. 21 must be shortened. This requires a very short delay circuit. That is, it is difficult to synchronize the output clock signal with the input clock signal with an accuracy equal to or less than the minimum unit delay time that can be generated by the gate circuit.

In this embodiment, the SMD and the DLL are combined, and a clock signal with a roughly accurate combination is generated by the SMD, and this is further improved by the DLL. As a result, the accuracy of the internal clock signal, which is limited by the minimum delay per stage, which is a problem in SMD, can be dramatically improved.

Fig. 22 shows a specific example. The external input and the output signal of the SMD are input to the phase comparator 222, and the output controls the output signal of the SMD with the voltage control delay circuit 220 to more accurately match the external clock signal. Can generate an internal clock signal. Compared to Fig. 21, the delay time in delay b2 15 is set not d2 but to a shorter time (d2 d3). The total sum at this time is

dl ltCK + (tCK-dl -d2) + d2-d3} d (VCD) = 2tCK-d3 + d (VCD)

Becomes Here, d (VCD) indicates a delay time by the voltage control delay circuit 220. Therefore, if d (VCD) can be adjusted to d3, the internal clock is synchronized with the external clock.

According to this embodiment, there is an effect that the time until an internal clock signal synchronized with the clock input signal is generated can be shortened as compared with the case where only the DLL is used. In addition, according to the present embodiment, since the SMD circuit finely adjusts the clock signal having almost the same phase, a relatively large number of cycles are required to generate the internal clock, which is a disadvantage of the DLL. Can solve a certain problem You.

In addition, the delay time assigned to the VCO (Voltage Controlled Delay) part, in which the delay time is changed by voltage using the DLL, is smaller than that of a normal DLL only. Thus, the output accuracy can be improved.

Industrial applicability

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

That is, a sense amplifier circuit with the highest performance determined by the performance of the device can be realized without the side effect of decreasing the yield. Another advantage of the present application is that even if the device performance is changed after the design is completed, the best characteristics of each device performance can be obtained, that is, there is no need to determine the operation margin of the sense amplifier at the design stage. Be

Claims

The scope of the claims

1. A clock terminal to which a clock signal is input, and an internal circuit to which a signal to be processed is input, wherein the signal to be processed is referred to as the internal circuit based on a first time of the click signal. And a synchronous integrated circuit that operates the internal circuit based on a second time of the quick signal.

2. When the signal to be processed is input to the internal circuit at the third time and the internal circuit is operated at the fourth time, the time interval between the first time and the third time is constant. 2. The synchronous integrated circuit according to claim 1, wherein a time interval between the second time and the fourth time is constant.

3. The synchronous integrated circuit includes a memory array including a plurality of memory cells specified to be read by an address signal, and a sense amplifier that amplifies a signal read from the memory cell specified by the address signal, The signal to be processed is a signal read from the memory cell; the internal circuit is the sense amplifier; and the address signal specifies the memory cell based on the first time. 2. The synchronous integrated circuit according to claim 1, wherein an amplification operation of said sense amplifier is started based on said second time.

4. A decoder which decodes the address at the first time and decodes a signal read from a memory cell designated by the decoded address with reference to the second time. 4. The synchronous integrated circuit according to claim 3, wherein the amplification is performed by the sense amplifier that has started the operation.

5. The time at which a signal is read from the memory cell designated by the decoded address and the time at which amplification of the sense amplifier is started are changed by the cycle time of the clock signal. Item 4. The synchronous integrated circuit according to item 4.

6. The first time is the first rising time of the clock signal pulse, and the second time is the second rising time of the clock signal pulse.

twenty three

盯 Corrected paper (Rule 91) The synchronous integrated circuit according to any one of claims 1 to 5, wherein the rising time is a rising time, and the second rising is a rising of a pulse next to the first rising.

7. A semiconductor memory device operating based on a clock signal, comprising: a plurality of memory cells for storing information; a decoder for decoding an address signal for designating at least one of the memory cells; An output line for outputting an output signal reflecting information stored in a memory cell designated by the address signal; and an amplifier for amplifying the output signal. Decoding the address signal at time 1, the output line outputs the output signal at a second time that is a predetermined time after the first time, and the amplifier outputs a second signal different from the first time. A semiconductor memory device that is activated at a fourth time that is shifted by a predetermined time from the time of 3.

8. The first time is the rising or falling edge of the first pulse of the close signal, and the third time is after the first pulse of the close signal. 8. The semiconductor memory device according to claim 7, wherein the rising edge or the falling edge of the second pulse.

9. The semiconductor memory device according to claim 7, wherein the amplifier is activated at a fourth time which is a predetermined time before a third time different from the first time.

10. The semiconductor memory device according to claim 7, wherein the amplifier is activated at a fourth time, which is a predetermined time after a third time different from the first time.

11. The semiconductor memory device according to claim 8, wherein the first pulse and the second pulse are continuous pulses.

12. The semiconductor memory device according to claim 7, wherein the amplifier amplifies by applying positive feedback.

13. The timing of the fourth time is formed by processing the clock signal by an LL circuit, an SMD circuit, or a PLL circuit.

twenty four

Π * Correct paper (Rule 91) 13. The semiconductor memory device according to any one of to 12.

14. The DLL circuit or the PLL circuit includes a first delay circuit whose delay time varies depending on the frequency of the clock signal, and a delay time independent of the frequency of the clock signal. 14. The semiconductor memory device according to claim 13, further comprising a fixed second delay circuit.

15. A plurality of memory cells each having a lead line connected thereto, and the lead lines are not selected on the basis of the third time. 3. The semiconductor memory device according to claim 1.

16. In a synchronous integrated circuit having a sense amplifier to which an activation time is inputted from the outside, a time different from the time based on the input time of a signal to be amplified by the sense amplifier is used as a reference. A synchronous integrated circuit characterized by activating a sense amplifier.

17. The reference of the activation time of the sense amplifier is a reference next to a reference which is based on an input time of a signal to be amplified. Synchronous integrated circuit

18. In a synchronous integrated circuit having a sense amplifier whose activation time is designated by an external clock signal, the absolute value of the amount of change in the clock cycle of the clock signal and the activation of the sense amplifier A synchronous integrated circuit in which the time interval between the activation time and the input time of the signal to be amplified to the sense amplifier changes correspondingly.

19. Synchronous cook signal generating circuit having a phase comparator and a variable delay circuit controlled by the phase comparator, wherein an input signal and an output of a synchronous mirror delay circuit are applied to the input signal of the phase comparator. A synchronous clock signal generating circuit using a signal and using a variable delay circuit controlled by the output of the phase comparator as a part of the delay circuit in the synchronous mirror delay circuit.

20. A semiconductor memory device which operates based on a clock signal, comprising a plurality of memory cells for storing information, data lines and read lines connected to the memory cells, and an output signal of the data line. With a sense amplifier

When reading information from the memory cell, the data line outputs the output signal at a second time that is a predetermined time after the first time of the quick signal, and the sense amplifier outputs the first signal. A semiconductor memory device that is activated at a fourth time shifted by a predetermined time from a third time different from the third time.

21. At the time of writing information to the memory, the data line rises at a fifth time which is different from the first time of the close signal by a predetermined time, and The second line is dropped at a sixth time that is different from the second time by a predetermined time, and the lead line is raised at a second time that is different from the first time of the click signal by a predetermined time. 20. The semiconductor memory device according to claim 19, wherein the signal falls at an eighth time that is different from the second time of the signal by a predetermined time.

22. The semiconductor memory device according to claim 20, wherein the memory cell is an SRAM or a DRAM.