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“The QuickDSP Design Guide”, Quicklogic, Aug. 2001, revision B. “QuickDSPTM Family Data Sheet”, Quicklogic, Aug. 7, 2001, revision B.

Rangasayee, K., “Complex PLDs let you produce efficient arithmetic designs,”EDN(European Edition), vol. 41, No. 13, Jun. 20, 1996, pp. 109,110,112,114,116.

Ro sado, A, et al., “A high-speed multiplier coprocessor unit based on FPGA,”Journal ofElectricalEngineering, vol. 48, No. 11-12, 1997, pp. 298-302.

Santillan-Q., G.F., et al., “Real-time integer convolution implemented using systolic arrays and a digit-serial architecture in complex programmable logic devices,” Proceedings of the Third International Workshop on Design ofMixed-Mode Integrated Circuits and Applications (Cat. No. 99EX303), Jul. 26-28, 1999, pp. 147-150. Texas Instruments Inc., “TMS320C54x DSP Reference Set, vol. 1: CPU and Peripherals”, Literature No. SPRU131F, Apr. 1999, pp. 2-1 through 2-16 and 4-1 through 4-29.

Tisserand, A., et al., “An on-line arithmetic based FPGA for low power custom computing,” Field Programmable Logic and Applications, 9th International Workshop, FPL '99, Proceedings (Lecture Notes in Computer Science vol. 1673), Lysaght, P., et al., eds., Aug. 30-Sep. 1, 1999, pp. 264-273.

Tralka, C., “Embedded digital signal processor (DSP) modules in programmable logic devices (PLDs),” Elektronik, vol. 49, No. 14 , Jul. 11, 2000, pp. 84-96.

Valls, J ., et al., “A Study About FPGA-Based Digital Filters,” Signal Processing Systems, 1998, SIPS 98, 1998 IEEE Workshop, Oct. 10, 1998, pp. 192-201.

“Virtex-II 1.5V Field-Programmable Gate Arrays”, )filinx, Jan. 25, 2001, module 2 of4.

“Virtex-II 1.5V Field-Programmable Gate Arrays”, )filinx, Apr. 2, 2001, module 1 of4.

“Virtex-II 1.5V Field-Programmable Gate Arrays”, )filinx, Apr. 2, 2001, module 2 of4.

Walters, A.L., “A Scaleable FIR Filter Implementation Using 32-bit Floating-Point Complex Arithmetic on ,a FPGA Based Custom Computing Platform,”Allison L. Walters, Thesis Submitted to the Faculty of Virginia Polytechnic Institute and State University, Jan. 30, 1998.

Wenzel, L., “Field programmable gate arrays (FPGAs) to replace

digital signal processor integrated circuits,” Elektronik, vol. 49, No.

5, Mar. 7, 2000, pp. 78-86.

“Xilinx Unveils New FPGA Architecture to Enable High-Perfor

mance, 10 Million System Gate Designs”, )filinx, Jun. 22, 2000.

“Xilinx Announces DSP Algorithms, Tools and Features forVirtex-II

Architecture”, )filinx, Nov. 21, 2000.

Xilinx Inc., “Virtex-II 1.5V Field-Programmable Gate Arrays”,

Advance Product Specification, DS031-2 (v1.9), Nov. 29, 2001,

Module 2 of 4, pp. 1-39.

Xilinx Inc., “Using Embedded Multipliers”, Virtex-II Platform

FPGA Handbook, UG002 (v1.3), Dec. 3, 2001, pp. 251-257.

Xilinx, Inc., “A 1D Systolic FIR,” copyright 1994-2002, downloaded

from http://wvvw.iro.umontreal.ca/~aboulham/F6221/

Xilinx%20A%201D%20systolic%20FIR.htm.

Xilinx, Inc., “The Future of FPGA’s,” White Paper, available Nov.

14, 2005 for download from http://www.xilinx.com/prs_

rls,5yrWhite.htm.

Weisstein, E.W., “Karatsuba Multiplication,” MathWorld—A Wolfram Web Resource (Dec. 9, 2007), accessed Dec. 11, 2007 at http://

mathworld.wolfram. com/KaratsubaMultiplication.html.

Altera Corporation, “DSP Blocks in Stratix II and Stratix II GX

Devices ” Stratix II Device Handbook, vol. 2, Chapter 6, v4.0 (Oct.

2005).

Underwood, K. “FPGAs vs. CPUs: Trends in Peak Floating-Point

Performance,” Proceedings of the 2004 ACM/SIGDA 12th Interna

tional Symposium on Field Programmable GateArrays, pp. 171-180,

Feb. 22-24, 2004.

Xilinx Inc., “XtremeDSP Design Considerations User Guide,” v 1.2,

Feb. 4, 2005.

Altera Corporation, “Statix II Device Handbook, Chapter 6—DSP

Blocks in Stratix II Devices,” v1.1, Jul. 2004.

Xilinx Inc., “Complex Multiplier v2.0”, DS291 Product Specifica

tion/Datasheet, Nov. 2004.

Haynes, S.D., et al., “Configurable multiplier blocks for embedding

in FPGAs,” Electronics Letters, vol. 34, No. 7, pp. 638-639 (Apr. 2,

1998).

Altera Corporation, “FIR Compiler: MegaCore® Function User

Guide,” version 3.3.0, rev. 1, pp. 3 11 through 3 15 (Oct. 2005).

* cited by examiner

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