Referring to FIG. 1, a silicon layer 12, which is a single crystal silicon, and a buried insulating oxide layer 11 (e.g.. silicon dioxide) are formed on a P-type silicon substrate 10. The silicon layer 12 and insulating layer 11 together constitute the silicon on insulator (SOI) structure 1. The SOI structure 1 can be provided by any conventional technique for fabricating SOI structures. For instance, the SOI structure 1 may be formed by implanting a high concentration of oxygen into bulk substrate 10 by conventional SIMOX technique. Alternatively, the SOI structure 1 can be formed by a conventional bond and etch back process. These and other conventional techniques for forming SOI structures are described, e.g.. in U.S. Pat. No. 5.241.211. which descriptions are incorporated herein by reference. The SOI structure 1, as formed on a bulk semiconductor substrate, can be incorporated into the inventive process flow as a preformed SOI wafer. The thickness of the buried oxide layer 11 and silicon layer 12 can vary depending on the device requirements. Generally, the thickness of the silicon layer 12 ranges from approximately 500A to 5.000A, and the thickness of the buried oxide layer 13 ranges from approximately 500A to 1 um. A pad oxide layer 13 (e.g.. silicon dioxide) of approximately 8 nm thickness and a pad nitride layer 14 (e.g.. silicon nitride) of approximately 100 nm thickness are sequentially deposited on the silicon layer 12.
A photosensitive layer 15 (e.g.. a photoresist), as shown in FIG. 2, is coated on nitride layer 14 and developed to define a pattern of capacitor trenches. Using the patterned photoresist, the pattern of capacitor trenches 18 is transferred to the nitride layer 14. By anisotropic etching, the pattern is transferred through the pad oxide 13, silicon layer 12, buried oxide layer 11 and ultimately into the underlying silicon substrate 10 to form capacitor trenches 18. The depth of the trenches 18 in the bulk silicon substrate 10 is determined by the desired capacitance. The intermediate construction at this stage of fabrication is shown in FIG. 2. The photoresist 15 is removed at this juncture.
A protective photoresist layer (not shown) is then deposited on upper exposed surface areas of the wafer followed by removal of the photoresist in both the trench regions defining the capacitor trenches 18 and from SOI nitride pad 14 at its areas adjacent the capacitor trenches 18 to expose both these areas for an N+ implant. The patterned remainder of the protective photoresist is not seen in FIG. 2 since it is located outside and defines openings at the capacitor areas of present interest.
As indicated in FIG. 3. an N+ implantation is performed across the surface of the device. The N+dopant or impurity preferably is a high dose of phosphorus, although, alternatively, other Group 1HA or VA species such as boron or arsenic could be used as the dopant. As shown in FIG. 4. the implant dopant penetrates into both the exposed areas at the trench bottom to form N+ regions 16 and also through nitride layer 14/pad oxide 13 into the SOI surface areas adjacent to the trenches 14 to form N+ zone 17 in the upper surface area of silicon layer 12. The phosphorus implant is performed at an ion energy level of between 5 and 50 KeV and at an ion dose between 1.0E13 and 1.0E15 per cm2. The energy is selected such that the peak of the implant lies in the silicon layer 12 adjacent to the trench capacitors (not covered by photoresist). The protective photoresist used at this stage of fabrication blocks the implant from other areas which will later contain active devices, but which are not shown in the present figures as they concern features unessential for obtaining an understanding of the present invention. As can be appreciated, an alternative arrangement for this invention can involve use of a N Type Si substrate 10
and use of a P type implantation dopant to form P+ regions 16 and a P+ zone 17 in the upper surface area of silicon layer 12.
Thermal budget encountered in subsequent processing 5 steps described herein will effectively cause diffusion of the implanted phosphorus such that a continuous N-region 16 will be formed from the trench to trench, and. silicon layer 12 will become doped throughout by diffusion of dopant in N+ zone 17. as best seen in FIG. 7.
10 Returning to the process flow description, following the removal of the protective photoresist used for implantation of N+ regions 16 and 17, the exposed silicon surfaces of the capacitor trenches 18 are cleaned up with a short sacrificial oxidation and etch. A thin composite nitride/oxide capacitor
15 dielectric layer 19 is then formed using a conventional technique on the walls of the trenches 18 and on the surface of nitride pad layer 14. as seen in FIG. 4, using conventional processing methods employed in DRAM fabrication. For example, dielectric layer 19 can be formed by depositing
20 about 5 nm of nitride followed by nitride reoxidation to grow about 3 nm of overlying oxide.
A capacitor plate mask 21 is then used to define the trenches, such as trench 18a indicated in FIG. 5. which will be used to contact the lower diffused capacitor plate 16
25 shown in FIGS. 7 and 8. The thin dielectric layer 19 is removed from these trenches as well as the surrounding nitride pad material of pad layer 14 and thin pad oxide 13 as best seen in FIG. 5 to expose surfaces 17' of N+ silicon layer 17. While FIG. 5 shows removal of dielectric layer 19
30 portions from both the trench sidewalls and bottom of trench 18A, it will be understood that the dielectric layer 19 need not be removed from the bottom of trench 18A as long as portions of dielectric layer 19 are removed effective to expose edges of silicon layer 17 and semiconductor sub
35 strate 10 which bound and help define trench 18A.
In a preferred embodiment, the etching for this step is a single predominantly directional etch step with a small isotropic component for nitride layer 14 and the thin layer of pad oxide 13 selective to silicon. The small isotropic com
40 ponent is needed to remove the capacitor dielectric component 19 from the trench sidewalls of trench 18A. The etchant chemistry for this step can be a plasma derived from a gas mixture of CF4+CHF3+0 2+Ar. which has an approximately 10:1 selectivity to silicon and which will remove the
45 approximately 8 nm of pad oxide layer 13 as well as the capacitor dielectric 19 from the inside of the unprotected trench 18A. Photoresist may be used as the etch mask 21 for this step. Alternatively, another type of masking layer, which later can be removed selectively to silicon, silicon dioxide
50 and silicon nitride, e.g., polyimide patterned by a photoresist layer, also may be used for this etch step.
Following stripping of the capacitor plate photoresist mask 21, N+ in situ doped polysilicon 20 is deposited in the trenches 18, 18A and polished back to the top of the pad
55 nitride 14 as shown in FIG. 6. Alternatively, undoped polysilicon can be filled in the trenches 18,18A and polished back before an N+ implant is performed in conjunction with an implantation mask to dope the polysilicon previously filled into the trenches. The polysilicon trench fill 20 con
60 tacts the exposed silicon surfaces 17'. This contact formed between the doped polysilicon 20 filling trench 18A and the exposed silicon surfaces 17' also provides a low thermal resistance path (i.e., a high thermal conduction path) between silicon layer 12 and the merged diffusion region 16
65 of substrate 10.
Shallow trench isolation (STT) 23, as indicated in FIG. 9, is then defined outside and bounding the capacitor areas of