A preferred arrangement is one in which the error-recovery logic operates to force the delay value to be stored in the non-delay latch in place of the non-delayed value.
Whilst the present technique is applicable to both synchronous and asynchronous data processing circuits, the invention 5 is well suited to synchronous data processing circuits in which the processing operations within the processing stages are driven by a non-delayed clock signal.
In the context of systems in which the processing stages are driven by the non-delayed clock signal, the error-recovery 10 logic can utilize this to facilitate recovery from an error by gating the non-delayed clock signal to provide sufficient time for the following processing stage to recover from input of the incorrect non-delayed value and instead use the correct delayed value. 15
In the context of embodiments using a non-delayed clock signal, the capture times can be derived from predetermined phase points in the non-delayed clock signal and a delayed clock signal derived from the non-delayed clock signal. The delay between the non-delayed capture and the delayed cap- 20 ture can be defined by the phase shift between these two clock signals.
The present technique is particularly well suited to embodiments in which the processing stages are respective pipeline stages within a synchronous pipeline. 25
The detection and recovery from errors can be used in a variety of different situations, but is particularly well suited to situations in which it is wished to dynamically control operating parameters of an integrated circuit in dependence upon the detection of such errors. Counter intuitively, the present 30 technique can be used to control operating parameters such that the system operates with a non-zero error rate being maintained as the target rate since this may correspond to an improved overall performance, either in terms of speed or power consumption, even taking into account the measures 35 necessary to recover from occurrence of errors.
The operating parameters which may be varied include the operating voltage, an operating frequency an integrated circuit body biased voltage (which controls threshold levels) and temperature amongst others. 40
In order to ensure that the data captured in the delayed latch is always correct, an upper limit on the maximum delay in the processing logic of any stage is such that at no operating point can the delay of the processing logic of any stage exceed the sum of the clock period plus the amount by which the delayed 45 capture is delayed. As a lower limit on any processing delay there is a requirement that the processing logic of any stage should have a processing time exceeding the time by which the delayed capture follows the non-delayed capture so as to ensure that following data propagated along short paths does 50 not inappropriately corrupt the delayed capture value. This can be ensured by padding short paths with one or more delay elements as required.
The present technique is applicable to a wide variety of different types of integrated circuit, such as general digital 55 processing circuits, but is particularly well suited to systems in which the processing stages are part of a data processor or microprocessor.
In order to facilitate the use of control algorithms for controlling the operational parameters preferred embodiments 60 include an error counter circuit operable to store a count of the detection of errors corresponding to a change in the delayed value compared with the non-delayed value. This error counter may be reached by software to carry out control of the operational parameters. 65
It will be appreciated that the delayed latch and non-delayed latch discussed above could have a wide variety of
different forms. In particular, these may be considered to include embodiments in the form of flip-flops, D-type latches, sequential elements, memory cells, register elements, combinations thereof and a wide variety of other storage devices which are able to store a signal value.
Viewed from another aspect the present invention provides a method of controlling an integrated circuit for performing data processing, said method comprising the steps of:
supplying a processing stage output signal from at least one processing stage of a plurality of processing stages as a processing stage input signal to a following processing stage, said at least one processing stage operating to:
perform a processing operation with data processing logic upon at least one processing stage input value to generate a processing logic output signal;
capture a non-delayed value of said processing logic output signal at a non-delayed capture time, said non-delayed value being supplied to said following processing stage as said processing stage output signal following said non-delayed capture time;
capturing a delayed value of said processing logic output signal at a delayed capture time later than said non-delayed capture time;
comparing said non-delayed value and said delayed value to detect a change in said processing logic output signal following said non-delayed capture time indicative of said processing logic not having finished said processing operation at said non-delayed capture time; and
when said change is detected, performing an error-recovery operation suppressing use of said non-delayed value by said following processing stage.
The above, and other objects, features and advantages of this invention will be apparent from the following detailed description of illustrative embodiments which is to be read in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 schematically illustrates a plurality of processing stages to which the present technique is applied;
FIG. 2 is a circuit block diagram schematically illustrating a circuit for use in the present technique;
FIG. 3 is a circuit diagram schematically illustrating a non-delayed latch and a delayed latch together with an associated comparator and error-recovery logic; and
FIGS. 4A and 4B are a flow diagram schematically illustrating the operation of the circuit of FIG. 1.
DESCRIPTION OF THE PREFERRED
FIG. 1 illustrates a part of an integrated circuit, which may be a part of a synchronous pipeline within a processor core, such as an ARM processor core produced by ARM limited of Cambridge, England. The synchronous pipeline is formed of a plurality of like processing stages. The first stage comprises processing logic 2 followed by a non-delayed latch 4 in the form of a flip-flop together with a comparator 6 and a delayed latch 8. Subsequent processing stages are similarly formed. A non-delayed clock signal 10 drives the processing logic and non-delayed latches 4 within all of the processing stages to operate synchronously as part of a synchronous pipeline. A delayed clock signal 12 is supplied to the delayed latches 8 of the respective processing stages. The delayed clock signal 12 is a phase shifted version of the non-delayed clock signal 10. The degree of phase shift controls the delay period between the capture of the output of the processing logic 2 by the