COMPONENT PACKAGING APPARATUS,
SYSTEMS, AND METHODS
This application is a divisional of U.S. patent application Ser. No. 10/750,459, filed Dec. 31, 2003 now U.S. Pat. No. 7,365,414, which claims the benefit of priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application Ser. No. 60/525,935, filed on Dec. 1, 2003, both of which are incor- 10 porated herein by reference.
This disclosure is related to pending U.S. patent applica- 15 tion Ser. No. 10/750,534, titled "Component Packaging Apparatus, Systems and Methods," by Peter A. Davison and Paul A. Koning, filed on Dec. 31, 2003, and is assigned to the assignee of the embodiments disclosed herein, Intel Corporation. 20
Various embodiments described herein relate to component packaging generally, including apparatus, systems, and methods used for integrated circuit packages.
Electronic chips typically need to be packaged in a package that provides an electric circuit between each electrical con- 30 nection from the chip and an external connector such as a pin or a ball extending from the package to external circuitry such as a printed-circuit board. The circuitry on the chip, particularly a very fast chip such as a microprocessor, generates a considerable amount of heat. Typically, the circuitry and elec- 35 trical connections for a chip are provided on one face of the chip. Sometimes, the majority of heat is removed from the opposite face of the chip.
The circuit side of the chip typically provides pads that are connected to the chip' s packaging using, for example, solder- 40 ball connections, which provide connections for electrical power and for input-output signals. The opposite, or back, side of the chip can have a heatsink or other heat-removing device attached, providing heat elimination. For some systems, a thermal-interface material (TIM) is used to attach a 45 heat spreader to the back of an IC chip. In some systems a second thermal-interface material is used to attach a heat sink to the heat spreader.
A package for a chip or chips typically has a non-conductive substrate (such as a plastic film or layer, or a ceramic 50 layer) with conductive traces above a surface of the substrate. Package wiring is becoming smaller, multilayered, and denser. Either solder-ball connections or wirebonds connect a chip to the package. Some packages include multiple chips, such as one or more logic or processor chips, one or more 55 communications chips (such as for a cell phone or wireless LAN), and/or one or more memory chips, such as DDR RAMs (double-data-rate random-access memories, which are typically volatile and lose their contents when power is removed) and/or a FLASH-type reprogrammable non-vola- 60 tile memory. Optionally, a cover or encapsulant is used to enclose parts or all of the chip or chips.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-section schematic view of a portion of an imprinting foil 100.
FIG. 2 is a close-up cross-section schematic view of a portion of imprinting foil 100.
FIG. 3 is a cross-section schematic view of a substrate 300.
FIG. 4 is a cross-section schematic view of substrate 300 and imprinting foils 100.
FIG. 5 is a cross-section schematic view of substrate 300 being embossed.
FIG. 6 is a cross-section schematic view of embossed substrate 600.
FIG. 7 is a cross-section schematic view of etched embossed substrate 700.
FIG. 8 is a cross-section schematic view of coated substrate 800.
FIG. 9 is a cross-section schematic view of plated substrate 900.
FIG. 10 is a cross-section schematic view of planarized substrate 1000.
FIG. 11 is a cross-section schematic view of a packaged circuit 1100.
FIG. 12 is a perspective exploded view of computer system 1200 using circuit 1100.
FIG. 13 is a cross-section schematic view of an exemplary dielectric film 310.
FIG. 14 is a side schematic view of an exemplary embossing machine 1400.
In the following detailed description of the various embodiments, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration some exemplary embodiments in which the subject matter may be practiced. It is understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.
The leading digit(s) of reference numbers appearing in the Figures generally corresponds to the Figure number in which that component is first introduced, such that the same reference number is used throughout to refer to an identical component which appears in multiple Figures. The same reference number or label may refer to signals and connections, and the actual meaning will be clear from its use in the context of the description.
The terms chip, die, integrated circuit, monolithic device, semiconductor device, and microelectronic device, are used interchangeably in this description.
The terms metal line, trace, wire, conductor, signal path and signaling medium are all related. The related terms listed above, are generally interchangeable, and appear in order from specific to general. In this field, metal lines are sometimes referred to as traces, wires, lines, interconnect or simply metal. Metal lines, generally copper (Cu) or an alloy of Cu and another metal such as nickel (Ni), aluminum (Al), titanium (Ti), molybdenum (Mo), or stacked layers of different metals, alloys or other combinations, are conductors that provide signal paths for coupling or interconnecting, electrical circuitry. Conductors other than metal are available in microelectronic devices. Materials suchas doped poly silicon, doped single-crystal silicon (often referred to simply as diffusion, regardless of whether such doping is achieved by thermal diffusion or ion implantation), titanium (Ti), molybdenum (Mo), and refractory metal silicides are examples of other conductors.