US 7,313,583 B2 Dec. 25, 2007
GALOIS FIELD ARITHMETIC UNIT FOR
USE WITHIN A PROCESSOR
Inventors: Joshua Porten, Palo Alto, CA (US);
Won Kim, Union City, CA (US); Scott
D. Johnson, Mountain View, CA (US);
John R. Nickolls, Los Altos, CA (US)
Assignee: Broadcom Corporation, Irvine, CA
(US)
Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 559 days.
Appl. No.: 10/460,599
Filed: Jun. 12, 2003
Prior Publication Data
US 2004/0078411 Al Apr. 22, 2004
Related U.S. Application Data
Provisional application No. 60/420,236, filed on Oct. 22, 2002.
Int. CI.
G06F15/00 (2006.01)
H03M13/00 (2006.01)
U.S. CI 708/492; 714/784
Field of Classification Search 708/492;
714/781, 784 See application file for complete search history.
A Galois field arithmetic unit includes a Galois field multiplier section and a Galois field adder section. The Galois field multiplier section includes a plurality of Galois field multiplier arrays that perform a Galois field multiplication by multiplying, in accordance with a generating polynomial, al!< operand and a 2nd operand. The bit size of the Ist and 2nd operands correspond to the bit size of a processor data path, where each of the Galois field multiplier arrays performs a portion of the Galois field multiplication by multiplying, in accordance with a corresponding portion of the generating polynomial, corresponding portions of the Ist and 2nd operands. The bit size of the corresponding portions of the Is' and 2nd operands corresponds to a symbol size of symbols of a coding scheme being implemented by the corresponding processor.
7 Claims, 10 Drawing Sheets
