« PreviousContinue »
(12) United States Patent ao) Patent No.: Us 7,348,215 B2
Lee (45) Date of Patent: *Mar. 25,2008
FOREIGN PATENT DOCUMENTS
EP 0475022 Al 3/1992
Isaak, H. et al., "Development of Flex Stackable Carriers" IEEE Electronic Components and Technology Conference, 2000 Proceedings 50fh, May 21, 2000-May 24, 2000, Las Vegas, NV, USA, pp. 387-384, IEEE Catalog No.: 00C1137070.
Primary Examiner—Scott B. Geyer
(74) Attorney, Agent, or Firm—TraskBritt
A method for assembly and packaging of one or more flip chip-configured semiconductor dice with an interposer substrate to form a flip chip-type semiconductor device assembly. The flip chip-type semiconductor device assembly includes a conductively bumped semiconductor die and an interposer substrate having a plurality of recesses formed therein. The semiconductor die is mounted to the interposer substrate with the conductive bumps disposed in the plurality of recesses so that the die face is adjacent the facing surface of the interposer substrate. One or more openings may be provided in an opposing surface of the interposer substrate which extend to the plurality of recesses and the conductive bumps disposed therein. Dielectric filler material may then be introduced through the one or more openings to the recesses and, optionally, between the semiconductor die and interposer substrate.
36 Claims, 13 Drawing Sheets
Australian Patent Office, Search Report, May 30, 2003, 4 pages. U. S. Patent Application entitled Microelectronic Devices and Methods of Manufacture, filed Aug. 30, 2001, U.S. Appl. No. 09/944,465.
Al-Sarawi et al., "A review of 3-D packaging technology," Components, Packaging, and Manufacturing Technology, Part B: IEEE Transactions on Advanced Packaging, vol. 21, Issue 1, Feb. 1998, pp. 2-14.
Andros et al., "TBGA Package Technology," Components, Packaging, and Manufacturing Technology, Part B: IEEE Transactions on Advanced Packaging, vol. 17, Issue 4, Nov. 1994, pp. 564-568. Clot et al., "Flip-Chip on Flex for 3D Packaging," 1999. 24th IEEE/CPMT, Oct. 18-19, 1999, pp. 36-41.
Ferrando et al., "Industrial approach of a flip-chip method using the stud-bumps with a non-conductive paste," Adhesive Joining and
Coating Technology in Electronics Manufacturing, 2000. Proceedings. 4th International Conference on, Jun. 18-21, 2000, pp. 205211.
Gallagher et al., "A Fully Additive, Polymeric Process for the
Fabrication and Assembly of Substrate and Component Level
Packaging," The First IEEE International Symposium on Polymeric
Electronics Packaging, Oct. 26-30, 1997, pp. 56-63.
Geissinger et al., "Tape Based CSP Package Supports Fine Pitch
Wirebonding," Electronics Manufacturing Technology Symposium,
2002, IEMT 2002, 27th Annual IEEE/SEMI International, Jul.
17-18, 2002, pp. 41-452.
Hatanaka, H., "Packaging processes using flip chip bonder and future directions of technology development," Electronics Packaging Technology Conference, 2002. 4th, Dec. 10-12, 2002, pp. 434-439.
Haug et al., "Low-Cost Direct Chip Attach: Comparison of SMD
Compatible FC Soldering with Anisotropically Conductive Adhe-
sive FC Bonding," IEEE Transactions of Electronics Packaging
Manufacturing, vol. 23, No. 1, Jan. 2000, pp. 12-18.
Kloeser et al., "Fine Pitch Stencil Printing of Sn/Pb and Lead Free
Solders for Flip Chip Technology," IEEE Transactions of
CPMT—Part C, vol. 21, No. 1, 1998, pp. 41-49.
Lee et al., "Enhancement of Moisture Sensitivity Performance of a
FBGA," Proceedings of International Symposium on Electronic
Materials & Packaging, 2000, pp. 470-475.
Li et al., "Stencil Printing Process Development for Flip Chip
Interconnect," IEEE Transactions Part C: Electronics Packaging
Manufacturing, vol. 23, Issue 3, (Jul. 2000), pp. 165-170.
Lyons et al., A New Approach to Using Anisotropically Conductive
Adhesives for Flip-Chip Assembly, Part A, IEEE Transactions on
Components, Packaging, and Manufacturing Technology, vol. 19,
Issue 1, Mar. 1996, pp. 5-11.
Meehan et al., "High volume flip chip applications," in Proceeding
of Area Packaging Technology, Berlin, Germany, Nov. 1995.
Teo et al., "Enhancing Moisture Resistance of PBGA," Electronic
Components and Technology Conference, 1988. 48th IEEE, May
25-28, 1998, pp. 930-935.
Teutsch et al, "Wafer Level CSP using Low Cost Electroless Redistribution Layer," Electronic Components and Technology Conference, 2000. 2000 Proceedings. 50th, May 21-24, 2000, pp. pp. 107-113.
"The 2003 International Technology Roadmap for Semiconductor:
Assembly and Packaging."
Tsui et al., "Pad redistribution technology for flip chip applications,"
Electronic Components and Technology Conference, 1998. 48th
IEEE, May 25-28, 1998, pp. 1098-1102.
Australian Search Report dated Aug. 11, 2004 (3 pages).
Australian Search Report dated Aug. 16, 2004 (4 pages).
Australian Search Report dated Nov. 8, 2004 (5 pages).
* cited by examiner