Semiconductor memory device having an SRAM and a DRAM on a single chip

(54) SEMICONDUCTOR MEMORY DEVICE HAVING AN SRAM AND A DRAM ON A SINGLE CHIP

(75) Inventors: Hitoshi Ikeda, Kawasaki (JP); Akihiro Funyu, Kawasaki (JP); Shinya Fujioka, Kawasaki (JP); Takaaki Suzuki, Kawasaki (JP); Masao Taguchi, Kawasaki (JP); Kimiaki Satoh, Kawasaki (JP); Kotoku Sato, Kawasaki (JP)

(73) Assignee: Fujitsu Limited, Kawasaki (JP)

( * ) Notice: Subject to any disclaimer, the term ol this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.

(56) References Cited

U.S. PATENT DOCUMENTS

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* cited by examiner

(21) Appl. No.: 09/917,913

(22) Filed: Jul. 31, 2001

(65) Prior Publication Data

US 2002/0006071 Al Jan. 17, 2002

Related U.S. Application Data

(62) Division ol application No. 09/531,498, filed on Mar. 21, 2000, now Pat. No. 6,292,426.

(30) Foreign Application Priority Data

May 31, 1999 (JP) 11-150792

(51) Int. C I. G11C 7/00

(52) U.S. CI 365/226; 365/227; 365/228;

365/229; 365/149; 365/154

(58) Field of Search 365/226, 227,

365/228, 229, 149, 154

Primary Examiner—Connie C. Yoha

(74) Attorney, Agent, or Firm—Arent Fox Kintner Plotkin

& Kahn

(57) ABSTRACT

A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/ DRAM address information provided to select one of the SRAM and the DRAM.

4 Claims, 14 Drawing Sheets