[54] METHOD AND APPARATUS FOR
SWITCHING ADDRESS GENERATION
MODES IN CPU HAVING PLURAL
ADDRESS GENERATION MODES
[75] Inventors: Seiichi Kawano, Machida; Hirohide Komiyama, Zama; Shuichi Mukohyama, Yamato, all of Japan
[73] Assignee: International Business Machines Corp., Armonk, N.Y.
[21] Appl. No.: 14,892
[22] Filed: Feb. 8,1993
[30] Foreign Application Priority Data
Nov. 20, 1992 [JP] Japan 4-034842
[51] Int.Cl.& G06F9/06
[52] U.S. Q 395/375; 364/946.2;
364/262.4
[58] Field of Search 395/375, 800, 775
[56] References Cited
U.S. PATENT DOCUMENTS 4,747,040 3/1988 Blanset 395/650
4,899,275 2/1990 Sachs 395/425
4,972,316 11/1990 Dixon 395/425
5,083,259 1/1992 Maresh 395/325
5,150,472 9/1992 Blank 395/425
5,168,557 12/1992 Shibuya 395/375
5,265,237 11/1993 Tobias 395/500
Primary Examiner—David Y. Eng
Attorney, Agent, or Firm—Robert S. Babayi
[57] ABSTRACT
A data processing system has a microprocessor that is operable in real and protected address generation modes. Transition from the real mode to the protected mode is done by initializing system tables and pointer registers, switching from the real mode to the protected mode, and flushing a prefetch queue before executing further instructions in the protected mode. The transition also includes flushing instructions from the prefetch queue, immediately after the initializing, and executing at least one instruction while prefetching additional instructions that are executed to complete the transition.
13 Claims, 4 Drawing Sheets
