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(12) United States Patent
Sherrer et al.
(io) Patent No.: (45) Date of Patent:
US 7,508,065 B2 Mar. 24, 2009
(54) DEVICE PACKAGE AND METHODS FOR THE FABRICATION AND TESTING THEREOF
(75) Inventors: David W. Sherrer, Radford, VA (US);
Larry J. Rasnake, Blacksburg, VA
(US); John J. Fisher, Blacksburg, VA
(73) Assignee: Nuvotronics, LLC, Blacksburg, VA
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl.No.: 11/590,629
(22) Filed: Oct. 31, 2006
(65) Prior Publication Data
US 2007/0072321 Al Mar. 29, 2007
Related U.S. Application Data
(62) Division of application No. 10/941,667, filed on Sep. 15, 2004, now Pat. No. 7,129,163.
(60) Provisional application No. 60/502,868, filed on Sep. 15, 2003.
Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure. Also provided are sealed via structures, methods of detecting leakage in a sealed device package, sealed device packages, device packages having cooling structures, and methods of bonding a first component to a second component.
18 Claims, 26 Drawing Sheets
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FOREIGN PATENT DOCUMENTS
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EP 1 333 267 Al 8/2003
WO WO 2004/025239 A2 3/2004
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* cited by examiner