BiCMOS process and process for forming bipolar transistors on wafers also ...

[54] BICMOS PROCESS AND PROCESS FOR FORMING BIPOLAR TRANSISTORS ON WAFERS ALSO CONTAINING FETS

[75] Inventor: Ceredig Roberts, Boise, Id.

[73] Assignee: Micron Technology, Inc., Boise, Id.

[21] Appl. No.: 556,907

[22] Filed: Jul. 23,1990

[51] Int CI.' H01L 21/265

[52] U.S.CI 437/34; 437/31;

437/46; 437/56; 437/59; 437/29; 437/186; 437/57; 148/DIG. 9; 148/DIG. 82

[58] Field of Search 437/34, 46, 193, 31,

437/29, 59, 162, 152, 155, 56, 57, 186; 148/DIG. 9, DIG. 82, DIG. 105; 357/43

[56] References Cited

U.S. PATENT DOCUMENTS

4,475,279 10/1984 Gahle 437/59

4,637,125 1/1987 Iwasaki et al 437/152

4,722,908 2/1988 Burton 437/152

4,764,480 8/1988 Vora 437/56

4,808,548 2/1989 Thomas et al 148/DIG. 10

4,849,364 7/1989 Scovell et al 437/31

4,874,717 10/1989 Neppl et al 437/59

4,891,328 1/1990 Gris 437/34

4,927,776 5/1990 Soejima 357/43

Primary Examiner—Brian E. Hearn

Assistant Examiner—Tuan Nguyen

Attorney, Agent, or Firm—Wells, St. John & Roberts

A process for fabricating integrated circuits containing bipolar transistors in semiconductor wafers comprising the following steps:

forming a well and an upper insulating layer on a semiconductor wafer;

selectively patterning and doping a bipolar transistor base implant region into the well;

selectively patterning a layer of conductive material atop the insulating layer, the conductive material layer selectively exposing a first area of the base implant region and covering other areas of the base implant region, the conductive material layer having at least one first edge which at least in part defines the exposed first area;

doping through the exposed first area to form an emitter implant region within the base implant region, the conductive material layer masking without photoresist the other covered areas of the base implant region during doping of the exposed first area; then patterning the layer of conductive material to expose a second area of the base implant region and to form gates of MOS transistors elsewhere in the integrated circuits, the patterning to expose the second area defining at least one second conductive material edge atop the base implant region;

masking the first area and exposing the second area with photoresist; and

doping through the exposed second area to form a base contact.

16 Claims, 5 Drawing Sheets