Utilizing multiple test bitstreams to avoid localized defects in partially ...

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US007620863B1

United States Patent

Trimberger

(io) Patent No.: (45) Date of Patent:

US 7,620,863 Bl Nov. 17, 2009

UTILIZING MULTIPLE TEST BITSTREAMS TO AVOID LOCALIZED DEFECTS IN PARTIALLY DEFECTIVE PROGRAMMABLE INTEGRATED CIRCUITS

Inventor: Stephen M. Trimberger, San Jose, CA (US)

Assignee: Xilinx, Inc., San Jose, CA (US)

Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.

Appl.No.: 12/181,346

Filed: Jul. 29, 2008

Related U.S. Application Data

Division of application No. 10/956,990, filed on Oct. 1, 2004, now Pat. No. 7,424,655.

Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices, thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting user configuration bitstreams are stored along with associated test bitstreams in a memory device, e.g., a programmable read-only memory (PROM). Under the control of a configuration control circuit or device, the test bitstreams are loaded into a partially defective IC and tested using an automated testing procedure. When a test bitstream is found that enables the associated user design to function correctly in the programmed IC, i.e., that avoids the defective programmable resources in the IC, the associated user bitstream is loaded into the IC, the configuration procedure terminates, and the programmed IC begins to function according to the user design.

19 Claims, 7 Drawing Sheets

Page 2

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