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United States Patent [m
 ATM SWITCHING ELEMENT AND METHOD HAVING INDEPENDENTLY ACCESSD3LE CELL MEMORIES
 Inventor: Brian D. Holden, Sunnyvale, Calif.
 Assignee: Integrated Telecom Technology, Santa Clara, Calif.
 Appl. No.: 235,006
 Filed: Apr. 28,1994
 Int. CL6 H04L 12/54
 U.S. CI 370/395; 370/352; 370/412;
 Field of Search 370/60, 60.1, 61,
 References Cited
U.S. PATENT DOCUMENTS
5,083,269 1/1992 Syobatake et al 370/85.6 X
5,099,475 3/1992 Kozaki et al 370/60
5,144,619 9/1992 Munter 370/60.1
5,233,606 8/1993 Pashanetal 370/85.6
5,285,444 2/1994 Sakurai et al 370/60
5,317,561 5/1994 Fischer et al 370/60.1 X
5,325,356 6/1994 Lyles 370/60
Lane, "ATM Knits Voice, Data On Any Net", IEEE Spectrum, Feb. 1994, pp. 42-45.
Alles, "Tutorial: ATM in Private Networking", Hughes LAN Systems, 1993.
"Fujitsu, Asynchronous Transfer Mode: IC's for ATM", Fujitsu, 1993.
Performance Evaluation of High Speed Switching Fabrics and Networks, Robertazzi ed., IEEE Press, 1993, pp. 1-3, 251-252.
Ahmadi et al., "A Survey of Modern High-Performance Switching Techniques", IEEE J. Selected Areas Commun., Sep. 1989, pp. 1091-1103, reprinted in Performance Evaluation, pp. 4-16.
US005583861A [ii] Patent Number: 5,583,861  Date of Patent: Dec. 10,1996
Karol et al., "Input Versus Output Queuing on a Space Division Packet Switch", IEEE Trans. Commun., Dec. 1987, pp. 1347-1356, reprinted in Performance Evaluation, pp. 59-68.
Chen et al., "Performance Study of an Input Queuing Packet Switch with Two Priority Cases", IEEE Trans. Commun., Jan. 1991, pp. 117-126, reprinted in Performance Evaluation, pp. 99-107.
Liew et al., "Comparison of Buffering Strategies for Asymetric Packet Switch Modules", IEEE J. Selected Areas Commun., Apr. 1991, pp. 428^-38, reprinted in Performance Evaluation, pp. 125-134.
Yeh et al., "The Knockout Switch: A Simple, Modular Architecture for High Performance Packet Switching", IEEE J. Selected Areas Commun., Oct. 1987, pp. 1274-1283, reprinted in Performance Evaluation, pp. 223-234.
(List continued on next page.)
Primary Examiner—Douglas W. Olms
Assistant Examiner—Russell W. Blum
Attorney, Agent, or Firm—Townsend and Townsend and
An ATM switching system architecture of a switch fabrictype is built of, a plurality of ATM switch element circuits and routing table circuits for each physical connection to/from the switch fabric. A shared pool of memory is employed to eliminate the need to provide memory at every crosspoint. Each routing table maintains a marked interrupt linked list for storing information about which ones of its virtual channels are experiencing congestion. This linked list is available to a processor in the external workstation to alert the processor when a congestion condition exists in one of the virtual channels. The switch element circuit typically has up to eight 4-bit-wide nibble inputs and eight 4-bit-wide nibble outputs and is capable of connecting cells received at any of its inputs to any of its outputs, based on the information in a routing tag uniquely associated with each cell.
15 Claims, 13 Drawing Sheets
Lee, "Nonblocking Copy Networks for Multicast Packet Switching", IEEE J. Selected Areas Commun., Dec. 1988, pp. 1455-1467, reprinted in Performance Evaluation, pp. 253-265.
Marchok et al., "First Stage Multicasting in a Growable Packet (ATM) Switch", Proc. IEEE International Confer
ence on Communications '91, Jun. 1991, pp. 1007-1013, reprinted in Performance Evaluation, pp. 283-289. Kim et al., "Call Scheduling Algorithms in a Multicast Switch", IEEE Trans. Commun., Mar. 1992, pp. 625-635, reprinted in Performance Evaluation, pp. 290-299. Ohshima et al., "A New ATM Switch Architecture Based on STS-Type Shared Buffering and its LSI Implementation", XTV International Switching Symposium, Oct. 1992.