US 7,633,143 Bl Dec. 15, 2009
(54) SEMICONDUCTOR PACKAGE HAVING
PLURAL CHIPS SIDE BY SIDE ARRANGED
(75) Inventor: Wen-Jeng Fan, Hsinchu (TW)
(73) Assignee: Powertech Technology Inc., Hsinchu (TW)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl.No.: 12/234,894
(22) Filed: Sep. 22, 2008
(51) Int. CI.
H01L 23/495 (2006.01)
(52) U.S. CI 257/676; 257/666
(58) Field of Classification Search 257/676,
257/666, 723, 724 See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS
5,057,906 A * 10/1991 Ishigami 257/706
A semiconductor package with multiple chips side-by-side disposed on a leadframe is revealed, primarily comprising a plurality of leads of a leadframe, a first chip, a second chip, and an encapsulant to encapsulate the chips where the chip thickness of the second chip is larger than the one of the first chip. The first chip and the second chip are individually disposed on a first die-attaching area and on a second dieattaching area of the leads or a die pad of the leadframe. The second die-attaching area is downset relative to the first dieattaching area in a manner that a bottom surface of the encapsulant is closer to the second die-attaching areas than to the first die-attaching areas. Therefore, when chips with different thicknesses are side-by-side disposed, there is no unbalanced mold flow nor package warpage issue.
14 Claims, 6 Drawing Sheets