Low cost timing system for highly accurate multi-modal semiconductor testing

(54) LOW COST TIMING SYSTEM FOR HIGHLY ACCURATE MULTI-MODAL SEMICONDUCTOR TESTING

(75) Inventor: Peter Reichert, Thousand Oaks, CA (US)

(73) Assignee: Teradyne, Inc., Boston, MA (US)

( * ) Notice: Subject to any disclaimer, the term ol this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.

(21) Appl. No.: 09/360,215

(22) Filed: Jul. 23, 1999

(51) Int. CI.7 G01R 31/28

(52) U.S. C I 714/738

(58) Field of Search 714/738, 724,

714/742, FOR 101; 324/765, 73.1, 158.1;

327/105; 365/201

(56) References Cited

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RE36,063 E 1/1999 Conner 395/550

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6,115,303 A * 9/2000 Fister 365/201

6,275,057 Bl * 8/2001 Takizawa 324/765

OTHER PUBLICATIONS

Armstrong, A.: "Timing Innovations Serve Logic and Mixed-Signal ATE"; Test and Measurement World; US Cahners Publishing, Denver; vol. 18, No. 11, Oct. 1, 1998, pp. 47^18, 50, 52, 54, XP000788714; ISSN: 0744-1657; p. 50, right-hand column, line 1—p. 51, right-hand column, line 30; figures 4-6.

* cited by examiner

Primary Examiner—Albert Decady

Assistant Examiner—Matthew C. Dooley

(74) Attorney, Agent, or Firm—Lance M. Kreisman

(57) ABSTRACT

A timing system is disclosed that responds to pattern generation circuitry for producing test patterns for application to a device-under-test. The timing system includes a timing memory circuit that stores programmed edge timings for the patterns and couples to timing logic including a master oscillator and a plurality ol fixed edge generators. The fixed edge generators are responsive to the programmed edge timings to produce the event timing signals.

18 Claims, 5 Drawing Sheets