Method for making improved shallow trench isolation for semiconductor ...

United States Patent [w]

Tan et al.

US006001706A [ii] Patent Number: [45] Date of Patent:

6,001,706 Dec. 14,1999

[54] METHOD FOR MAKING IMPROVED SHALLOW TRENCH ISOLATION FOR SEMICONDUCTOR INTEGRATED CIRCUITS

[75] Inventors: Poh Suan Tan, Singapore, Singapore;

Lap Chan, San Franciso, Calif.;
Qinghua Zhong; Qian Gang, both of
Singapore, Singapore

[51] Int. C I. H01L 21/76

[52] U.S. CI 438/424; 438/228; 438/426

[58] Field of Search 438/228, 424,

438/425, 426, 427

[56] References Cited

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A method was achieved for fabricating field oxide regions (shallow trench isolation) having raised portions which are self-aligned and extend over edges of device areas. This results in FETs with improved sub-threshold characteristics and lower sub-threshold leakage currents. The method consists of forming a pad oxide and depositing a doped polysilicon layer and a hard mask layer on a silicon substrate. Shallow trenches are etched through the hard mask, doped polysilicon layer and partially into the silicon substrate. A thermal oxidation is used to form a liner oxide in the trenches and to oxidize, at a higher oxidation rate, the sidewalls of the doped polysilicon layer to form an oxide over the edges of the device areas. A gap-fill oxide is deposited in the trenches and chemical mechanical polished (CMP) back to the polysilicon layer. The remaining polysilicon layer over the device areas is selectively removed to provide a field oxide having raised portions formed over the edges of the device areas. This eliminates the wrap-around corner effect which in the prior art resulted in enhanced corner conduction and increased sub-threshold leakage currents at substrate back bias. This improved method also provides greater processing latitude during the chemical mechanical polish step.

20 Claims, 5 Drawing Sheets

16'