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US007064375B2
(12) United States Patent ao) Patent No.: Us 7,064,375 B2
Yonehama et al. (45) Date of Patent: Jun. 20,2006
(54) SEMICONDUCTOR MEMORY DEVICE
HAVING A GATE ELECTRODE AND A
DIFFUSION LAYER AND A
MANUFACTURING METHOD THEREOF
Keisuke Yonehama, Mie-ken (JP); Eiji
Sakagami, Mie-ken (JP); Hiromasa
Fujimoto, Kanagawa-ken (JP); Naoki
Koido, Kanagawa-ken (JP)
Kabushiki Kaisha Toshiba, Tokyo (JP)
Subject to any disclaimer, the term of this
patent is extended or adjusted under 35
U.S.C. 154(b) by 0 days.
10/602,595
Jun. 25, 2003
Prior Publication Data
A semiconductor memory device, including a first memory cell having a first gate electrode, a first diffusion layer, and a second diffusion layer; a first contact layer connected to the first diffusion layer of the first memory cell; a second contact layer connected to the first contact layer; a second memory cell having a second gate electrode, a third diffusion layer and a fourth diffusion layer, the second gate electrode of the second memory cell electrically connected to the first gate electrode of the first memory cell, the first and second memory cells arranged in a direction perpendicular to the first bit line; and a conductive layer commonly connected to the second diffusion layer of the first memory cell and the fourth diffusion layer of the second memory cell, a height of the conductive layer substantially being coplanar with a height of the first contact layer.
30 Claims, 12 Drawing Sheets
214a1 and 214b1:Ti layer
214a2 and 214b2:W layer
