The addresses of firmward (ROM) being interrogated to ascertain data are continuously monitored. Selected key addresses are recognized by address detection means. Timing means is then actuated to count a preset number of address accesses, system clock cycles, or other suitable timing means. A substitute...http://www.google.com.au/patents/US4716586?utm_source=gb-gplus-sharePatent US4716586 - State sequence dependent read only memory
