A delay-locked loop (DLL) circuit and a method for generating transmission core clock signals are provided, where the DLL circuit receives an applied external clock signal and generates a transmission core clock signal, the DLL circuit includes a delay circuit unit and a transmission core clock signal...http://www.google.com.au/patents/US7825710?utm_source=gb-gplus-sharePatent US7825710 - Delay-locked loop circuits and method for generating transmission core clock signals
