A method for queuing hardware control blocks for a system including a host microprocessor and a plurality of devices that each includes an onboard sequencer is based on a single host endless new hardware control block queue in a host memory that is managed such that the host endless new hardware control...http://www.google.com.au/patents/US6012107?utm_source=gb-gplus-sharePatent US6012107 - Hardware control block delivery queues for host adapters and other devices with onboard processors
