A flag logic circuit is provided for use in a multi-queue memory device having a plurality of queues. A first stage memory stores a flag value for each of the queues in the multi-queue memory device. Flag values are routed from the first stage memory to a flag status bus having a width N in the manner...http://www.google.com.au/patents/US20060020742?utm_source=gb-gplus-sharePatent US20060020742 - Status bus accessing only available quadrants during loop mode operation in a multi-queue first-in first-out memory system
