The read latency of a plurality of memory devices in a high speed synchronous memory subsystem is equalized through the use of at least one flag signal. The flag signal has equivalent signal propagation characteristics read clock signal, thereby automatically compensating for the effect of signal propagation....http://www.google.com.au/patents/US20040160832?utm_source=gb-gplus-sharePatent US20040160832 - Method of synchronizing read timing in a high speed memory system
