A cache controller for a multithreading multiprocessor system which starts an execution of another thread by suspending an ongoing execution of a thread when a cache miss happens. The cache controller comprises a cache directory unit for storing cache managing data including a footprint bit to indicate...http://www.google.com.au/patents/US5535361?utm_source=gb-gplus-sharePatent US5535361 - Cache block replacement scheme based on directory control bit set/reset and hit/miss basis in a multiheading multiprocessor environment
