Each transistor or logic unit on an integrated circuit wafer is tested prior to interconnect metallization. By CAD means, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and...http://www.google.com.au/patents/US5020219?utm_source=gb-gplus-sharePatent US5020219 - Method of making a flexible tester surface for testing integrated circuits
