A cache memory architecture having a separate redundant read bus fully dedicated to redundancy and fed by a single spare sub-array common to all memory sub-arrays of the cache memory. Redundant sense amplifiers are dotted to the redundant read bus, and normal sense amplifiers are connected to a main...http://www.google.com.au/patents/US5627963?utm_source=gb-gplus-sharePatent US5627963 - Redundant read bus for correcting defective columns in a cache memory
