A non-volatile memory latch device includes two PMOS memory cells and a cross-coupled static latch having two PMOS transistors and two NMOS transistors. The floating gates of each PMOS memory cell/transistor pair are coupled together. The control gates of all four PMOS devices are commonly...http://www.google.com.au/patents/US5781471?utm_source=gb-gplus-sharePatent US5781471 - PMOS non-volatile latch for storage of redundancy addresses
