A fault tolerance method for FPGAs featuring interconnect resources made up of wiring segments that are programmably coupled to two or more configurable logic blocks (CLBs) through connection switches. In accordance with a first embodiment, one of the wiring segments is designated as being reserved for...http://www.google.com.au/patents/US6167558?utm_source=gb-gplus-sharePatent US6167558 - Method for tolerating defective logic blocks in programmable logic devices
