A P.sup.+ layer is formed on the lower surface of an N.sup.- substrate, and recesses are defined in the upper surface of the N.sup.- substrate. Then, P.sup.+ gate regions and bottom gate regions are formed in side walls and bottoms of the recesses. The N.sup.- substrate and an N.sup.- substrate...http://www.google.com.au/patents/US5648665?utm_source=gb-gplus-sharePatent US5648665 - Semiconductor device having a plurality of cavity defined gating regions and a fabrication method therefor
