Multi-level Jitter Control includes a system and operational methods for distributing jitter buffers among two or more subsystems of a system on a chip "SOC". In one embodiment, an integrated circuit includes a first processor equipped to receive audio data, perform a first level of jitter buffer control...http://www.google.com.au/patents/US20040062260?utm_source=gb-gplus-sharePatent US20040062260 - Multi-level jitter control
