An improved preload/prefetching architecture is disclosed for controlling branch target instruction loading in a pipelined processor. Branch target instructions can be speculatively preloaded/prefetched based on a first prediction indicator provided in a branch control instruction, and they also can...http://www.google.com.au/patents/US6374348?utm_source=gb-gplus-sharePatent US6374348 - Prioritized pre-fetch/preload mechanism for loading and speculative preloading of candidate branch target instruction
