An array of NROM flash memory cells configured to store at least two bits per four F2. Split vertical channels are generated along each side of adjacent pillars. A single control gate is formed over the pillars and in the trench between the pillars. The split channels can be connected by an n+ region...http://www.google.com.au/patents/US20050128804?utm_source=gb-gplus-sharePatent US20050128804 - Multi-state NROM device
