A two-level controller for a system interface between an auxiliary processor and main memory modules of a multiprocessing system which respective processor and system have different clock rates, memory access times and memory addressing capabilities. The two-level controller is formed of a hierarchy...http://www.google.com.au/patents/US4586133?utm_source=gb-gplus-sharePatent US4586133 - Multilevel controller for a cache memory interface in a multiprocessing system
