A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first...http://www.google.com.au/patents/US7786594?utm_source=gb-gplus-sharePatent US7786594 - Wafer level stack structure for system-in-package and method thereof
