An integrated circuit includes a plurality of processing stages each including processing logic 2, a non-delayed latch 4, a delayed latch 8 and a comparator 6. The non-delayed latch 4 captures an output from the processing logic 2 at a non-delayed capture time. At a later delayed capture time, the delayed...http://www.google.com.au/patents/US7650551?utm_source=gb-gplus-sharePatent US7650551 - Error detection and recovery within processing stages of an integrated circuit
