An a-Si FET comprising electrically conductive source and drain regions supported by an insulating substrate; a layer of amorphous silicon which is separately deposited in a space between said source and drain regions so as to engage the source and drain regions; source and drain electrodes electrically...http://www.google.com.au/patents/US4797108?utm_source=gb-gplus-sharePatent US4797108 - Method of manufacturing amorphous silicon field effect transistors
