A dual processor computer system is disclosed that includes a processor failure detection and recovery circuit which initially designates one of the processing units as the lead-off master and the other processing unit as a slave. The processor failure detection and recovery circuit includes a timer...http://www.google.com.au/patents/US5530946?utm_source=gb-gplus-sharePatent US5530946 - Processor failure detection and recovery circuit in a dual processor computer system and method of operation thereof
