WO2017167398A1

WO2017167398A1 - Method and apparatus for time and event aligned multilayer multiagent performance monitoring

Info

Publication number: WO2017167398A1
Application number: PCT/EP2016/057258
Authority: WO
Inventors: Francesc Guim Bernat; Kshitij A DOSHI; Alejandro Duran GONZALEZ; David Pardo KEPPEL
Original assignee: Intel Corporation
Priority date: 2016-04-01
Filing date: 2016-04-01
Publication date: 2017-10-05
Also published as: DE112016006686T5

Abstract

A processing system includes a processing core and a performance monitor agent (PMA) coordinator, communicatively coupled to the processing core, to receive, from the processing core, a request to monitor an event type associated with a device of the processing system, the request comprising a first identifier to identify the event type and a second identifier to identify the device, determine a memory address of a memory based on the first identifier and the second identifier, and transmit an instruction to a PMA executor associated with the device to cause the PMA executor to store information relating to the event type in a record starting at the memory address of the memory.

Description

METHOD AND APPARATUS FOR TIME AND EVENT ALIGNED MULTILAYER MULTIAGENT PERFORMANCE MONITORING

TECHNICAL FIELD

[0001] Embodiments of the disclosure relate generally to a processing system, and, more specifically, relate to a distributed performance monitor (PMON) that can monitor the performance of multiple processing units in the processing system through a centralized controller.

BACKGROUND

[0002] In most modern multi-programmed data processing or computer systems, various tasks or user applications contend for processing time to execute on a central processing unit (CPU) or similar processing device. Activity in even the most highly multitasking environment tends to be bursty, having periods of latency or inactivity followed by periods of intense processing activity.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. The drawings, however, should not be taken to limit the disclosure to the specific

embodiments, but are for explanation and understanding only.

[0004] Figure 1 illustrates a processing system including a multi-layered PMON architecture according to an embodiment of the present disclosure.

[0005] Figure 2 illustrates details of a designated memory area according to an embodiment of the present disclosure.

[0006] Figure 3 illustrates a detailed PMA executor according to an embodiment of the present disclosure.

[0007] Figure 4 is a flow diagram of a method to operate a processing system according to an embodiment of the disclosure.

[0008] Figure 5A is a block diagram illustrating a micro -architecture for a processor in which one embodiment of the disclosure may be used. [0009] Figure 5B is a block diagram illustrating an in-order pipeline and a register renaming stage, out-of-order issue/execution pipeline implemented according to at least one embodiment of the disclosure.

[0010] Figure 6 illustrates a block diagram of the micro-architecture for a processor in accordance with one embodiment of the disclosure.

[0011] Figure 7 is a block diagram illustrating a system in which an embodiment of the disclosure may be used.

[0012] Figure 8 is a block diagram of a system in which an embodiment of the disclosure may operate.

[0013] Figure 9 is a block diagram of a system in which an embodiment of the disclosure may operate.

[0014] Figure 10 is a block diagram of a System-on-a-Chip (SoC) in accordance with an embodiment of the present disclosure

[0015] Figure 11 is a block diagram of an embodiment of an SoC design in accordance with the present disclosure.

[0016] Figure 12 illustrates a block diagram of one embodiment of a computer system.

DETAILED DESCRIPTION

[0017] A processing system (e.g., a system-on-a chip (SoC)) may include multiple integrated circuit units (referred to as IC function units hereinafter) to perform certain tasks. The IC function units can include central processing units (CPUs), memory controllers, cache coherence controllers etc. These IC function units may communicate with each other via a bus system (e.g., an in-die interconnect (IDI) or a ring interconnect) using a communication protocol (e.g., the IDI protocol). Each of the IC function units may include a specialized performance monitor (PMON) to measure performance metrics associated with executing these tasks. The PMON may be a block of logic circuit embedded in an IC function unit to count the occurrences of performance-related events. The events can be different types of events including, for example, L1/L2 misses, last-level cache (LLC) misses, or a CPU clock halt.

[0018] A PMON of an IC function unit may be associated with a limited number (e.g., three) counters that are implemented in hardware or software to count the occurrences of a type of events. In some processing systems, the PMON may monitor multiple types of events associated with the IC function unit. Since the number of monitored event types may exceed the number of the counters, a counter may be time-multiplexed to count different types of events. For example, the PMON may count the occurrences of a type of events up to a threshold value and then generate a PMON interrupt signal to inform a processing core that the count of the event has exceeded the threshold value. A software application executing on the processing core may record the count and reinitialize the counter for a following processor time unit. Because of multiplexing, the software application collects the counts of the event type at a certain sampling rate over millions of instructions over multiple CPUs. Further, the software application may calculate statistics (e.g., the average) from these samples to create an event profile that may show the cause of the event type (e.g., an uptick in cycles per instruction (CPI)).

[0019] In operation, however, a type of events may occur in bursts and the access to the memory may be over multiple levels of hierarchy and usually non-uniform over time. As the number of processing cores within a processing system rises and the memory structure becomes more complex, it is harder to identify the causes of an event type based on the event profile generated from the statistics calculated using samples of event counts.

[0020] Embodiments of the present disclosure include a processing system that includes a multiple- layered PMON architecture that allows for interrupt-free event data collection directly into memory areas that are assigned to different types of events. Since the collected event data are stored in the memory areas that are assigned to event types and identified by identifiers associated with event types, a software application running on the processing core may retrieve the collected data using memory address mapping directly into the user space of the software application. In this way, the event data may be collected continuously at a very fine grain without the need for multiplexing.

[0021] In one embodiment, the PMON architecture may include one or more IC function units that are communicatively coupled with each other via an interconnect (e.g., the

IDI). Each IC function unit may include a programmable performance monitor agent (PMA) executor that is communicatively coupled to a centralized PMA coordinator via the interconnect. A software application executing on a processing core may issue requests to the

PMA coordinator via an application programming interface (PMON API). The requests may specify PMON parameters including such as, for example, the IC function unit and the event type to be monitored, a schedule according to which the event types are recorded, the memory regions to record the event type etc. The event types may be represented by an event type identifier, and the schedule may be represented by a sampling rate. Responsive to receiving a request, the PMA coordinator may program the PMA executor of the designated IC function unit to monitor the specified types of events and record the performance data associated with the event type in the memory region designated to the IC function unit and the event type. The performance data may include information that can be used to calculate metrics relating to the performance of the IC function unit. Thus, PMA executors may record performance data related to event types in the assigned memory regions without invoking interrupts to request the processing core to perform data collection from counters.

[0022] Figure 1 illustrates a processing system 100 including a multi-layered PMON architecture according to an embodiment of the present disclosure. As shown in Figure 1, processing system 100 may include one or more IC function units 102 A - 102B, a PMA coordinator 104, a memory 106, and an interconnect (e.g., the IDI) that communicatively connects IC function units 102A - 102B, PMA coordinator 104, and memory 106 using a communication protocol (e.g., the IDI protocol). As discussed above, the IC function units may include a processor, a memory controller, a cache controller. For example, in one embodiment, IC function unit 102A may be a processor that may include a processing core 110 to execute executable instructions of software applications. Additionally, each one of IC function units 102 A - 102B may include a PMA executor 112 A, 112B that can receive instructions and parameters from PMA coordinator 104. Thus, PMA executor 112 A, 112B can be programmed to monitor event types associated with the corresponding IC function unit and record performance data associated with event types associated with the IC function unit in a designated memory region.

[0023] In one embodiment, as shown in Figure 1, processing system 100 may be a system-on-a-chip hardware circuit that may be implemented on a single die (a same substrate) within a single semiconductor package. Processing system 100 may include an IC function unit 102 of a processor. Processor 102 may include a processing core 110 that may include an instruction execution pipeline and associated hardware components (such as L1/L2 cache etc.). Processing core 110 may be programmed to execute software applications composed of executable instructions. In one embodiment, processing core 110 may be provided with an interface function library called PMON API 114 so that a software application executing on processing core 110 may employ PMON API 114 to issue performance monitor requests via interconnect 108 to PMA coordinator 104. The performance monitor requests may include configuration data for PMA coordinator 104. The configuration data may include a memory address range associated with memory 106 to store collected performance data. In one embodiment, the memory region specified by the memory address range may form a circular buffer to store the performance data, whereas, when the buffer is full, the oldest content is overwritten by new performance data. The circular buffer may be employed for avoiding buffer overflows. The configuration data may also include event type identifiers, identifiers (e.g., instruction pointers) for instructions that generate the type of events, and the threshold values associated with the event type to be collected. The performance data associated with an event type may be recorded in a segment assigned to the event type within the memory address range. For example, each event type may be associated with an address offset with respect to a start address of the memory address range. Thus, the performance data collected for the event type may be recorded starting from the address offset. Thus, performance data of different event types may be recorded in different segments, where each of the segments may be associated with a respect address offset. The performance monitor requests may also include an instruction to start, stop, initialize (or configure), or reinitialize (or reconfigure) PMA executor 112 A, 112B. These instructions may be associated with a schedule according to which the performance data collection is executed.

[0024] PMA coordinator 104 may be a hardware controller that may send

programming instructions and parameters to PMA executors 112 A, 112B to delegate the performance of the PMON requests received from processing core 110. PMA coordinator 104 may provide configuration data to PMA executors 112 A, 112B that may specify how to collect performance data with respect to an event type and where in memory to store the collected performance data. The processing core 110 may expose registers 118 to software applications that may store the configuration data in these registers to send requests to PMA coordinator 104.

[0025] In one implementation, PMA coordinator 104 may include a decoder 116, registers 118, a translation lookaside buffer 120, a PMA coordinator logic circuit 122, and an interconnect interface 124 (e.g., an IDI interface). PMA coordinator 104 is communicatively connected to IC function units 102 A, 102B (and their corresponding PMA executors 112 A,

112B) and memory 106 to exchange messages using an interconnect communication protocol

(e.g., the coherency IDI protocol). Interconnect interface 124 may include logic circuit to connect components of PMA coordinator 104 to interconnect 108 to receive requests issued by a software application (using PMON API 114) executing on processing core 110, retrieve

PMON configuration data stored in memory 106, and send further requests to PMA executors

112A, 112B to perform performance monitoring tasks. In one embodiment, interconnect 108 is an on-die, ring-based interconnect that includes a data ring, a request ring, an acknowledge ring, and a snoop ring. The data ring may be used to transmit data; the request and acknowledge rings may be used to transmit control signals relating to data transmission; and the snoop ring may be used to transmit cache signals generated due to memory accesses (e.g., read and/or write). PMA coordinator 104 may communicate messages relating to

performance monitoring with other components in processing system 100 using these rings already existing in the ring-based bus system. In another embodiment, an additional PMON ring may be added to the existing ring-based bus system to facilitate the communication of the messages relating to performance monitoring.

[0026] In one embodiment, registers 118 may be model-specific registers (MSRs) that may store configuration data received from processing core 110. Processing core 110 may execute a software application to send configuration requests (e.g., using PMON API 114) to PMA coordinator 104. The configuration requests may include the configuration data to be stored in registers 118 and then in memory 106. For example, during an initialization process (or re-initialization process), the configuration requests from processing core 110 may transfer configuration data (e.g., the designated memory address ranges) associated with different IC function units to PMA coordinator 104 and then in memory 106. Subsequently, after receiving a start request to monitor the performance of an IC function unit, PMA coordinator logic 122 may load the configuration data from memory 106. In one embodiment, a first register may store the memory address range that encompasses the circular buffer to store performance data associated with an IC function unit. A second register may store the memory locations to store event type identifiers, instruction identifiers etc. A third register may store the address offsets for memory segments associated with different event types. A fourth register may store a current head pointer and tail pointer for the circular buffer. A fifth register may store the instruction (e.g., start, stop, initialize, or reinitialize) to PMA executor 112A, 112B.

[0027] PMA coordinator logic circuit 122 may operate employing the configuration data stored in registers 118. Thus, the software application running on processing core 110 may change how PMA coordinator 104 operates by modifying the configuration data stored in registers 118.

[0028] PMA coordinator logic circuit 122 may assign performance monitoring tasks to PMA executors 122 A, 122B based on configuration data in registers 118. In one embodiment, PMA coordinator logic circuit 122 may transmit instructions and parameters to

PMA executors 122 A, 122B to activate (or deactivate) counters associated with these PMA executors. The instructions from PMA coordinator logic circuit 122 to PMA executors 122A, 122B may be generated based on the configuration data stored in registers 118. PMA coordinator logic circuit 122 may use cache agents (e.g., cache controllers) to set up memory regions that are assigned to PMA executors 122A, 122B. For example, a software application may include code to allocate memory regions for storing the configuration data and the performance data and the pointers to the memory regions may be saved in registers 118 by the cache controllers.

[0029] Each PMA executor 122 A, 122B may be associated with a designated memory region 132A, 132B specified by a respective memory address range. In one embodiment, the memory address range may be specified in the physical memory address space. For example, as shown in Figure 1, PMA executor 122A may be associated with memory region 132A, and PMA executor 122B may be associated with memory region 132B. The designated memory region 132A, 132B may include a configuration data area to store the configuration data associated with the corresponding PMA executor and a collected data area to store the performance data collected by the PMA executor. Figure 2 illustrates details of a designated memory area 200 according to an embodiment of the present disclosure.

[0030] As shown in Figure 2, memory region 200 may include a PMON

configuration data area 202 and a PMON collected data area 204. PMON configuration data area 202 may include records 206A through 206B to store configuration parameters. In one embodiment, the configuration parameters may include a first identifier ("PMON ID") that identifies an event type, a second identifier ("device ID") that identifies an IC function unit whose performance with respect to the event type is monitored, a trigger point that describes the initiation point at which performance data collection starts, a stop point that describes the end point at which performance data collection concludes, and a memory address range within which the collected data stores. The trigger point (or the stop point) can be timestamps at which the data collection starts (or stops). The trigger point can also be a memory location within the memory address range and a threshold value. The trigger point occurs when the collected data value at the memory location crosses the threshold value. The trigger point and the stop point encode the schedule of the event monitoring.

[0031] PMON collected data area 204 may be associated with the memory address ranges defined in records of PMON configuration data area 202. PMON collected data area 204 may store performance data collected associated with an event type identified by the PMON ID. In one embodiment, as described in the following sections, the PMA executor may collect the performance data in a counter (e.g., a register that records the occurrence of an event type) and t store the performance data in a record in PMON configuration data area 202 according to the schedule received from the PMA coordinator. The stored data may include the PMON ID identifying the event type, a counter value representing the

performance data, and time (e.g., a timestamp) indicating the time instance at which the counter value is captured. Each record in PMON collected data area 204 may have a fixed length and start at a respective address offset from a starting address of memory region 200 assigned to the IC function unit identified by the device ID. Thus, data associated with an event type for an IC function unit may be retrieved by a software application from these records 208A, 208B stored in PMON collected data area 204.

[0032] Referring to Figure 1, in response to receiving a request from processing core

110 to monitor performance of IC function unit 102A, 102B, PMA coordinator logic circuit 122 may set up the corresponding PMA executors 112 A, 112B by storing the configuration parameters (e.g., PMON ID, device ID, trigger event, stop event, memory address range) in PMON configuration data area 202 of the designated memory region 132A, 132B. The PMA coordinator logic circuit 122 may have access to the system clock or bus snooping that may generate the trigger event and stop event. Further, PMA coordinator logic circuit 122 may, based on the configuration parameters, send an instruction (e.g., start, stop, initialize, or reinitialize) to request PMA executor 112 A, 112B to act accordingly.

[0033] In one embodiment, the request received from processing core 110 may include the device ID identifying the IC function unit whose performance is to be monitored. For example, the request received from processing core 110 may specify monitoring the event type of "Ll misses" (PMON ID "L1 MISS") for an IC function unit identified by an identifier "CORE L" Decoder 116 of PMA coordinator 104 may determine the PMA executor associated with the IC function unit. PMA coordinator logic circuit 122 may write the device ID in the record 206 A, 206B stored in PMON configuration data area 202.

[0034] In one embodiment, a translation lookaside buffer (TLB) 120 may be used to translate the virtual memory addresses employed by software applications running on processing core 110 to physical memory addresses used in the records stored in PMON configuration data area 202. TLB 120 may include a mapping table that maps the virtual memory addresses to the physical memory addresses. Thus, in response to receiving the request from a software application running on processing core 110 including a memory address range defined in the virtual memory address space, PMA coordinator logic circuit 122 may first employ TLB 120 to translate the memory address range into the physical memory address space and then store the memory address range in records 206A, 206B stored in PMON configuration data area 202. [0035] PMA executor 112A, 112B may, via interconnect 108, receive instructions from PMA coordinator 104 to initialize and collect performance data for specified event types. In one embodiment, PMA executors 112A, 112B are similar or identical logic circuits that may be initialized (or configured) to collect performance data. PMA executor 112 A, 112B may include an interface circuit 130A, 130B for communicating with interconnect 108 using an interconnect communication protocol, a PMA executor logic circuit 128 A, 128B for initializing configuration registers of PMA executor logic units 112 A, 112B and collecting performance data, and a PMON event detector 126 A, 126B to detect events based on the configuration data.

[0036] In one embodiment, PMA executors 112A, 112B may receive a request from

PMA coordinator 104 including a task that cannot be performed or that PMA executor 112 A, 112B fails to perform for certain reasons. For example, the requested task would require a number of counters that exceeds the total number of counters made available to the PMA executor 112 A, 112B. In response to failing to perform the requested task, PMA executor logic circuit 128A,128B may generate an interrupt to processing core 110 to send a message specifying the exception and details about the failure. The details may include the device ID associated with PMA executor 112A, 112B, a PMON ID for the requested event type, and the reason for the failure.

[0037] In one embodiment, PMA executor logic circuit 128A,128B may receive an initialization instruction along with configuration data to set up PMA executor 112 A, 112B to collect performance data with respect to an event type. For example, the requested event type may be LI cache misses associated with a cache controller. PMA executor logic circuit 128A,128B may initialize PMON event detector 126A, 126B to monitor cache snoop messages to detect LI misses. In response to detecting an LI miss, PMON event detector 126A, 126B may inform PMA executor logic circuit 128A,128B of the occurrence of the LI miss event.

[0038] PMA executor logic circuit 128A,128B may be programmed to collect occurrences of LI misses using counters. In one embodiment, PMA executor logic circuit

128A,128B may use a counter to count the number of LI misses. PMA executor logic circuit

128A,128B may further write the content of the counter to the corresponding memory region

132A, 132B. In one embodiment, the write back to the memory may occur when PMA executor logic circuit 128A,128B receive, from PMA coordinator 104, an instruction to deactivate the counter. In another embodiment, PMA executor logic circuit 128A,128B may write back to the memory according to a schedule provided by PMA coordinator 104. [0039] Figure 3 illustrates a detailed PMA executor 300 according to an embodiment of the present disclosure. As shown in Figure 3, PMA executor 300 may be

communicatively coupled to a memory 304 that is similar to memory 200 as shown in Figure 2, including PMON configuration data area 304 and PMON collected data area 306. PMA executor 300 may include registers 308 to store configuration data of the PMA executor logic circuit, an executor logic 310 to move performance data from counters to memory, an event detector 312 to detect a type of events and increment counters, and counters 314 to record the occurrences of certain event types.

[0040] In one embodiment, PMA executor 300 may include a number of hardware counters 314. Each one of counters 314 may be assigned (by PMA coordinator) to record the occurrence of a particular event type captured by event detector 312. For example, a first counter may be assigned to record LI misses, and a second counter may be assigned to record L2 misses. Executor 310 may include a circuit implementing control logics to perform performance data collection according to the schedule received from PMA coordinator. Thus, the executor logic 310 may receive, from PMA coordinator, a configuration instruction including a schedule to transfer performance data from counters to memory and the memory locations to store the performance data. The executor logic 310 may store the schedule and memory locations in registers 308. In one embodiment, the configuration instruction may include configuration data such as, for example, a schedule to collect counter values, whether or not the counter value should be aggregated, wherever in memory space (e.g., a physical memory address range) to store the counter value, and whether auxiliary data (e.g., instruction pointers) are to be captured along with the event types. If the instruction pointers are to be captured along with the counter values, executor logic 310 may capture the instruction pointers and write directly in the memory.

[0041] After PMA executor 300 is programmed based on the configuration data stored in registers 308, the control logic of executor logic 310 may receive a start instruction from the PMA coordinator to start collecting performance data in counters 314 and transfer the collected counter values from counters 314 to memory 302. Executor logic 310 may stop operations in response to receiving a stop instruction from the PMA coordinator.

[0042] In one embodiment, executor logic 310 may operate in an aggregation mode instructed by the PMA coordinator. Under the aggregation mode, executor logic 310 may calculate certain statistical values based on the counter values accumulated in the counter and write the statistical values to the memory 302. For example, one aggregation mode may be, for example, "to collect L2 misses every 1000 instructions," or "to write to the memory if LI misses are more than five every 1000 instructions"). Executor logic 310 may be programmed to include sub-states to maintain intermediate quantities (e.g., L2 misses within 1000 instructions) and cause to transfer the counter values stored in counters 314 to the memory 302 when the threshold value is reached. The aggregation mode of executor logic 310 provides a flexible trade-off between the memory space used to store performance data and the accuracy (i.e., how fine is the data sampling rate) of the collected performance data.

[0043] In one embodiment, executor logic 310 may also collect data from logical counters used by software applications running on a processing core and/or aggregate the data collected from these logical counters. For example, PMA executor 300 (as part of a processor or via an interconnect) may monitor the performance of the processing core and have access to the logical counters used by software applications running on the processing core.

Software applications may calculate a profile of a synthetic event (an event that is not generated by hardware, but defined in software programs). A synthetic event may not be detected by event detector 312. For example, the synthetic event type can be "last-level cache (LLC) misses per ring switch between a first ring and a second ring"). In this case, the occurrence of the ring switch may trigger an update in a logical counter, and the software application may instruct executor logic 310 to collect counter values of the logical counter as a hardware event counter (e.g., counters 314).

[0044] In one embodiment, executor logic 310 may also insert alignment markers

(e.g., timestamps) when it writes counter values to memory (e.g., as shown in Figure 2). The alignment markers may allow software applications to identify, access, and analyze the counter values stored in memory 304. Thus, the performance data stored in PMON collected data area 306 may be stored in both event and time aligned records.

[0045] In one embodiment, executor logic 310 may include filter circuits that may selectively record performance data (including counter values and associated auxiliary data) based on certain parameters. For example, executor logic 310 may record perform data for event types related to a section of physical memory addresses, instruction pointers, or virtual machines (identified by virtual machine identifiers) etc. Thus, software applications running on the processing core may pinpoint the hardware and software components whose performance data are collected.

[0046] In one embodiment, executor logic 310 may also be programmed to assert a trap and generate a callback to the software applications running on the processing core. The trap can be in the form of an interrupt signal from the PMA executor to the processing core executing the software application. The asserted trap may cause the software application to switch context (e.g., to reinitiate the PMA executor). For example, in response to detecting that the trap is triggered, executor 310 may send a user-level interrupt as the callback to the software applications to notice the triggering of a re-initiation. In an alternative embodiment, the callback may be a virtual one. For example, executor 310 may write to a memory location or a vector register to indicate the triggering. Software applications may poll the memory location or the vector register to detect the triggering of a callback.

[0047] Because the performance data are written to memory regions assigned to each

PMA executor in segments (with offsets) assigned to different events with timestamps, the performance data stored in the memory 304 is aligned to the events that happen at PMA executors. Software applications may directly map the aligned performance data stored in the memory to its user space without the need for the software application to capture the performance data using the counters and interrupt mechanism.

[0048] In one embodiment, PMA coordinator 104 is part of processor 102A. In another embodiment, PMA coordinator 104 is an independent hardware device connected to interconnect 108 and communicates with processor 102A via an interconnect communication protocol.

[0049] Figure 4 is a flow diagram of a method to operate a processing system according to an embodiment of the disclosure. Method 400 may be performed by processing logic that may include hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (such as instructions run on a processing system, a general purpose computer system, or a dedicated machine), firmware, or a combination thereof. In one embodiment, method 400 may be performed, in part, by processing logics of any one of the IC function units 102A, 102B and PMA coordinator 104 described with respect to Figure 1.

[0050] For simplicity of explanation, the method 400 is depicted and described as a series of acts. However, acts in accordance with this disclosure can occur in various orders and/or concurrently and with other acts not presented and described herein. Furthermore, not all illustrated acts may be performed to implement the method 400 in accordance with the disclosed subject matter. In addition, those skilled in the art will understand and appreciate that the method 400 could alternatively be represented as a series of interrelated states via a state diagram or events.

[0051] Referring to Figure 4, at 402, a PMA coordinator, communicatively coupled to a processing core, may receive, from the processing core, a request to monitor an event associated with a device of the processing system, the request comprising a first identifier to identify the event and a second identifier to identify the device.

[0052] At 404, the PMA coordinator may determine a memory address of a memory based on the first identifier and the second identifier.

[0053] At 406, the PMA coordinator may transmit an instruction to a PMA executor associated with the device to cause the PMA executor to collect information relating to the event type and store the information in a record starting at the memory address of the memory.

[0054] Figure 5A is a block diagram illustrating a micro -architecture for a processor

500 that implements the processing device including heterogeneous cores in accordance with one embodiment of the disclosure. Specifically, processor 500 depicts an in-order

architecture core and a register renaming logic, out-of-order issue/execution logic to be included in a processor according to at least one embodiment of the disclosure.

[0055] Processor 500 includes a front end unit 530 coupled to an execution engine unit 550, and both are coupled to a memory unit 570. The processor 500 may include a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, processor 500 may include a special-purpose core, such as, for example, a network or communication core, compression engine, graphics core, or the like. In one embodiment, processor 500 may be a multi-core processor or may part of a multi-processor system.

[0056] The front end unit 530 includes a branch prediction unit 532 coupled to an instruction cache unit 534, which is coupled to an instruction translation lookaside buffer (TLB) 536, which is coupled to an instruction fetch unit 538, which is coupled to a decode unit 540. The decode unit 540 (also known as a decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points,

microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decoder 540 may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. The instruction cache unit 534 is further coupled to the memory unit 570. The decode unit 540 is coupled to a rename/allocator unit 552 in the execution engine unit 550. [0057] The execution engine unit 550 includes the rename/allocator unit 552 coupled to a retirement unit 554 and a set of one or more scheduler unit(s) 556. The scheduler unit(s) 556 represents any number of different schedulers, including reservations stations (RS), central instruction window, etc. The scheduler unit(s) 556 is coupled to the physical register file(s) unit(s) 558. Each of the physical register file(s) units 558 represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, etc., status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. The physical register file(s) unit(s) 558 is overlapped by the retirement unit 554 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s), using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.).

[0058] Generally, the architectural registers are visible from the outside of the processor or from a programmer's perspective. The registers are not limited to any known particular type of circuit. Various different types of registers are suitable as long as they are capable of storing and providing data as described herein. Examples of suitable registers include, but are not limited to, dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. The retirement unit 554 and the physical register file(s) unit(s) 558 are coupled to the execution cluster(s) 560. The execution cluster(s) 560 includes a set of one or more execution units 562 and a set of one or more memory access units 564. The execution units 562 may perform various operations (e.g., shifts, addition, subtraction, multiplication) and operate on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point).

[0059] While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s) 556, physical register file(s) unit(s) 558, and execution cluster(s) 560 are shown as being possibly plural because certain embodiments create separate pipelines for certain types of

data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster

- and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s) 564). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

[0060] The set of memory access units 564 is coupled to the memory unit 570, which may include a data prefetcher 580, a data TLB unit 572, a data cache unit (DCU) 574, and a level 2 (L2) cache unit 576, to name a few examples. In some embodiments DCU 574 is also known as a first level data cache (LI cache). The DCU 574 may handle multiple outstanding cache misses and continue to service incoming stores and loads. It also supports maintaining cache coherency. The data TLB unit 572 is a cache used to improve virtual address translation speed by mapping virtual and physical address spaces. In one exemplary embodiment, the memory access units 564 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 572 in the memory unit 570. The L2 cache unit 576 may be coupled to one or more other levels of cache and eventually to a main memory.

[0061] In one embodiment, the data prefetcher 580 speculatively loads/prefetches data to the DCU 574 by automatically predicting which data a program is about to consume. Prefeteching may refer to transferring data stored in one memory location of a memory hierarchy (e.g., lower level caches or memory) to a higher-level memory location that is closer (e.g., yields lower access latency) to the processor before the data is actually demanded by the processor. More specifically, prefetching may refer to the early retrieval of data from one of the lower level caches/memory to a data cache and/or prefetch buffer before the processor issues a demand for the specific data being returned.

[0062] The processor 500 may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, CA; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, CA).

[0063] It should be understood that the core may support multithreading (executing two or more parallel sets of operations or threads), and may do so in a variety of ways including time sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that physical core is simultaneously multithreading), or a combination thereof (e.g., time sliced fetching and decoding and simultaneous multithreading thereafter such as in the Intel® Hyperthreading technology).

[0064] While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. While the illustrated embodiment of the processor also includes a separate instruction and data cache units and a shared L2 cache unit, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (LI) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and/or the processor.

Alternatively, all of the cache may be external to the core and/or the processor.

[0065] Figure 5B is a block diagram illustrating an in-order pipeline and a register renaming stage, out-of-order issue/execution pipeline implemented by processing device 500 of Figure 5A according to some embodiments of the disclosure. The solid lined boxes in Figure 5B illustrate an in-order pipeline, while the dashed lined boxes illustrates a register renaming, out-of-order issue/execution pipeline. In Figure 5B, a processor pipeline 500 includes a fetch stage 502, a length decode stage 504, a decode stage 506, an allocation stage 508, a renaming stage 510, a scheduling (also known as a dispatch or issue) stage 512, a register read/memory read stage 514, an execute stage 516, a write back/memory write stage 518, an exception handling stage 522, and a commit stage 524. In some embodiments, the ordering of stages 502-524 may be different than illustrated and are not limited to the specific ordering shown in Figure 5B.

[0066] Figure 6 illustrates a block diagram of the micro-architecture for a processor

600 in accordance with one embodiment of the disclosure. In some embodiments, an instruction in accordance with one embodiment can be implemented to operate on data elements having sizes of byte, word, doubleword, quadword, etc., as well as datatypes, such as single and double precision integer and floating point datatypes. In one embodiment the in-order front end 601 is the part of the processor 600 that fetches instructions to be executed and prepares them to be used later in the processor pipeline.

[0067] The front end 601 may include several units. In one embodiment, the instruction prefetcher 626 fetches instructions from memory and feeds them to an instruction decoder 628 which in turn decodes or interprets them. For example, in one embodiment, the decoder decodes a received instruction into one or more operations called "microinstructions" or "micro-operations" (also called micro op or uops) that the machine can execute. In other embodiments, the decoder parses the instruction into an opcode and corresponding data and control fields that are used by the micro-architecture to perform operations in accordance with one embodiment. In one embodiment, the trace cache 630 takes decoded uops and assembles them into program ordered sequences or traces in the uop queue 634 for execution. When the trace cache 630 encounters a complex instruction, the microcode ROM 632 provides the uops needed to complete the operation.

[0068] Some instructions are converted into a single micro-op, whereas others need several micro-ops to complete the full operation. In one embodiment, if more than four micro-ops are needed to complete an instruction, the decoder 628 accesses the microcode ROM 632 to do the instruction. For one embodiment, an instruction can be decoded into a small number of micro ops for processing at the instruction decoder 628. In another embodiment, an instruction can be stored within the microcode ROM 632 should a number of micro-ops be needed to accomplish the operation. The trace cache 630 refers to an entry point programmable logic array (PLA) to determine a correct micro -instruction pointer for reading the micro-code sequences to complete one or more instructions in accordance with one embodiment from the micro-code ROM 632. After the microcode ROM 632 finishes sequencing micro-ops for an instruction, the front end 601 of the machine resumes fetching micro-ops from the trace cache 630.

[0069] The out-of-order execution engine 603 is where the instructions are prepared for execution. The out-of-order execution logic has a number of buffers to smooth out and reorder the flow of instructions to optimize performance as they go down the pipeline and get scheduled for execution. The allocator logic allocates the machine buffers and resources that each uop needs in order to execute. The register renaming logic renames logic registers onto entries in a register file. The allocator also allocates an entry for each uop in one of the two uop queues, one for memory operations and one for non-memory operations, in front of the instruction schedulers: memory scheduler, fast scheduler 602, slow/general floating point scheduler 604, and simple floating point scheduler 606. The uop schedulers 602, 604, 606, determine when a uop is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resources the uops need to complete their operation. The fast scheduler 602 of one embodiment can schedule on each half of the main clock cycle while the other schedulers can only schedule once per main processor clock cycle. The schedulers arbitrate for the dispatch ports to schedule uops for execution.

[0070] Register files 608, 610, sit between the schedulers 602, 604, 606, and the execution units 612, 614, 616, 618, 620, 622, 624 in the execution block 611. There is a separate register file 608, 610, for integer and floating point operations, respectively. Each register file 608, 610, of one embodiment also includes a bypass network that can bypass or forward just completed results that have not yet been written into the register file to new dependent uops. The integer register file 608 and the floating point register file 610 are also capable of communicating data with the other. For one embodiment, the integer register file 608 is split into two separate register files, one register file for the low order 32 bits of data and a second register file for the high order 32 bits of data. The floating point register file 610 of one embodiment has 128 bit wide entries because floating point instructions typically have operands from 64 to 128 bits in width.

[0071] The execution block 611 contains the execution units 612, 614, 616, 618, 620,

622, 624, where the instructions are actually executed. This section includes the register files 608, 610, that store the integer and floating point data operand values that the microinstructions need to execute. The processor 600 of one embodiment is comprised of a number of execution units: address generation unit (AGU) 612, AGU 614, fast ALU 616, fast ALU 618, slow ALU 620, floating point ALU 622, floating point move unit 624. For one embodiment, the floating point execution blocks 622, 624, execute floating point, MMX, SIMD, and SSE, or other operations. The floating point ALU 622 of one embodiment includes a 64 bit by 64 bit floating point divider to execute divide, square root, and remainder micro-ops. For embodiments of the present disclosure, instructions involving a floating point value may be handled with the floating point hardware.

[0072] In one embodiment, the ALU operations go to the high-speed ALU execution units 616, 618. The fast ALUs 616, 618, of one embodiment can execute fast operations with an effective latency of half a clock cycle. For one embodiment, most complex integer operations go to the slow ALU 620 as the slow ALU 620 includes integer execution hardware for long latency type of operations, such as a multiplier, shifts, flag logic, and branch processing. Memory load/store operations are executed by the AGUs 612, 614. For one embodiment, the integer ALUs 616, 618, 620, are described in the context of performing integer operations on 64 bit data operands. In alternative embodiments, the ALUs 616, 618, 620, can be implemented to support a variety of data bits including 16, 32, 128, 256, etc. Similarly, the floating point units 622, 624, can be implemented to support a range of operands having bits of various widths. For one embodiment, the floating point units 622, 624, can operate on 128 bits wide packed data operands in conjunction with SIMD and multimedia instructions.

[0073] In one embodiment, the uops schedulers 602, 604, 606, dispatch dependent operations before the parent load has finished executing. As uops are speculatively scheduled and executed in processor 600, the processor 600 also includes logic to handle memory misses. If a data load misses in the data cache, there can be dependent operations in flight in the pipeline that have left the scheduler with temporarily incorrect data. A replay mechanism tracks and re-executes instructions that use incorrect data. Only the dependent operations need to be replayed and the independent ones are allowed to complete. The schedulers and replay mechanism of one embodiment of a processor are also designed to catch instruction sequences for text string comparison operations.

[0074] The processor 600 also includes logic to implement store address prediction for memory disambiguation according to embodiments of the disclosure. In one embodiment, the execution block 611 of processor 600 may include a store address predictor (not shown) for implementing store address prediction for memory disambiguation.

[0075] The term "registers" may refer to the on-board processor storage locations that are used as part of instructions to identify operands. In other words, registers may be those that are usable from the outside of the processor (from a programmer's perspective).

However, the registers of an embodiment should not be limited in meaning to a particular type of circuit. Rather, a register of an embodiment is capable of storing and providing data, and performing the functions described herein. The registers described herein can be

implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In one embodiment, integer registers store thirty-two bit integer data. A register file of one embodiment also contains eight multimedia SIMD registers for packed data.

[0076] For the discussions below, the registers are understood to be data registers designed to hold packed data, such as 64 bits wide MMXTM registers (also referred to as 'mm' registers in some instances) in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. These MMX registers, available in both integer and floating point forms, can operate with packed data elements that accompany SIMD and SSE instructions. Similarly, 128 bits wide XMM registers relating to SSE2, SSE3, SSE4, or beyond (referred to generically as "SSEx") technology can also be used to hold such packed data operands. In one embodiment, in storing packed data and integer data, the registers do not need to differentiate between the two data types. In one embodiment, integer and floating point are either contained in the same register file or different register files. Furthermore, in one embodiment, floating point and integer data may be stored in different registers or the same registers.

[0077] Referring now to Figure 7, shown is a block diagram illustrating a system 700 in which an embodiment of the disclosure may be used. As shown in Figure 7, multiprocessor system 700 is a point-to-point interconnect system, and includes a first processor 770 and a second processor 780 coupled via a point-to-point interconnect 750. While shown with only two processors 770, 780, it is to be understood that embodiments of the disclosure are not so limited. In other embodiments, one or more additional processors may be present in a given processor. .

[0078] Processors 770 and 780 are shown including integrated memory controller units 772 and 782, respectively. Processor 770 also includes as part of its bus controller units point-to-point (P-P) interfaces 776 and 778; similarly, second processor 780 includes P-P interfaces 786 and 788. Processors 770, 780 may exchange information via a point-to-point (P-P) interface 750 using P-P interface circuits 778, 788. As shown in Figure 7, IMCs 772 and 782 couple the processors to respective memories, namely a memory 732 and a memory 734, which may be portions of main memory locally attached to the respective processors.

[0079] Processors 770, 780 may each exchange information with a chipset 790 via individual P-P interfaces 752, 754 using point to point interface circuits 776, 794, 786, 798. Chipset 790 may also exchange information with a high-performance graphics circuit 738 via a high-performance graphics interface 739.

[0080] A shared cache (not shown) may be included in either processor or outside of both processors, yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.

[0081] Chipset 790 may be coupled to a first bus 716 via an interface 796. In one embodiment, first bus 716 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present disclosure is not so limited.

[0082] As shown in Figure 7, various I/O devices 714 may be coupled to first bus

716, along with a bus bridge 718 which couples first bus 716 to a second bus 720. In one embodiment, second bus 720 may be a low pin count (LPC) bus. Various devices may be coupled to second bus 720 including, for example, a keyboard and/or mouse 722,

communication devices 727 and a storage unit 728 such as a disk drive or other mass storage device which may include instructions/code and data 730, in one embodiment. Further, an audio I/O 724 may be coupled to second bus 720. Note that other architectures are possible. For example, instead of the point-to-point architecture of Figure 7, a system may implement a multi-drop bus or other such architecture. [0083] Referring now to Figure 8, shown is a block diagram of a system 800 in which one embodiment of the disclosure may operate. The system 800 may include one or more processors 810, 815, which are coupled to graphics memory controller hub (GMCH) 820. The optional nature of additional processors 815 is denoted in Figure 8 with broken lines.

[0084] Each processor 810, 815 may be some version of the circuit, integrated circuit, processor, and/or silicon integrated circuit as described above. However, it should be noted that it is unlikely that integrated graphics logic and integrated memory control units would exist in the processors 810, 815. Figure 8 illustrates that the GMCH 820 may be coupled to a memory 840 that may be, for example, a dynamic random access memory (DRAM). The DRAM may, for at least one embodiment, be associated with a non- volatile cache.

[0085] The GMCH 820 may be a chipset, or a portion of a chipset. The GMCH 820 may communicate with the processor(s) 810, 815 and control interaction between the processor(s) 810, 815 and memory 840. The GMCH 820 may also act as an accelerated bus interface between the processor(s) 810, 815 and other elements of the system 800. For at least one embodiment, the GMCH 820 communicates with the processor(s) 810, 815 via a multi-drop bus, such as a frontside bus (FSB) 895.

[0086] Furthermore, GMCH 820 is coupled to a display 845 (such as a flat panel or touchscreen display). GMCH 820 may include an integrated graphics accelerator. GMCH 820 is further coupled to an input/output (I/O) controller hub (ICH) 850, which may be used to couple various peripheral devices to system 800. Shown for example in the embodiment of Figure 8 is an external graphics device 860, which may be a discrete graphics device, coupled to ICH 850, along with another peripheral device 870.

[0087] Alternatively, additional or different processors may also be present in the system

800. For example, additional processor(s) 815 may include additional processors(s) that are the same as processor 810, additional processor(s) that are heterogeneous or asymmetric to processor 810, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor. There can be a variety of differences between the processor(s) 810, 815 in terms of a spectrum of metrics of merit including architectural, micro-architectural, thermal, power consumption characteristics, and the like. These differences may effectively manifest themselves as asymmetry and heterogeneity amongst the processors 810, 815. For at least one embodiment, the various processors 810, 815 may reside in the same die package.

[0088] Referring now to Figure 9, shown is a block diagram of a system 900 in which an embodiment of the disclosure may operate. Figure 9 illustrates processors 970, 980. Processors 970, 980 may include integrated memory and I/O control logic ("CL") 972 and 982, respectively and intercommunicate with each other via point-to-point interconnect 950 between point-to-point (P-P) interfaces 978 and 988 respectively. Processors 970, 980 each communicate with chipset 990 via point-to-point interconnects 952 and 954 through the respective P-P interfaces 976 to 994 and 986 to 998 as shown. For at least one embodiment, the CL 972, 982 may include integrated memory controller units. CLs 972, 982 may include I/O control logic. As depicted, memories 932, 934 coupled to CLs 972, 982 and I/O devices 914 are also coupled to the control logic 972, 982. Legacy I/O devices 915 are coupled to the chipset 990 via interface 996.

[0089] Embodiments may be implemented in many different system types. Figure 10 is a block diagram of a SoC 1000 in accordance with an embodiment of the present disclosure.

Dashed lined boxes are optional features on more advanced SoCs. In Figure 10, an interconnect unit(s) 1012 is coupled to: an application processor 1020 which includes a set of one or more cores 1002A-N and shared cache unit(s) 1006; a system agent unit 1010; a bus controller unit(s) 1016; an integrated memory controller unit(s) 1014; a set or one or more media processors 1018 which may include integrated graphics logic 1008, an image processor 1024 for providing still and/or video camera functionality, an audio processor 1026 for providing hardware audio acceleration, and a video processor 1028 for providing video encode/decode acceleration; an static random access memory (SRAM) unit 1030; a direct memory access (DMA) unit 1032; and a display unit 1040 for coupling to one or more external displays. In one embodiment, a memory module may be included in the integrated memory controller unit(s) 1014. In another

embodiment, the memory module may be included in one or more other components of the SoC 1000 that may be used to access and/or control a memory.

[0090] The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units 1006, and external memory (not shown) coupled to the set of integrated memory controller units 1014. The set of shared cache units 1006 may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof.

[0091] In some embodiments, one or more of the cores 1002A-N are capable of multithreading. The system agent 1010 includes those components coordinating and operating cores 1002A-N. The system agent unit 1010 may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores 1002A-N and the integrated graphics logic 1008. The display unit is for driving one or more externally connected displays.

[0092] The cores 1002A-N may be homogenous or heterogeneous in terms of architecture and/or instruction set. For example, some of the cores 1002A-N may be in order while others are out-of-order. As another example, two or more of the cores 1002A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set.

[0093] The application processor 1020 may be a general-purpose processor, such as a

Core™ i3, i5, i7, 2 Duo and Quad, Xeon™, Itanium™, Atom™ or Quark™ processor, which are available from Intel™ Corporation, of Santa Clara, Calif. Alternatively, the application processor 1020 may be from another company, such as ARM Holdings™, Ltd, MIPS™, etc. The application processor 1020 may be a special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, co-processor, embedded processor, or the like. The application processor 1020 may be implemented on one or more chips. The application processor 1020 may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

[0094] Figure 11 is a block diagram of an embodiment of a system on-chip (SoC) design in accordance with the present disclosure. As a specific illustrative example, SoC 1100 is included in user equipment (UE). In one embodiment, UE refers to any device to be used by an end-user to communicate, such as a hand-held phone, smartphone, tablet, ultra-thin notebook, notebook with broadband adapter, or any other similar communication device. Often a UE connects to a base station or node, which potentially corresponds in nature to a mobile station (MS) in a GSM network.

[0095] Here, SOC 1100 includes 2 cores— 1106 and 1107. Cores 1106 and 1107 may conform to an Instruction Set Architecture, such as an Intel® Architecture Core™-based processor, an Advanced Micro Devices, Inc. (AMD) processor, a MlPS-based processor, an ARM-based processor design, or a customer thereof, as well as their licensees or adopters. Cores 1106 and 1107 are coupled to cache control 1108 that is associated with bus interface unit 1109 and L2 cache 1110 to communicate with other parts of system 1100. Interconnect 1110 includes an on-chip interconnect, such as an IOSF, AMBA, or other interconnect discussed above, which potentially implements one or more aspects of the described disclosure.

[0096] Interconnect 1110 provides communication channels to the other components, such as a Subscriber Identity Module (SIM) 1130 to interface with a SIM card, a boot ROM

1135 to hold boot code for execution by cores 1106 and 1107 to initialize and boot SoC 1100, a SDRAM controller 1140 to interface with external memory (e.g. DRAM 1160), a flash controller 1145 to interface with non-volatile memory (e.g. Flash 1165), a peripheral control

1150 (e.g. Serial Peripheral Interface) to interface with peripherals, video codecs 1120 and Video interface 1125 to display and receive input (e.g. touch enabled input), GPU 1115 to perform graphics related computations, etc. Any of these interfaces may incorporate aspects of the disclosure described herein. In addition, the system 1100 illustrates peripherals for communication, such as a Bluetooth module 1170, 3G modem 1175, GPS 1180, and Wi-Fi 1185.

[0097] Figure 12 illustrates a diagrammatic representation of a machine in the example form of a computer system 1200 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, may be executed. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, or the Internet. The machine may operate in the capacity of a server or a client device in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0098] The computer system 1200 includes a processing device 1202, a main memory

1204 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM) or DRAM (RDRAM), etc.), a static memory 1206 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 1218, which communicate with each other via a bus 1230.

[0099] Processing device 1202 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device may be complex instruction set computing (CISC) microprocessor, reduced instruction set computer (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 1202 may also be one or more special- purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. In one embodiment, processing device 1202 may include one or processing cores. The processing device 1202 is configured to execute the processing logic 1226 for performing the operations and steps discussed herein.

[0100] The computer system 1200 may further include a network interface device

1208 communicably coupled to a network 1220. The computer system 1200 also may include a video display unit 1210 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1212 (e.g., a keyboard), a cursor control device 1214 (e.g., a mouse), and a signal generation device 1216 (e.g., a speaker). Furthermore, computer system 1200 may include a graphics processing unit 1222, a video processing unit 1228, and an audio processing unit 1232.

[0101] The data storage device 1218 may include a machine-accessible storage medium 1224 on which is stored software 1226 implementing any one or more of the methodologies of functions described herein, such as implementing store address prediction for memory disambiguation as described above. The software 1226 may also reside, completely or at least partially, within the main memory 1204 as instructions 1226 and/or within the processing device 1202 as processing logic 1226 during execution thereof by the computer system 1200; the main memory 1204 and the processing device 1202 also constituting machine-accessible storage media.

[0102] The machine-readable storage medium 1224 may also be used to store instructions 1226 implementing store address prediction and/or a software library containing methods that call the above applications. While the machine-accessible storage medium 1128 is shown in an example embodiment to be a single medium, the term "machine-accessible storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term "machine-accessible storage medium" shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instruction for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-accessible storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media.

[0103] The following examples pertain to further embodiments. Example 1 is a processing device that may include a processing core and a performance monitor agent

(PMA) coordinator, communicatively coupled to the processing core, to receive, from the processing core, a request to monitor an event type associated with a device of the processing system, the request comprising a first identifier to identify the event type and a second identifier to identify the device, determine a memory address of a memory based on the first identifier and the second identifier, and transmit an instruction to a PMA executor associated with the device to cause the PMA executor to store information relating to the event type in a record starting at the memory address of the memory.

[0104] In Example 2, the subject matter of Example 1 can further include an interconnect to connect the processing core, the PMA coordinator, and the device using an interconnect communication protocol, wherein the interconnect comprises a performance monitor ring, communicatively connecting the processing core, the PMA coordinator, and the PMA executor, to transmit the request and the instruction.

[0105] In Example 3, the subject matter of Example 1 can further provide that the

PMA coordinator further comprises a coordinator logic circuit to determine the memory address, and a plurality of registers to store the first identifier, the second identifier, and the memory address.

[0106] In Example 4, the subject matter of any of Examples 1 and 3 can further provide that the memory address is a physical memory address associated with the memory, and wherein the coordinator logic circuit uses a translation lookaside buffer of the PMA coordinator to determine the memory address.

[0107] In Example 5, the subject matter of Example 1 can further provide that the instruction to the PMA executor comprises the event type identifier and a schedule according to which the information relating to the event type is to be collected.

[0108] In Example 6, the subject matter of any of Examples 1 and 5 can provide that the PMA executor further comprises an executor logic circuit to receive the instruction from the PMA coordinator, an event detector, communicatively coupled to the executor logic circuit, to detect an occurrence of events of the event type, a register to store the memory address, and a counter to store a number of times that the events has occurred.

[0109] In Example 7, the subject matter of Example 6 can further provide that the executor logic circuit is to capture a value of the counter according to the schedule, and in response to capturing the value, to store the value and a timestamp to the record in the memory.

[0110] In Example 8, the subject matter of Example 7 can further provide that the request comprises at least one of an initialization instruction to cause the PMA coordinator to set up the register of the PMA executor, a start instruction to cause the PMA coordinator to start collecting the information by the PMA executor, or a stop instruction cause the PMA coordinator to terminate collecting the information by the PMA executor. [0111] In Example 9, the subject matter of Example 8 can further provide that the memory comprises a first area to store a plurality of configuration data records and a plurality of collected data records, wherein each one of the plurality of configuration data record comprises the first identifier, the second identifier, a trigger point to start collecting the information, a stop point to terminate collecting the information, and the memory address, and wherein each one of the plurality of collected data record comprises the first identifier, the capture value, and the timestamp.

[0112] In Example 10, the subject matter of Example 9 can further provide that the software application is to retrieve the plurality of collected data records based on the first identifier.

[0113] Example 11 is a system-on-a-chip including a processing core, a memory communicatively coupled to the processing core, and a performance monitor agent (PMA) coordinator, communicatively coupled to the processing core and the memory, to receive, from the processing core, a request to monitor an event type associated with a device of the processing system, the request comprising a first identifier to identify the event type and a second identifier to identify the device, determine a memory address of the memory based on the first identifier and the second identifier, and transmit an instruction to the device to cause a PMA executor associated with the device to store information relating to the event type in a record starting at the memory address of the memory.

[0114] In Example 12, the subject matter of Example 11 can further include an interconnect to connect the processing core, the PMA coordinator, and the device using an interconnect communication protocol, wherein the interconnect comprises a performance monitor ring, communicatively connecting the processing core, the PMA coordinator, and the PMA executor, to transmit the request and the instruction.

[0115] In Example 13, the subject matter of Example 11 can further provide that the

[0116] In Example 14, the subject matter of any of Examples 11 and 13 can further provide that the memory address is a physical memory address associated with the memory, and wherein the coordinator logic circuit uses a translation lookaside buffer of the PMA coordinator to determine the memory address. [0117] In Example 15, the subject matter of Example 11 can further provide that the instruction to the PMA executor comprises the event type identifier and a schedule according to which the information relating to the event type is to be collected.

[0118] In Example 16, the subject matter of any of Examples 11 and 15 can further provide that the PMA executor further comprises an executor logic circuit to receive the instruction from the PMA coordinator, an event detector, communicatively coupled to the executor logic circuit, to detect an occurrence of events of the event type, a register to store the memory address, and a counter to store a number of times that the events has occurred.

[0119] In Example 17, the subject matter of Example 16 can further provide that the executor logic circuit is to capture a value of the counter according to the schedule, and in response to capturing the value, to store the value and a timestamp to the record in the memory.

[0120] In Example 18, the subject matter of Example 17 can further provide that the request comprises at least one of an initialization instruction to cause the PMA coordinator to set up the register of the PMA executor, a start instruction to cause the PMA coordinator to start collecting the information by the PMA executor, or a stop instruction cause the PMA coordinator to terminate collecting the information by the PMA executor.

[0121] In Example 19, the subject matter of Example 18 can further provide that the memory comprises a first area to store a plurality of configuration data records and a plurality of collected data records, wherein each one of the plurality of configuration data record comprises the first identifier, the second identifier, a trigger point to start collecting the information, a stop point to terminate collecting the information, and the memory address, and wherein each one of the plurality of collected data record comprises the first identifier, the capture value, and the timestamp.

[0122] Example 20 is a method including receiving, by a performance monitor agent

(PMA) coordinator from a processing core, a request to monitor an event type associated with a device of the processing system, the request comprising a first identifier to identify the event type and a second identifier to identify the device, determining a memory address of a memory based on the first identifier and the second identifier, and transmitting an instruction to a PMA executor associated with the device to cause the PMA executor to store information relating to the event type in a record starting at the memory address of the memory.

[0123] In Example 21, the subject matter of Example 20 can further include translating the memory address from a virtual memory address space to a physical memory address space using a translation lookaside buffer. [0124] Example 22 is an apparatus comprising: means for performing any of the subject matter of Examples 20 and 21.

[0125] Example 23 is a machine-readable non-transitory medium having stored thereon program code that, when executed, perform operations including receiving, by a performance monitor agent (PMA) coordinator from a processing core, a request to monitor an event type associated with a device of the processing system, the request comprising a first identifier to identify the event type and a second identifier to identify the device, determining a memory address of a memory based on the first identifier and the second identifier, and transmitting an instruction to a PMA executor associated with the device to cause the PMA executor to store information relating to the event type in a record starting at the memory address of the memory.

[0126] In Example 24, the subject matter of Example 23 can further provide that the operations further includes translating the memory address from a virtual memory address space to a physical memory address space using a translation lookaside buffer.

[0127] While the disclosure has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations there from. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this disclosure.

[0128] A design may go through various stages, from creation to simulation to fabrication. Data representing a design may represent the design in a number of manners.

First, as is useful in simulations, the hardware may be represented using a hardware description language or another functional description language. Additionally, a circuit level model with logic and/or transistor gates may be produced at some stages of the design process. Furthermore, most designs, at some stage, reach a level of data representing the physical placement of various devices in the hardware model. In the case where conventional semiconductor fabrication techniques are used, the data representing the hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit. In any representation of the design, the data may be stored in any form of a machine readable medium. A memory or a magnetic or optical storage such as a disc may be the machine readable medium to store information transmitted via optical or electrical wave modulated or otherwise generated to transmit such information. When an electrical carrier wave indicating or carrying the code or design is transmitted, to the extent that copying, buffering, or re-transmission of the electrical signal is performed, a new copy is made. Thus, a communication provider or a network provider may store on a tangible, machine-readable medium, at least temporarily, an article, such as information encoded into a carrier wave, embodying techniques of embodiments of the present disclosure.

[0129] A module as used herein refers to any combination of hardware, software, and/or firmware. As an example, a module includes hardware, such as a micro-controller, associated with a non-transitory medium to store code adapted to be executed by the microcontroller. Therefore, reference to a module, in one embodiment, refers to the hardware, which is specifically configured to recognize and/or execute the code to be held on a non- transitory medium. Furthermore, in another embodiment, use of a module refers to the non- transitory medium including the code, which is specifically adapted to be executed by the microcontroller to perform predetermined operations. And as can be inferred, in yet another embodiment, the term module (in this example) may refer to the combination of the microcontroller and the non-transitory medium. Often module boundaries that are illustrated as separate commonly vary and potentially overlap. For example, a first and a second module may share hardware, software, firmware, or a combination thereof, while potentially retaining some independent hardware, software, or firmware. In one embodiment, use of the term logic includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.

[0130] Use of the phrase 'configured to,' in one embodiment, refers to arranging, putting together, manufacturing, offering to sell, importing and/or designing an apparatus, hardware, logic, or element to perform a designated or determined task. In this example, an apparatus or element thereof that is not operating is still 'configured to' perform a designated task if it is designed, coupled, and/or interconnected to perform said designated task. As a purely illustrative example, a logic gate may provide a 0 or a 1 during operation. But a logic gate 'configured to' provide an enable signal to a clock does not include every potential logic gate that may provide a 1 or 0. Instead, the logic gate is one coupled in some manner that during operation the 1 or 0 output is to enable the clock. Note once again that use of the term 'configured to' does not require operation, but instead focus on the latent state of an apparatus, hardware, and/or element, where in the latent state the apparatus, hardware, and/or element is designed to perform a particular task when the apparatus, hardware, and/or element is operating.

[0131] Furthermore, use of the phrases 'to,' 'capable of/to,' and or 'operable to,' in one embodiment, refers to some apparatus, logic, hardware, and/or element designed in such a way to enable use of the apparatus, logic, hardware, and/or element in a specified manner. Note as above that use of to, capable to, or operable to, in one embodiment, refers to the latent state of an apparatus, logic, hardware, and/or element, where the apparatus, logic, hardware, and/or element is not operating but is designed in such a manner to enable use of an apparatus in a specified manner.

[0132] A value, as used herein, includes any known representation of a number, a state, a logical state, or a binary logical state. Often, the use of logic levels, logic values, or logical values is also referred to as 1 's and 0's, which simply represents binary logic states. For example, a 1 refers to a high logic level and 0 refers to a low logic level. In one embodiment, a storage cell, such as a transistor or flash cell, may be capable of holding a single logical value or multiple logical values. However, other representations of values in computer systems have been used. For example the decimal number ten may also be represented as a binary value of 910 and a hexadecimal letter A. Therefore, a value includes any representation of information capable of being held in a computer system.

[0133] Moreover, states may be represented by values or portions of values. As an example, a first value, such as a logical one, may represent a default or initial state, while a second value, such as a logical zero, may represent a non-default state. In addition, the terms reset and set, in one embodiment, refer to a default and an updated value or state, respectively. For example, a default value potentially includes a high logical value, i.e. reset, while an updated value potentially includes a low logical value, i.e. set. Note that any combination of values may be utilized to represent any number of states.

[0134] The embodiments of methods, hardware, software, firmware or code set forth above may be implemented via instructions or code stored on a machine-accessible, machine readable, computer accessible, or computer readable medium which are executable by a processing element. A non-transitory machine-accessible/readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine, such as a computer or electronic system. For example, a non-transitory machine- accessible medium includes random-access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage medium; flash memory devices; electrical storage devices; optical storage devices; acoustical storage devices; other form of storage devices for holding information received from transitory (propagated) signals (e.g., carrier waves, infrared signals, digital signals); etc., which are to be distinguished from the non-transitory mediums that may receive information there from.

[0135] Instructions used to program logic to perform embodiments of the disclosure may be stored within a memory in the system, such as DRAM, cache, flash memory, or other storage. Furthermore, the instructions can be distributed via a network or by way of other computer readable media. Thus a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to, floppy diskettes, optical disks, Compact Disc, Read-Only Memory (CD- ROMs), and magneto-optical disks, Read-Only Memory (ROMs), Random Access Memory (RAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), magnetic or optical cards, flash memory, or a tangible, machine-readable storage used in the transmission of information over the Internet via electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). Accordingly, the computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

[0136] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0137] In the foregoing specification, a detailed description has been given with reference to specific exemplary embodiments. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Furthermore, the foregoing use of embodiment and other exemplarily language does not necessarily refer to the same embodiment or the same example, but may refer to different and distinct embodiments, as well as potentially the same embodiment.

Claims

CLAIMS What is claimed is:

1. A processing system comprising:

a processing core; and

a performance monitor agent (PMA) coordinator, communicatively coupled to the processing core, to:

receive, from the processing core, a request to monitor an event type associated with a device of the processing system, the request comprising a first identifier to identify the event type and a second identifier to identify the device;

determine a memory address of a memory based on the first identifier and the second identifier; and

transmit an instruction to a PMA executor associated with the device to cause the PMA executor to store information relating to the event type in a record starting at the memory address of the memory.

2. The processing system of claim 1, further comprising:

an interconnect to connect the processing core, the PMA coordinator, and the device using an interconnect communication protocol, wherein the interconnect comprises a performance monitor ring, communicatively connecting the processing core, the PMA coordinator, and the PMA executor, to transmit the request and the instruction.

3. The processing system of claim 1, wherein the PMA coordinator further comprises: a coordinator logic circuit to determine the memory address; and

a plurality of registers to store the first identifier, the second identifier, and the memory address.

4. The processing system of any of claims 1 and 3, wherein the memory address is a physical memory address associated with the memory, and wherein the coordinator logic circuit uses a translation lookaside buffer of the PMA coordinator to determine the memory address.

5. The processing system of claim 1, wherein the instruction to the PMA executor comprises the event type identifier and a schedule according to which the information relating to the event type is to be collected.

6. The processing system of any of claims 1 and 5, wherein the PMA executor further comprises:

an executor logic circuit to receive the instruction from the PMA coordinator;

an event detector, communicatively coupled to the executor logic circuit, to detect an occurrence of events of the event type;

a register to store the memory address; and

a counter to store a number of times that the events has occurred.

7. The processing system of claim 6, wherein the executor logic circuit is to capture a value of the counter according to the schedule, and in response to capturing the value, to store the value and a timestamp to the record in the memory.

8. The processing system of claim 7, wherein the request comprises at least one of an initialization instruction to cause the PMA coordinator to set up the register of the PMA executor, a start instruction to cause the PMA coordinator to start collecting the information by the PMA executor, or a stop instruction cause the PMA coordinator to terminate collecting the information by the PMA executor.

9. The processing system of claim 8, wherein the memory comprises a first area to store a plurality of configuration data records and a plurality of collected data records, wherein each one of the plurality of configuration data record comprises the first identifier, the second identifier, a trigger point to start collecting the information, a stop point to terminate collecting the information, and the memory address, and wherein each one of the plurality of collected data record comprises the first identifier, the capture value, and the timestamp.

10. The processing system of claim 9, wherein the software application is to retrieve the plurality of collected data records based on the first identifier.

11. A system-on-a-chip comprising:

a processing core;

a memory communicatively coupled to the processing core; and

a performance monitor agent (PMA) coordinator, communicatively coupled to the processing core and the memory, to:

receive, from the processing core, a request to monitor an event type associated with a device of the processing system, the request comprising a first identifier to identify the event type and a second identifier to identify the device; determine a memory address of the memory based on the first identifier and the second identifier; and

transmit an instruction to the device to cause a PMA executor associated with the device to store information relating to the event type in a record starting at the memory address of the memory.

12. The SoC of claim 11, further comprising:

13. The SoC of claim 11, wherein the PMA coordinator further comprises:

a coordinator logic circuit to determine the memory address; and

14. The SoC of any of claims 11 and 13, wherein the memory address is a physical memory address associated with the memory, and wherein the coordinator logic circuit uses a translation lookaside buffer of the PMA coordinator to determine the memory address.

15. The SoC of claim 11, wherein the instruction to the PMA executor comprises the event type identifier and a schedule according to which the information relating to the event type is to be collected.

16. The SoC of any of claims 11 and 15, wherein the PMA executor further comprises: an executor logic circuit to receive the instruction from the PMA coordinator;

a register to store the memory address; and

a counter to store a number of times that the events has occurred.

17. The SoC of claim 16, wherein the executor logic circuit is to capture a value of the counter according to the schedule, and in response to capturing the value, to store the value and a timestamp to the record in the memory.

18. The SoC of claim 17, wherein the request comprises at least one of an initialization instruction to cause the PMA coordinator to set up the register of the PMA executor, a start instruction to cause the PMA coordinator to start collecting the information by the PMA executor, or a stop instruction cause the PMA coordinator to terminate collecting the information by the PMA executor.

19. The SoC of claim 18, wherein the memory comprises a first area to store a plurality of configuration data records and a plurality of collected data records, wherein each one of the plurality of configuration data record comprises the first identifier, the second identifier, a trigger point to start collecting the information, a stop point to terminate collecting the information, and the memory address, and wherein each one of the plurality of collected data record comprises the first identifier, the capture value, and the timestamp.

20. A method comprising:

receiving, by a performance monitor agent (PMA) coordinator from a processing core, a request to monitor an event type associated with a device of the processing system, the request comprising a first identifier to identify the event type and a second identifier to identify the device;

determining a memory address of a memory based on the first identifier and the second identifier; and

transmitting an instruction to a PMA executor associated with the device to cause the PMA executor to store information relating to the event type in a record starting at the memory address of the memory.

21. The method of claim 20, further comprising:

translating the memory address from a virtual memory address space to a physical memory address space using a translation lookaside buffer.

22. An apparatus comprising: means for performing the method of any of claims 20 and 21.

23. A machine-readable non-transitory medium having stored thereon program code that, when executed, perform operations comprising:

24. The machine-readable non-transitory medium of claim 23, wherein the operations further comprises: