WO2016175736A1

WO2016175736A1 - On-chip ink level sensor including a capacitive sensor

Info

Publication number: WO2016175736A1
Application number: PCT/US2015/027732
Authority: WO
Inventors: Ning GE; Zhiyong Li; Leong Yap CHIA; Wai Mun Wong
Original assignee: Hewlett-Packard Development Company, L.P.
Priority date: 2015-04-27
Filing date: 2015-04-27
Publication date: 2016-11-03
Also published as: TW201637883A

Abstract

An on-chip ink level sensor includes a capacitive sensor. The capacitive sensor includes a metal layer, a memristor switching material having a thickness ranging from about 2 nm to about 50 nm positioned on the metal layer, a second metal layer positioned on the memristor switching material, and a substance in contact with the second metal layer. A capacitance of the capacitive sensor changes with a change in the substance. The sensor also includes first switch to apply a voltage to the capacitive sensor (placing a charge on the capacitive sensor) and a second switch to share the charge between the capacitive sensor and a reference capacitor, which results in a reference voltage. An evaluation transistor of the sensor is to provide a drain to source resistance in proportion to the reference voltage.

Description

ON-CHIP INK LEVEL SENSOR INCLUDING A CAPACITIVE SENSOR

BACKGROUND

[0001 ] Some inkjet printers include an ink level sensor in an ink supply reservoir. The ink level sensor senses the ink level remaining in the ink supply reservoir, and in some instances, provides a corresponding indication of the amount of remaining ink. Accurate ink level sensing may be desirable for a number of reasons. First, sensing the correct level of ink and providing the corresponding indication of the amount of ink left in an ink cartridge allows printer users to prepare to replace spent ink cartridges. Second, accurate ink level indications also help to avoid ink waste. Inaccurate ink level indications may result in the premature replacement of ink cartridges that still contain ink. Third, printing systems can use ink level sensing to trigger certain actions (e.g., prompt a notification to the user) that help prevent the formation of low quality prints that could otherwise result from inadequate supply levels.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Features of examples of the present disclosure will become apparent by reference to the following detailed description and drawings, in which like reference numerals correspond to similar, though perhaps not identical, components. For the sake of brevity, reference numerals or features having a previously described function may or may not be described in connection with other drawings in which they appear.

[0003] Fig. 1 is a schematic diagram of an inkjet printing system; [0004] Fig. 2 is a bottom, cut-away view of two ends of an example of a pnnthead including four examples of an on-chip ink level sensor disclosed herein;

[0005] Fig. 3 is a cross-sectional view of a portion of a printhead including an example of a drop generator;

[0006] Fig. 4 is a cross-sectional view of a portion of a printhead including an example of the capacitive sensor disclosed herein;

[0007] Fig. 5 is a timing diagram of non-overlapping clock signals used to drive an example of the ink level sensor disclosed herein;

[0008] Fig. 6 is an example of an ink level sensor circuit disclosed herein;

[0009] Fig. 7 is a flow diagram depicting an example of a method of

manufacturing a capacitive sensor of the on-chip ink level sensor disclosed herein; and

[0010] Figs. 8A through 8F are cross-sectional views of an example of a method of manufacturing a printhead including an example of the capacitive sensor disclosed herein.

DETAILED DESCRIPTION

[001 1 ] For a parallel plate capacitor having an insulator between two plates, the capacitance (C, farads) is given by equation 1 :

C = ε_γε₀ -_ά Eq. 1 where A is the area of overlap between the two plates in square meters, ε_Γ is the dielectric constant of the insulator, ε₀ is the permittivity of free space (i.e., electric constant, ε₀ ^s 8.854x10^"12 F nrf ¹), and d is the separation between the plates in meters.

[0012] The capacitance of the capacitive sensor disclosed herein depends, in part, upon the level of ink in a fluid chamber in which the capacitive sensor resides. When the ink covers a second metal layer of the capacitive sensor, the capacitance value is at a maximum. The maximum capacitance of the capacitive sensor disclosed herein is relatively high, even though the capacitive sensor is compact, having an area of 400 μιτι² or less. The capacitive sensor includes a thin memristor switching material (having a thickness ranging from about 2 nm to about 50 nm) with a high dielectric constant, which contributes to increasing the maximum capacitance that the capacitive sensor is capable of sensing. The capacitive sensor disclosed herein also has a higher coupling ratio (i.e., sensing capacitor capacitance versus sensing field effect transistor (FET) capacitance + parasitic capacitance) when compared to an ink level sensing capacitor that includes a passivation layer having a greater thickness, and in some instances a higher dielectric constant, than the memristor switching material.

[0013] In addition to being a high coupling ratio capacitor, the capacitive sensor disclosed herein also has memristor functionality, and thus is a Memcap capacitor. For example, upon application of a threshold switching voltage, the capacitive sensor is capable of switching, as a memristor, from a high resistance state to a low resistance state with less capacitance effect. The capacitive sensor includes two conductive plates (at least when ink is in contact with the second metal layer of the capacitive sensor) that function as electrodes, and the memristor switching material is sandwiched between the two conductive plates. The conductive plates act as selectors to allow memristor operation of the memristor switching material in some voltage regions, and to not allow memristor operation in other voltage regions. Memristor resistance is thus a function of current or voltage over time when in the operating voltage region.

[0014] In the examples disclosed herein, the conductive plates prevent current flow through the memristor switching material in the high resistance state. As an example, the high resistance state memristor switching material may correspond with a voltage ranging from about -5 V to about 5 V, where the memristor switching material is acting as a sensing capacitor with negligible leakage current (i.e., the memristor switching material is in a capacitance state). However, once the voltage across the memristor switching material reaches the set or forming voltage (e.g., over 5 V), then the memristor is set to ON and the current flows through the memristor switching material. Setting the memristor shorts the capacitor as the memristor switching material is in a low resistance state. As mentioned above, the resistance is a function of the amount of current or voltage over time, and if the time is long enough, the resistance will eventually saturate at a low resistance value. Memristor switching is non-volatile switching, and thus the memristor switching material will remain in the low resistance state even after the external voltage is removed. To reset the memristor switching material back to the high resistance state having high capacitance (i.e., capacitance state), another voltage (e.g., -5 V) is applied. After the external voltage is removed, the memristor switching material will remain in the high resistance state until another set and reset cycle of the memristor switching material. Accordingly, the capacitive sensor disclosed herein is resettable, and thus can be charged, discharged, or allowed to operate as a normal capacitor or memristor depending on the bias applied and the application.

[0015] The capacitive sensor disclosed herein is part of an on-chip ink level sensor. By "on-chip," it is meant that the components of the ink level sensor are integrated on-board a printhead substrate (e.g., silicon substrate). In an example, the printhead is a thermal inkjet (TIJ) printhead (e.g., a drop-on-demand thermal inkjet printhead) or a piezoelectric printhead. The printhead may be part of a printhead assembly, which may be part of an inkjet printing system.

[0016] An example of the inkjet printing system 100 including the printhead assembly 102 is shown in Fig. 1 . The printhead assembly 102 includes the printhead 1 14, which includes the on-chip ink level sensor (not shown in Fig. 1 , and described in detail in reference to Figs. 2 and 4-8). In an example, the printhead assembly 102 includes a single printhead 1 14, and in another example, the printhead assembly 102 includes an array of printheads 1 14.

[0017] In addition to the printhead assembly 102, the inkjet printing system 100 includes an ink supply assembly 104, a mounting assembly 106, a media transport assembly 108, an electronic printer controller 1 10, and a power supply 1 12 that provides power to the various electrical components of inkjet printing system 100.

[0018] The inkjet printhead assembly 102 includes the printhead 1 14, which ejects drops of ink through a plurality of nozzles 1 16 toward a print medium 1 18 to form an image, text, etc. thereon. Print media 1 18 may be any type of sheet or roll material, such as coated or uncoated paper, card stock, transparencies, polyester, plywood, foam board, fabric, canvas, etc.

[0019] Each nozzle 1 16 includes a microelectromechanical system (MEMS) fluidics chamber, which, as shown in Fig. 3, includes several thin layers that define a fluid chamber 14, a drop generator 24 (an example of which is a thermal inkjet firing resistor), and a bore or drop exit 31 .

[0020] The nozzles 1 16 may be arranged in one or more columns or arrays such that properly sequenced ejection of ink from the nozzles 1 16 causes characters, symbols, and/or other graphics or images to be printed on the print media 1 18 as the inkjet printhead assembly 102 and the print media 1 18 are moved relative to each other.

[0021 ] Ink supply assembly 104 supplies conductive fluid ink to the printhead assembly 102 and includes a reservoir 120 for storing the ink. The ink is capable of flowing from the reservoir 120 to the inkjet printhead assembly 102. The ink supply assembly 104 and the inkjet printhead assembly 102 can form either a oneway ink delivery system or a recirculating ink delivery system. In the one-way ink delivery system, substantially all of the ink supplied to inkjet printhead assembly 102 is consumed during printing. In the recirculating ink delivery system, a portion of the ink supplied to printhead assembly 102 is consumed during printing, and any ink not consumed during printing is returned to ink supply assembly 104.

[0022] In an example, the ink supply assembly 104 may supply ink (to the inkjet printhead assembly 102) under positive pressure through an ink conditioning assembly 105 via an interface connection, such as a supply tube. The ink supply assembly 104 may include, for example, a reservoir, a pump, and a pressure regulator. The ink conditioning assembly 105 may condition the ink before printing. Conditioning of the ink may include several processes, such as filtering, preheating, pressure surge absorption, and degassing. In the recirculating ink delivery system, the ink may be drawn under negative pressure from the printhead assembly 102 back to the ink supply assembly 104. A pressure difference between an inlet and an outlet of the printhead assembly 102 is selected to achieve a suitable backpressure at the nozzles 1 16. In an example, a suitable

backpressure at the nozzles 1 16 may be a negative pressure ranging from between -1 inches of water and -10 inches of water.

[0023] It is to be understood that the reservoir 120 of the ink supply assembly 104 may be removed, replaced, and/or refilled.

[0024] As shown in Fig. 1 , the inkjet printhead assembly 102 may also include a mounting assembly 106. The mounting assembly 106 is capable of positioning the inkjet printhead assembly 102 relative to the media transport assembly 108, and the media transport assembly 108 is capable of positioning the print media 1 18 relative to the inkjet printhead assembly 102. As such, a print zone 122 may be defined adjacent to the nozzles 1 16 in an area between the inkjet printhead assembly 102 and the print media 1 18. In an example when the inkjet printhead assembly 102 is a scanning type printhead assembly, the mounting assembly 106 may include a carriage for moving the inkjet printhead assembly 102 relative to media transport assembly 108 to scan the print media 1 18. In another embodiment when the inkjet printhead assembly 102 is a non-scanning type printhead

assembly, the mounting assembly 106 fixes the inkjet printhead assembly 102 at a prescribed position relative to the media transport assembly 108.

[0025] As shown in Fig. 1 , the inkjet printing system 100 also includes an electronic printer controller 1 10. The electronic printer controller 1 10 may include a processor, firmware, software, one or more memory components (e.g., volatile and non-volatile memory components), and other printer electronics for communicating with and controlling the inkjet printhead assembly 102, the mounting assembly 106, and the media transport assembly 108. Data 124 may be sent to the electronic printer controller 1 10 from a host system, such as a computer, and the data 124 may be temporarily stored in a memory of the electronic printer controller 1 10. The data 124 may be transmitted along an electronic, infrared, optical, or other information transfer path. As examples, the data 124 represents a document and/or file to be printed.

[0026] The electronic printer controller 1 10 may control the inkjet printhead assembly 102 for ejection of ink drops from the nozzles 1 16. For example, the electronic printer controller 1 10 may define a pattern of ejected ink drops that form characters, symbols, and/or other graphics or images on the print media 1 18. The pattern of ejected ink drops may be determined by print job commands and/or command parameters from the data 124.

[0027] The electronic printer controller 1 10 may include a printer application specific integrated circuit (ASIC) 126 and a resistance-sense module 128, which includes computer readable instructions executable on ASIC 126 or controller 1 10. Printer ASIC 126 may include a current source 130 and an analog to digital converter (ADC) 132. ASIC 126 is capable of converting the voltage present at current source 130 to determine a resistance, and then determining a

corresponding digital resistance value through the ADC 132. Computer readable instructions implemented by the resistance-sense module 128 enable the resistance determination and the subsequent digital conversion through the ADC 132.

[0028] Referring now to Fig. 2, a bottom view of an example of the printhead 1 14, including the on-chip ink level sensor 10, is depicted. The on-chip ink level sensor 10 includes sensing circuitry that implements a sample and hold technique that captures the state of the ink level through the capacitive sensor 12. The capacitance of the capacitive sensor 12 changes with the level of ink in a fluid chamber 14 overlying the capacitive sensor 12. The operation of the ink level sensing will be discussed further in reference to Figs. 4-6.

[0029] The printhead 1 14 includes a die substrate 16, which may be formed of silicon. The silicon die substrate 16 may be doped. An example of the doped silicon die substrate 16 is a p-type silicon substrate. [0030] From the bottom view of the printhead 1 14, the die substrate 16 underlies a chamber layer having the fluid chambers 14 formed therein and an orifice plate having bore exits 31 formed therein. Both the chamber layer 20 and the orifice plate 22 are described below in reference to Figs. 3 and 4. In Fig. 2, however, the chamber layer 20 and the orifice plate 22 are not shown in order to illustrate the die substrate 16. Since the fluid chambers 14 are formed in the chamber layer 20 (not shown in Fig. 2), the fluid chambers 14 in Fig. 2 are shown in dashed line in order to illustrate their position with respect to a fluid slot 18 and the on-chip ink level sensor 10 and/or a drop generator 24.

[0031 ] The fluid slot 18 is an elongated slot formed in the die substrate 16. The fluid slot 18 is in fluid communication with ink paths (not shown) that lead to the respective fluid chambers 14 that are positioned on both of the long sides of the fluid slot 18. By "fluid communication," it is meant that component(s) is/are configured so that a fluid can be in contact therewith. As an example, the previously mentioned fluid slot 18 may be connected to the ink paths so that fluid flows from the fluid slot 18 to the ink paths. As another example, a bore exit that is in fluid communication with a chamber 14 may enable fluid contained within the chamber 14 to exit therefrom. As still another example, a fluid chamber in fluid communication with a drop generator 24 and/or a capacitive sensor 12 may contain fluid that is capable of contacting the drop generator 24 and/or the capacitive sensor 12.

[0032] The example printhead 1 14 shown in Fig. 2 includes a single fluid slot 18, but it is to be understood that the printhead 1 14 may include two or more fluid slots 18. The fluid slot 18 is in fluid communication with a fluid supply (not shown), such as the fluid reservoir 120 (shown in Fig. 1 ), which supplies ink to the fluid slot 18 and the fluid chambers 14.

[0033] Each fluid chamber 14 is in fluid communication with the drop generator 24 and/or the on-chip ink level sensor 10. As shown in Fig. 2, in an example, four on-chip ink level sensors 10 may be positioned to be in fluid communication with the respective fluid chambers 14 located at the four corners of the ink slot 18. In this example, the other fluid chambers 14 may be in fluid communication with respective drop generators 24. Alternatively, in this example, any of the fluid chambers 14 may be in fluid communication with both the on-chip ink level sensor 10 and the drop generator 24 (see bottom left corner of the fluid slot 18 in Fig. 2). Due to small size of the capacitive sensor 12 of the ink level sensor 10, the capacitive sensor 12 and the drop generator 24 may be fabricated to be in fluid communication with the same fluid chamber 14. In another example, shown in phantom in Fig. 2, fluid chambers 14' may be formed at the two ends E1 , E2 of the ink slot 18, and respective on-chip ink level sensors 10 may be positioned to be in fluid communication with the respective fluid chambers 14'. In this example, the other fluid chambers 14 along the longer sides of the ink slot 18 may be in fluid communication with respective drop generators 24.

[0034] An example of the nozzle 1 16 portion of the printhead 1 14, including the drop generator 24, is shown in cross-section in Fig. 3. The drop generator 24 is associated with a single fluid chamber 14 and bore exit 31 . As shown in Fig. 3, the orifice plate 22 has the bore exit 31 formed therein and the chamber layer 20 has the fluid chamber 14 formed therein. The bore exit 31 is in fluid communication with the fluid chamber 14, so that ink 32 in the fluid chamber 14 can be ejected out through the bore exit 31 . In the printhead 1 14, the bore exits 31 may be arranged in the orifice plate 22 along the longer sides of the fluid slot 18 so they are positioned to be in fluid communication with respective fluid chambers 14 of respective nozzles 1 16.

[0035] The drop generator 24 includes an ejection element 26. In a thermal inkjet printhead, the ejection element 26 is a thermal firing resistor formed of a metal plate, which may be in contact with an insulating layer 28 (or 28', see Fig. 8E), which is in contact with a surface of the die substrate 16. The metal plate may be formed of Al, Ti, an AICu alloy, a TaAI alloy, or layers of metal(s) and alloy(s), such as a layer of Ti followed by a layer of AICu, or a layer of TaAI followed by a layer of AICu. In the example shown in Fig. 3, the ejection element 26 includes two layers, an electrically resistive layer 74 and a high conductive layer 76. As shown in Fig. 3, the high conductive layer 76 may include two bevels, between which the electrically resistive layer 74 is exposed. As an example, the electrically resistive layer 74 may have a thickness ranging from about 200 Angstroms to about 400 Angstroms, and the high conductive layer 76 may have a thickness of about 4800 Angstroms.

[0036] The insulating layer 28 (and insulating layer 28', discussed below) may be un-doped silicate glass (USG), phosphosilicate glass (PSG), tetraethyl orthosilicate (TEOS), borophosphosilicate glass (BPSG), or combinations thereof.

[0037] As shown in Fig. 3, a passivation layer 30 may be formed between the ejection element 26 and the fluid chamber 14 to protect the ejection element 26 from ink 32 in the chamber 14, and to act as a mechanical passivation or protective cavitation barrier structure to absorb the shock of collapsing vapor bubbles.

Examples of the passivation layer 30 include SiC, Si₃N₄, or layers of these materials, such as a layer of Si3N followed by a layer of SiC.

[0038] The chamber layer 20 has walls that define the fluid chambers 14, and that separate the die substrate 16 (and the various layers and elements formed thereon) from the orifice plate 22. An example of a material used to form the chamber layer 20 includes an epoxy-based negative photoresist (e.g., SU-8, IJ5000 from 3M, etc.).

[0039] During a thermal inkjet printing operation, a fluid drop is ejected from the chamber 14 through its corresponding bore exit 31 . Ink 32 is then refilled with fluid circulating from the fluid slot 18. The fluid drop is ejected as a result of electric current being passed through the ejection element 26, which rapidly heats the element 26. As a result of this heating, a thin layer of the ink 32 adjacent to the passivation layer 30 in contact with the ejection element 26 is superheated and vaporizes. This creates a vapor bubble in the corresponding chamber 14. The rapidly expanding vapor bubble forces a fluid drop out of the corresponding bore exit 31 . When the heated ejection element 26 cools, the vapor bubble quickly collapses, which draws more fluid from the fluid slot 18 into the chamber 14 in preparation for ejecting another drop from the nozzle 1 16. [0040] Referring back to Fig. 2, in addition to the drop generators 24, the printhead 1 14 also includes the on-chip ink level sensor(s) 10. The on-chip ink level sensor 10 disclosed herein includes the capacitive sensor 12, as well a sensor circuit 34. The sensor 10 may or may not also include a clearing resistor 36. Since the ejection element 26 fires ink 32 directly, the clearing resistor 36 may be excluded. The components of the sensor 10 are integrated on the printhead 1 14. It is to be understood that the on-chip ink level sensor 10 may also be electrically connected to off-chip components (i.e., components that are not integrated on the printhead 1 14), such as the current source 130 and the ADC 132 of the printer ASIC 126 (shown in Fig. 1 ). The off-chip components may be located on a printer carriage or the electronic controller 1 10 of the inkjet printing system 100.

[0041 ] The components of the on-chip ink level sensor(s) 10 may be located on the die substrate 16 along the ink slot 18 in any position where a drop generator 24 may be located. Various suitable positions for the on-chip ink level sensor(s) 10 are described above, and include, for example, at the four corners of the ink slot 18.

[0042] An example of a portion of the printhead 1 14 including the capacitive sensor 12 of the on-chip ink level sensor 10 is shown in cross-section in Fig. 4. The printhead 1 14 includes the die substrate 16 and the insulating layer 28 in contact therewith. In the example shown in Fig. 4, the capacitive sensor 12 is formed on a surface of the insulating layer 28 and in a via opening that is formed in a second insulating layer 28'. In an example, the insulating layers 28, 28' may be a single insulating layer. In an example when the layers 28, 28' are a single layer, the via opening may be formed so that it does not extend through the entire depth of the single insulating layer, and the capacitive sensor 12 may be formed in that via opening. Examples of the formation of the capacitive sensor 12 will be described further in reference to Figs. 8A through 8F.

[0043] The capacitive sensor 12 may have an area of 400 μιτι² (e.g., 20 μιτι x 20 μιτι) or less. As other examples, the capacitive sensor 12 may have an area of 225 μηη² (e.g., 15 μηη x 15 μηη), 100 μηη² (e.g., 10 μηη χ 10 μηη), 64 μηη² (e.g., 8 μηη χ 8 μηη), or any other suitable area of 400 μηη² or less. The dimensions of the capacitive sensor 12 enable it to be integrated on the printhead 1 14 in place of a drop generator 24, or near a drop generator 24 so the drop generator 24 and capacitive sensor 12 are associated with the same single fluid chamber 14 and nozzle 1 16.

[0044] The capacitive sensor 12 includes a metal layer 38, a memristor switching material (MSM) 40 positioned on the metal layer 38, a second metal layer 39 (which may include a transition layer 42 and an outer layer 74') positioned on the MSM 40, and a substance in contact with the second metal layer 39.

[0045] The metal layer 38 provides a first conductive plate (i.e., first plate) of the capacitive sensor 12. The metal layer 38 may be formed of Al or an alloy of Cu and Al. In an example, the AICu alloy includes from about 0.5 atomic% to about 1 .5 atomic% of Cu and a remainder of Al. The copper may be incorporated for electrical migration mitigation. In other examples, the metal layer 38 may be Al, AlCuSi, Cu, W, or any other suitable metal or metallic compound (e.g., TiN, TaN, some perovskites with or without dopants, such as BaTiO₃, Bai_-xLa_xTiO₃, and PrCaMnOs).

[0046] The MSM 40 may be grown or deposited on the metal layer 38. The MSM 40 is a very thin layer, having a thickness ranging from about 2 nm to about 50 nm. In an example, the thickness of the MSM 40 ranges from about 2 nm to less than 5 nm.

[0047] This thin MSM 40 may be a high quality dielectric material with a relative dielectric constant (ε_Γ) ranging from about 7.5 (e.g., Si3N₄) to about 60 (e.g., T1O2). It is to be understood that the high quality dielectric may be capable of transporting and hosting vacancies or ions that act as dopants in order to control the flow of electrons or current. The thin MSM 40 may be formed by oxidation, physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0048] As examples, the MSM 40 may be formed of an oxide (i.e., memristor switching oxide) or a nitride (i.e., memristor switching nitride). [0049] A memristor switching oxide contains at least one oxygen atom (O) and at least one other element. Some examples include alumina (aluminum oxide, AI2O3), titania (titanium oxide, ΤΊΟ2), zirconia (zirconium oxide, ZrO2), hafnia (hafnium oxide, HfO2), tantalum oxide (TaO_x), yttrium oxide (Y2O3), niobium oxide (NbO₂), calcium oxide (CaO), magnesium oxide (MgO), dysprosium oxide (Dy₂O₃), lanthanum oxide (La2Os), and silicon dioxide (S1O2). In an example, the MSM 40 is a layer of AIO_x (ε_Γ ~9) or a layer of AIO_x mixed with CuO_x grown (via oxidation) on the surface of an aluminum metal layer 38.

[0050] The memristor switching oxide may also be an alloy with two or three of the elements Ti, Zr, and Hf present (e.g., Ti_xZr_yHf_zO2, where x+y+z=1 ). Other related memristor switching oxides that may be used include titanates, zirconates, and hafnates. For example, titanates includes AT1O3, where A represents one of the divalent elements strontium (Sr), barium (Ba) calcium (Ca), magnesium (Mg), zinc (Zn), and cadmium (Cd). The memristor switching oxide may also be ABO3, where A represents the previously listed divalent elements and B represents Ti, Zr, or Hf. The memristor switching oxide may also be composed of alloys of these various compounds, such as Ca_aSr_bBacTi_xZryHf_zO3, where a+b+c=1 and x+y+z=1 .

[0051 ] It is to be understood that other oxides of transition and rare earth metals with different valences may be used for the MSM 40, both individually and as more complex compounds.

[0052] As mentioned above, the MSM 40 may be a semiconducting nitride (i.e., memristor switching nitride). An example of the memristor switching nitride includes Si3N (silicon nitride).

[0053] As mentioned above, the MSM 40 may be capable of transporting and hosting vacancies or ions that act as dopants, which allow for memristor operation. As examples, the mobile dopants may be oxygen anions or vacancies or nitrogen anions or vacancies. Table 1 below provides an example list of suitable MSMs 40 and the corresponding dopants. TABLE 1 : Examples of MSM Correspondir lg Mobile Dopants

Mobile Dopant

Ti0₂/Ti0₂-_x Oxygen vacancies

Zr0₂/Zr0₂-_x Oxygen vacancies

Hf0₂/Hf0₂-x Oxygen vacancies

SrTi0₂/SrTi0₂-_x Oxygen vacancies

[0054] Still referring to Fig. 4, the capacitive sensor 12 also includes the second metal layer 39. The second metal layer 39 may include one conductive layer or multiple conductive layers. In an example, the second metal layer 39 includes a transition layer 42 and an outer layer 74', the latter of which may be the same material as electrically resistive layer 74. In an example, the transition layer 42 is formed of TaAI, TiN, or TaN, and the outer layer 74' is formed of TaAI or WSiN. The second metal layer 39 provides an interface and cavitation layer between the MSM 40 and the substance in contact with the second metal layer 39. For example, TaAI is a high sheet resistivity layer that may provide chemical resistance to the ink 32 that the second metal layer 39 may come into contact with.

[0055] As shown in Fig. 4, a surface of the second metal layer 39 is exposed to one of the fluid chambers 14 of the printhead 1 14. Similar to the nozzle 1 16 with the drop generator 24, the fluid chamber 14 is defined by walls of the chamber layer 20 and the orifice plate 22. As shown in Fig. 4, when the chamber 14 adjacent to the capacitive sensor 12 is not also associated with a drop generator 24, a bore exit 31 may not be associated with the chamber 14 (i.e., this portion of the orifice plate 22 does not have a bore exit 31 defined therein). In other examples, the chamber 14 may be in fluid communication with the capacitive sensor 12 and the drop generator 24, and thus the chamber 14 may be associated with a bore exit 31 formed in the orifice plate 22.

[0056] The fluid chamber 14 includes the substance that is in contact with the second metal layer 39. When ink 32 fills the fluid chamber 14, the substance that is in contact with the second metal layer 39 is the ink 32. In the example shown in Fig. 4, the outer layer 74' is in contact with the ink 32. In this example, the second metal layer 39 and the conductive ink 32 form a second conductive plate of the capacitive sensor 12. When the ink 32 occupies less than the entire chamber 14, the substance that is in contact with the second metal layer 39 may be the ink 32 and air. In this example, the second metal layer 39 and any of the conductive ink 32 form the second conductive plate of the capacitive sensor 12. When the ink 32 is not present in the chamber 14, the substance that is in contact with the second metal layer 39 may be air alone. Without the ink 32, the second plate of the capacitive sensor 12 is electrically missing or weakly connected due to lack of a conducting substance as a signal path.

[0057] Since the conductive ink 32 forms part of the second conductive plate of the capacitive sensor 12, the capacitance value of the capacitive sensor 12 changes with the level of ink 32 in the chamber 14 (and thus with a change in the substance). When ink 32 is present in the chamber 14, the capacitive sensor 12 is connected, through ink 32 as a conductive substance, to ground so the

capacitance value is highest (i.e., 100%). However, when there is no ink 32 in the chamber 14 (i.e., the substance is air alone), the capacitance of the capacitive sensor 12 drops to a very small value (which is ideally close to zero), or the capacitor is non-existent due to a lack of conductive substance to ground. When the chamber 14 contains a combination of ink 32 and air as the substance, the capacitance value of the capacitive sensor 12 is somewhere between zero and 100%. Using the changing value of the capacitive sensor 12, the ink level sensor circuit 34 (described further below) is able to determine the ink 32 level in the chamber 14. It is to be understood that the ink 32 level in the chamber 14 is indicative of the level of ink 32 in reservoir 120 of inkjet printing system 100.

[0058] The capacitive sensor 12 disclosed herein has a relatively high capacitance value at its highest, in spite of the reduced area (which is about 27 times smaller than a thin-film stack capacitor, which utilizes, for example, the passivation layer 30 as the dielectric between two capacitor plates). The increased capacitance is due, at least in part, to the thinness of the MSM 40.

[0059] Fig. 4 also illustrates a conductive polysilicon layer 43 that may be positioned in the insulating layer 28 between the metal layer 38 of the capacitive sensor 12 and the die substrate 16. In thin-film stack capacitors including a passivation layer between two conductive plates, it has been found that intrinsic parasitic capacitance may be formed by one of the conductive plates, and the insulating layer and die substrate in contact therewith. In these thin-film stack capacitors, when a voltage is applied to the conductive plate, the capacitor made up of the conductive plate, the insulating layer, and the die substrate may charge. Because of this, the parasitic capacitance can contribute on the order of 20% of the capacitance determined for the thin-film stack capacitor. This can dilute signal(s) of the thin-film stack capacitor. The inclusion of the conductive polysilicon layer 43 in this type of capacitor effectively introduces an additional parasitic capacitor which is in series connection with the existing thin-film stack capacitor. This reduces the intrinsic parasitic capacitance. Due, in part, to the reduced area of the capacitive sensor 12 disclosed herein, it has been found that intrinsic parasitic capacitance between the metal layer 38, the insulating layer 28, and the die substrate 16 has been significantly reduced or eliminated, even without the conductive polysilicon layer 43. As such, the conductive polysilicon layer 43 may or may not be included in the examples of the printhead 1 14 disclosed herein.

[0060] Referring back to Fig. 2, some examples of the on-chip ink level sensor 10 may include the clearing resistor 36. Similar to the capacitive sensor 12, the clearing resistor 36 may be associated with a single chamber 14. The clearing resistor 36 may be hooked up to the firing lines and may be synchronized with the sensing timing of the capacitive sensor 12, and may be used to purge ink residue from the chamber 14 that it is associated with. An ink residue purge may be used prior to measuring the ink 32 level with capacitive sensor 12 and sensor circuit 34. The clearing resistor 36 may be used to the purge ink residue from the chamber 14, and then, to the extent that ink 32 is present in the reservoir 120, it flows back into the chamber 14 to enable an accurate ink level measurement.

[0061 ] As mentioned herein, with the changing value of the capacitive sensor 12, the ink level sensor circuit 34 (described further below) is able to determine the ink 32 level in the chamber 14. The sensor circuit 34 implements a sample and hold technique that captures the state of the ink 32 level through the capacitive sensor 12. A charge placed on the capacitive sensor 12 is shared between the capacitive sensor 12 and a reference capacitor, causing a reference voltage at the gate of an evaluation transistor. The current source 130 in the printer ASIC 126 supplies current at the transistor drain. The ASIC 126 measures the resulting voltage at the current source 130 and calculates the corresponding drain-to-source resistance of the evaluation transistor. The ASIC 126 then determines the status of the ink 32 level based on the resistance determined from the evaluation transistor. The sensor circuit 34 will be described in further detail in reference to Figs. 5 and 6.

[0062] Fig. 5 shows an example of a partial timing diagram 51 having non- overlapping clock signals (S1 -S3) with synchronized data and fire signals that may be used to drive the printhead 1 14, according to an example disclosed herein. The clock signals in timing diagram 51 may also be used to drive the operation of the ink level sensor circuit 34 as discussed below with regard to Fig. 6.

[0063] The sensor circuit 34 employs a charge sharing mechanism to determine different levels of ink 32 in the chamber 14. As shown in Fig. 6, the sensor circuit 34 includes two transistors T1 a, T1 b, which are configured as switches. Referring to both Figs. 5 and 6, during the initial operation of the sensor circuit 34, a clock pulse S1 is used to close the transistor switches T1 a and T1 b. This couples memory nodes M1 and M2 to ground, and discharges the capacitive sensor 12 and the reference capacitor 44.

[0064] The reference capacitor 44 is the capacitance between node M2 and ground. In this example, the reference capacitor 44 is implemented as the inherent gate capacitance of the evaluation transistor T4, and it is therefore illustrated using dashed lines. The reference capacitor 44 may additionally include associated parasitic capacitance, such as gate-source overlap capacitance, but the evaluation transistor T4 gate capacitance is the dominant capacitance in the reference capacitor 44. Using the gate capacitance of the evaluation transistor T4 as the reference capacitor 44 reduces the number of components in sensor circuit 34 by avoiding the inclusion of a specific reference capacitor fabricated between node M2 and ground. However, it is to be understood that the example shown in Fig. 6 is an example, and in other examples, it may be beneficial to adjust the value of reference capacitor 44 through the inclusion of a specific capacitor fabricated from M2 to ground (i.e., in addition to the inherent gate capacitance of evaluation transistor T4).

[0065] When the S1 clock pulse terminates, the T1a and T1 b transistor switches open. Directly after the T1 a and T1 b switches open, an S2 clock pulse is used to close transistor switch T2. Closing transistor switch T2 couples node M1 to a pre- charge voltage, Vp (e.g., on the order of +15 volts), and a charge Q1 is placed across capacitive sensor 12 according to the equation, Q1 =(C_MEMCAP)(VP). At this time, the M2 node remains at zero voltage potential since the S3 clock pulse is off. When the S2 clock pulse terminates, the T2 transistor switch opens. Directly after the T2 switch opens, the S3 clock pulse closes transistor switch T3, coupling nodes M1 and M2 to one another and sharing the charge Q1 between capacitive sensor 12 and reference capacitor 44. The shared charge Q1 between the capacitive sensor 12 and the reference capacitor 44 results in a reference voltage, Vg, at node M2, which is also at the gate of evaluation transistor T4, according to equation 2:

where C_MEMCAP is the capacitance of the capacitive sensor 12, C_REF is the capacitance of the reference capacitor 44 (a fixed value), and V_p is the constant voltage stored at the M1 node. [0066] Vg remains at M2 until another cycle begins with a clock pulse S1 grounding memory nodes M1 and M2. Vg at M2 turns on the evaluation transistor T4, which enables a measurement at the drain ID of transistor T4. In this example, it is presumed that the evaluation transistor T4 is biased in the linear mode of operation, where the evaluation transistor T4 acts as a resistor whose value is proportional to the gate voltage Vg (i.e., reference voltage). The evaluation transistor T4 resistance from drain to source (coupled to ground) is determined by forcing a small current at the drain ID (i.e., a current on the order of 1 milliamp). The drain ID is coupled to a current source, such as the current source 130 in the printer ASIC 126. Upon applying the current source at the drain ID, the voltage is measured at the drain ID (V|_D). Computer readable instructions, such as R_sense module 128 executing on the electronic controller 1 10 or ASIC 126, can convert V|_D to a resistance R_ds from drain ID to source of the T4 transistor using the current and V|_D. The ADC 132 in the printer ASIC 126 subsequently determines a corresponding digital value for the resistance Rds- The resistance Rd_S enables an inference as to the value of Vg based on the characteristics of transistor T4. Based on the value for Vg, a value of CMEMCAP may be determined from equation 2. The level of ink 32 can then be determined based on the value of CMEMCAP- [0067] Once the resistance Rds is determined, the ink 32 level may be determined various ways. For example, the measured Rd_S value can be compared to a reference value for R_ds, or a table of Rd_S values experimentally determined to be associated with specific ink levels. With no ink (i.e., a "dry" signal), or a very low ink level, the capacitance value of the capacitive sensor 12 is very low. This results in a very low Vg (on the order of 1 .7 volts), and the evaluation transistor T4 is off or nearly off (i.e., T4 is in cut off or sub-threshold operation region).

Therefore, the resistance R_ds from drain ID to ground through the evaluation transistor T4 would be very high (e.g., with drain ID current of 1 .2 mA, R_ds is typically above 12 k ohm). In contrast, with a high ink level (i.e., a "wet" signal), the capacitance value of the capacitive sensor 12 is close to 100% of its value, resulting in a high value for Vg (on the order of 3.5 volts). Therefore, the resistance R_ds is low. For example, with a high ink level, R_ds is below 1 k ohm, and is typically a few hundred ohms.

[0068] While not shown in Fig. 6, it is to be understood that auxiliary circuitry may be included as well.

[0069] It is to be understood that during the ink level sensing operation, the voltage applied to the capacitive sensor 12 (after it is initially charged), may be below the threshold voltage for memristor switching so that the capacitive sensor 12 is capable of functioning as a capacitor rather than a memristor. As briefly described above, the voltage applied across the capacitive sensor 12 may be changed in order to activate the mobile dopants in the MSM 40 so that current flows through the capacitive sensor 12. This shift in voltage shorts the capacitor and the MSM 40 functions as a low resistance resistor. As such, the capacitor function may be turned off, which may be desirable, for example, when the ink 32 supply life is at or near its end. Changing the voltage applied across the capacitive sensor 12 back to the low conductance region causes the capacitive sensor 12 to again behave as the capacitor.

[0070] To integrate the capacitive sensor 12 and the other ink level sensor 10 components on-board the printhead 1 14, an example of the method 200 shown in Fig. 7 may be used. The method 200 will be described in detail in conjunction with Figs. 8A-8F.

[0071 ] At the outset of the method 200 (reference numeral 202 in Fig. 2), the insulating/insulator layer 28' is deposited over a plurality of transistors formed in the die substrate 16 and interconnected by a first metal layer 60 (see Fig. 8C).

Examples of these transistors are the switching transistors T1 _a and T1 _b, T2, T3 and T4.

[0072] As shown in Fig. 8A, one transistor 46 is formed on the die substrate 16, such that it overlies a gate region 48 and slightly overlaps two wells 50, 52 (which form a source and a drain, e.g., drain ID shown in Fig. 6) on opposite sides of the gate region 48. [0073] To form the transistor 46, a gate oxide 54 is grown or deposited on the die substrate 16. The gate oxide 54 may be formed of a dielectric material. As examples, the gate oxide 54 may be formed of a layer of silicon dioxide, or of several layers, such as a layer of silicon nitride and a layer of silicon dioxide.

[0074] The transistor 46 also includes a polysilicon layer 56 in contact with the gate oxide 54. The polysilicon layer 56 may be a polycrystalline silicon. In an example, the polysilicon layer 56 may be deposited on the gate oxide 54 using any suitable deposition technique. After being deposited, the gate oxide 54 and the polysilicon layer 56 may be patterned with a gate mask and wet or dry etched to form the gate region 48.

[0075] A dopant concentration may then be applied in area(s) of the die substrate 16 that is/are not obstructed by the transistor 46 to create the

wells/source and drain 50, 52 of the transistor 46. After doping, there may be slight overlap between the gate oxide 54 and the respective wells 50, 52. This slight overlap between minimizes channel effects.

[0076] The insulating layer 28 (which in this example of the method 200 is a first insulator layer), is applied on the wells 50, 52 and on the transistor 46. Any example of the insulating layer 28 previously described may be used. In an example, the insulating layer 28 is deposited to a thickness of at least 2,000

Angstroms in order to provide sufficient thermal isolation between a later formed clearing resistor 36 and the die substrate 16. In an example, the thickness of the insulating layer 28 ranges from about 6,000 Angstroms to about 12,000 Angstroms, or more. After the insulating layer 28 is applied, it may be densified and/or planarized.

[0077] In some examples of the method 200, before applying the first insulating layer 28, a thin layer of thermal oxide may be applied over the well/source 50, well/drain 52, and transistor 46. This thermal oxide may be applied to a thickness ranging from about 50 Angstroms to 2,000 Angstroms. In an example, the thickness of the thermal oxide is about 1 ,000 Angstroms. [0078] As shown in Fig. 8A, a first set of contact regions 58 may be created by masking and etching the insulating layer 28. As an example, a contact mask may be used to form openings/contact regions 58 to the well/source 50 and the well/drain 52 (i.e., the active regions of the transistor 46). While not shown, another etch step may be used with a substrate contact mask to pattern and etch die substrate contacts.

[0079] Referring now to Fig. 8B, the first metal layer 60 is applied on the insulating layer 28 and in the openings 58. The first metal layer 60 may be formed of any of the materials described for the metal layer 38 of the capacitive sensor 12 because a portion of the first metal layer 60 will form the metal layer 38. When applied, the first metal layer 60 fills the contact openings 58. This forms contacts 62, 64 to the wells 50, 52.

[0080] The first metal layer 60 may then be patterned with a mask and etched to form the contacts 62, 64 and the metal layer 38 (i.e., the first capacitor plate of the capacitive sensor 12). The metal mask that is used is modified to include geometry for forming the respective metal layers 38 for each capacitive sensor 12 that is to be formed.

[0081 ] Another insulating layer 28' (shown in Fig. 8C after patterning) is deposited over contacts 62, 64 and the metal layer 38. The deposition of this insulating layer 28' corresponds with reference numeral 202 of Fig. 7, where insulating layer 28' is deposited over a plurality of transistors (e.g., transistor 46) formed in the die substrate 16 and interconnected by the first metal layer 60. The insulating layer 28' may be the same as or different from insulating layer 28. In an example, the insulating layer 28' may include multiple sub-layers, such as a nitride layer and a TEOS layer.

[0082] The insulating layer 28' may be planarized or not, and then masked and etched to create via opening(s) 66 and 68 (Fig. 8C). This corresponds with reference numeral 204 of the method 200 shown in Fig. 7. The via opening 66 exposes the contact 64, and the via opening 68 exposes the portion of the metal layer 60, 38 and defines an area and location for the capacitive sensor 12. This masking and etching step utilizes a mask that allows for creating the via openings 66, 68.

[0083] After the openings 66, 68 have been created, the MSM 40 is applied (e.g., deposited or grown) on the first metal layer 60 (layer/plate 38) and also on the exposed first metal layer 60 in the via opening 66 (i.e., on the contact 64). This corresponds with reference numeral 206 of the method 200 in Fig. 7. Further processing may be performed to inject mobile dopants (e.g., oxide or nitride vacancies, etc.) into the MSM 40. In addition, doping may be accomplished to create selectors, which allow for more precise control of the ultimately formed capacitive sensor 12 (see Fig. 8E).

[0084] Furthermore, the transition layer 42 of metal may be deposited or otherwise applied on the MSM 40 (corresponding with reference numeral 208 of the method 200 in Fig. 7), and on the exposed portions of the insulating layer 28'. Any examples of the transition layer 42 previously described may be deposited.

[0085] Next, in Fig. 8D, a MSM mask layer 70 is applied and etched to cover the transition layer 42 in the via opening 68 (i.e., at the area and location where the capacitive sensor 12 is to be formed). The MSM mask layer 70 does not cover the remainder of the transition layer 42, including the portion in the via opening 66. This MSM mask layer 70 is an additional mask layer for the entire process. The MSM mask layer 70 is utilized so that the MSM 40 and the transition layer 42 may be removed from the contact 64, and so that the remaining transition layer 42 may be removed from the insulating layer 28' except at the via opening 68 (i.e., the area/location where the capacitive sensor 12 is to be formed). The removal of the portion of the MSM 40 and the portion of the transition layer 42 is shown in Fig. 8D. This removal corresponds with reference numeral 210 of the method 200 in Fig. 7. After the etching is performed, the MSM mask layer 70 is removed.

[0086] In Fig. 8E, the second metal layer 39 of the capacitive sensor 12 is formed and a clearing resistor 36 is formed. The formation of the second metal layer 39 involves forming the outer layer 74' on the transition layer 42 (reference numeral 212 of the method 200 in Fig. 7). In the example shown in Fig. 8E, one portion of electrically resistive layer 74' is deposited or deposited and patterned on the transition layer 42 to form the second metal layer 39 of the capacitive sensor 12, and a second portion of the electrically resistive layer 74 is deposited or deposited and patterned on both the contact 64 (and thus first metal layer 60) and the insulating layer 28' to form one layer of the clearing resistor 36.

[0087] In Fig. 8E, the clearing resistor 36 is a multi-layered structure 72. As shown in Fig. 8E, the multi-layered structure 72 may include the portion of the electrically resistive layer 74 and a high conductive layer 76.

[0088] In an example, the electrically resistive material may be deposited and patterned to form the portion/layer 74' of the second metal layer 39 and the portion/layer 74 of the clearing resistor 36. The layer 76 may be deposited and patterned together or separately with the portion of the electrically resistive layer 74 as desired to create the clearing resistor 36 (e.g., a thin-film resistor) using a sloped metal etch mask to etch high conductive layer 76 to expose electrically resistive layer 74, and to etch a bond pad 78. In an example, the high conductive layer 76 may include two bevels, between which the electrically resistive layer 74 is exposed.

[0089] In an example, the electrically resistive layers 74, 74' may have a thickness ranging from about 200 Angstroms to about 400 Angstroms, and the high conductive layer 76 may have a thickness of about 4800 Angstroms.

[0090] While not shown, it is to be understood that the clearing resistor 36 may also be formed of a single layer. In the multi-layer configuration shown in Fig. 8E, the electrically resistive layer 74 may be tantalum aluminum (TaAI) or

polycrystalline silicon (polysilicon), and may be applied by any suitable deposition technique. The high conductive layer 76 may be aluminum (Al) and may be applied by any suitable deposition technique, such as sputtering. In an example, the high conductive layer 76 may be patterned with a metal mask and etched to form metal traces for interconnections. For example, the high conductive layer 76 may be used to connect the wells 50, 52 of the transistor 46 to the clearing resistor 36. The high conductive layer 76 may also be used to connect various signals from the first metal layer 60 to the wells 50, 52 of the transistor 46.

[0091 ] As shown in Fig. 8F, to form the printhead 1 14, additional thin-film materials are applied to form: i) the passivation layer 30 over the clearing resistor 36; ii) the chamber layer 20 to define the fluid chamber(s) 14 (at least one of which is in fluid communication with the capacitive sensor 12, corresponding with reference numeral 214 of Fig. 7); and iii) the orifice plate 22 to define the bore exit(s) 31 .

[0092] The passivation layer 30 may be applied in contact with the clearing resistor 36 to protect the clearing resistor 36 from ink 32. Using a cavitation mask, for example, the passivation layer 30 may be patterned and etched in a desirable area.

[0093] The chamber layer 20 and orifice plate 22 may then be formed, also using masking and etching with suitable materials. The chamber layer 20 is formed to create fluid chambers 14 that are to be in fluid communication with the capacitive sensor 12 and (when present) the clearing resistor 36. In the example shown in Fig. 8F, each of the capacitive sensor 12 and the clearing resistor 36 is in contact with the fluid chamber 14. In this example, the orifice plate 22 is formed so that a bore exit 31 is in fluid communication with the fluid chamber 14 and is aligned with the clearing resistor 36. The chamber layer 20 and orifice plate 22 may also be formed such that the bond pad 78 is exposed.

[0094] As shown in Fig. 8F, an opening 49 may then be defined through downstream fluidics MEMS processing, such as laser drilling or some other suitable technique. The opening 49 fluidly connects the fluid slot 18 (not shown in Fig. 8F) and the chamber 14 and defines the ink flow path P.

[0095] Conductive ink 32 (not shown in Fig. 8F) may then be introduced to the chamber(s) 14 for ink level sensing when the chamber 14 includes the capacitive sensor 12 (and the sensing circuit 34, not shown in Fig. 8F, in electrical

communication therewith). The introduction of the ink 32 in contact with the second metal layer 39 forms the second plate of the capacitive sensor 12. [0096] It is to be understood that the components of the examples disclosed herein may be positioned in a number of different orientations, and any directional terminology used in relation to the orientation of the components is used for purposes of illustration and is in no way limiting, unless specified otherwise.

Directional terminology includes words such as "top," "bottom," etc.

[0097] It is to be further understood that the ranges provided herein include the stated range and any value or sub-range within the stated range. For example, a range from about 2 nm to about 50 nm should be interpreted to include the explicitly recited limits of about 2 nm to about 50 nm, as well as individual values, such as 2.5 nm, 15.75 nm, 35 nm, etc., and sub-ranges, such as from about 5 nm to about 45 nm, from about 10 nm to about 40 nm, etc. Furthermore, when "about" is utilized to describe a value, this is meant to encompass minor variations (up to +/- 10%) from the stated value.

[0098] Reference throughout the specification to "one example", "another example", "an example", and so forth, means that a particular element (e.g., feature, structure, and/or characteristic) described in connection with the example is included in at least one example described herein, and may or may not be present in other examples. In addition, it is to be understood that the described elements for any example may be combined in any suitable manner in the various examples unless the context clearly dictates otherwise.

[0099] In describing and claiming the examples disclosed herein, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise.

[0100] While several examples have been described in detail, it is to be understood that the disclosed examples may be modified. Therefore, the foregoing description is to be considered non-limiting.

Claims

What is claimed is:

1 . An on-chip ink level sensor, comprising:

a capacitive sensor, including:

a metal layer;

a memristor switching material having a thickness ranging from about

2 nm to about 50 nm positioned on the metal layer;

a second metal layer positioned on the memristor switching material; and

a substance in contact with the second metal layer;

wherein a capacitance of the capacitive sensor changes with a change in the substance;

a first switch to apply a voltage to the capacitive sensor, placing a charge on the capacitive sensor;

a second switch to share the charge between the capacitive sensor and a reference capacitor, resulting in a reference voltage; and

an evaluation transistor to provide a drain to source resistance in proportion to the reference voltage.

2. The ink level sensor as defined in claim 1 wherein an area of the capacitive sensor is 400 μιτι² or less.

3. The ink level sensor as defined in claim 1 wherein the capacitive sensor has a capacitance state and is switchable, as a memristor, to a low impedance resistor with less capacitance than the capacitance state in response to a first applied voltage, and wherein the capacitive sensor is resettable in response to a second applied voltage.

4. The ink level sensor as defined in claim 1 wherein the metal layer is aluminum or includes an alloy of copper and aluminum, and the second metal layer includes a transition layer selected from the group consisting of TaAI, TiN, and TaN, and an outer layer selected from the group consisting of TaAI and WSiN.

5. The ink level sensor as defined in claim 1 wherein the substance is selected from the group consisting of ink, air, and a combination of ink and air.

6. The ink level sensor as defined in claim 1 wherein the memristor switching material is a dielectric having a relative dielectric constant ranging from about 7.5 to about 60, and wherein the dielectric is selected from the group consisting of tantalum oxide, hafnium oxide, titanium oxide, yttrium oxide, niobium oxide, zirconium oxide, aluminum oxide, calcium oxide, magnesium oxide, dysprosium oxide, lanthanum oxide, silicon dioxide, and silicon nitride.

7. A printhead, comprising:

a substrate with a plurality of transistors formed in the substrate, the plurality of transistors coupled to a first metal layer;

a capacitive sensor of an ink level sensor, including:

a portion of the first metal layer;

a memristor switching material having a thickness ranging from about 2 nm to about 50 nm positioned on the portion of the first metal layer;

a second metal layer positioned on the memristor switching material; and

a substance in contact with the second metal layer; and a fluid chamber in contact with the second metal layer of the capacitive sensor, the fluid chamber containing the substance.

8. The printhead as defined in claim 7 wherein an area of the capacitive sensor is 400 μιτι² or less.

9. The printhead as defined in claim 7 wherein the capacitive sensor has a capacitance state and is switchable, as a memristor, to a low impedance resistor with less capacitance than the capacitance state in response to a first applied voltage, and wherein the capacitive sensor is resettable in response to a second applied voltage.

10. The printhead as defined in claim 7 wherein:

the substance is selected from the group consisting of ink, air, and a combination of ink and air; and

a capacitance of the capacitive sensor changes with a change in the substance.

1 1 . The printhead as defined in claim 7 wherein the memristor switching material has a relative dielectric constant ranging from about 7.5 to about 60.

12. The printhead as defined in claim 1 1 wherein:

the memristor switching material is formed of a memristor switching oxide of the first metal layer, and a portion of the memristor switching oxide is doped with oxygen vacancies to allow for memristor operation; or

the memristor switching material is formed of a memristor switching nitride, and a portion of the memristor switching nitride is doped with nitrogen vacancies to allow for memristor operation.

13. A method of manufacturing a capacitive sensor of an on-chip ink level sensor, the method comprising:

depositing an insulator layer over a plurality of transistors formed in a substrate interconnected by a first metal layer;

masking and etching the insulator layer to define a via and an area and location of the capacitive sensor, thereby exposing the first metal layer; applying a memhstor switching material (MSM) layer in the etched insulator layer above the exposed first metal layer to form a high quality dielectric material having a thickness ranging from about 2 nm to about 50 nm on a first plate of the capacitive sensor;

depositing a transition layer of a metal over the MSM layer;

masking and etching the transition layer and the MSM layer to remove the transition layer and the MSM layer from within the via and to not remove them in the location of the capacitive sensor;

forming an outer layer of a second metal layer of the capacitive sensor; and forming a fluid chamber in contact with the capacitive sensor.

14. The method as defined in claim 13, further comprising introducing a conductive ink into the fluid chamber and in contact with the second metal layer to form a second plate of the capacitive sensor.

15. The method as defined in claim 13 wherein the area of the capacitive sensor is 400 μιτι² or less.