WO2015184153A1 - Low cte component with wire bond interconnects - Google Patents

Low cte component with wire bond interconnects Download PDF

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Publication number
WO2015184153A1
WO2015184153A1 PCT/US2015/033007 US2015033007W WO2015184153A1 WO 2015184153 A1 WO2015184153 A1 WO 2015184153A1 US 2015033007 W US2015033007 W US 2015033007W WO 2015184153 A1 WO2015184153 A1 WO 2015184153A1
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WO
WIPO (PCT)
Prior art keywords
wire bonds
contacts
component
openings
wire
Prior art date
Application number
PCT/US2015/033007
Other languages
French (fr)
Inventor
Rajesh Katkar
Cyprian Emeka Uzoh
Original Assignee
Invensas Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Invensas Corporation filed Critical Invensas Corporation
Publication of WO2015184153A1 publication Critical patent/WO2015184153A1/en

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    • H—ELECTRICITY
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    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
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    • H01L21/4814—Conductive parts
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    • H01L21/4889—Connection or disconnection of other leads to or from wire-like parts, e.g. wires
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
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    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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    • H01L2924/0001—Technical content checked by a classifier
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • Subject matter described in the present application involves components which have wire bond vias extending in a direction of a thickness of an element having a low coefficient of thermal expansion (“CTE"), e.g., an interposer or microelectronic element, and method of their fabrication. Such component can be assembled with one or more other elements in a microelectronic assembly.
  • CTE coefficient of thermal expansion
  • Microelectronic devices such as semiconductor chips typically require many input and output connections to other electronic components.
  • the input and output contacts of a semiconductor chip or other comparable device are generally disposed in grid-like patterns that substantially cover a surface of the device (commonly referred to as an "area array") or in elongated rows which may extend parallel to and adjacent to each edge of the device's front surface, or in the center of the front surface.
  • areas array a surface of the device
  • devices such as chips must be physically mounted on a substrate such as a printed circuit board, and the contacts of the device must be electrically connected to electrically conductive features of the circuit board.
  • Semiconductor chips are commonly provided in packages that facilitate handling of the chip during manufacture and during mounting of the chip on an external substrate such as a circuit board or other circuit panel.
  • semiconductor chips are provided in packages suitable for surface mounting.
  • Numerous packages of this general type have been proposed for various applications.
  • Most commonly, such packages include a dielectric element, commonly referred to as a "chip carrier" with terminals formed as plated or etched metallic structures on the dielectric. These terminals typically are connected to the contacts of the chip itself by features such as thin traces extending along the chip carrier itself and by fine leads or wires extending between the contacts of the chip and the terminals or traces .
  • the package In a surface mounting operation, the package is placed onto a circuit board so that each terminal on the package is aligned with a corresponding contact pad on the circuit board. Solder or other bonding material is provided between the terminals and the contact pads .
  • the package can be permanently bonded in place by heating the assembly so as to melt or "reflow" the solder or otherwise activate the bonding material.
  • solder masses in the form of solder balls, typically about 0.1 mm and about 0.8 mm (5 and 30 mils) in diameter, attached to the terminals of the package.
  • a package having an array of solder balls projecting from its bottom surface is commonly referred to as a ball grid array or "BGA” package.
  • Other packages, referred to as land grid array or “LGA” packages are secured to the substrate by thin layers or lands formed from solder.
  • Packages of this type can be quite compact.
  • An interposer can be provided as an interconnection element having contacts and top and bottom surfaces thereof electrically connected with one or more packaged or unpackaged semiconductor dies at one of the top or bottom surface thereof, and electrically connected with another component at the other one of the top or bottom surfaces.
  • the other component may in some cases be a package substrate or circuit panel.
  • the package substrate may in turn be electrically connected with still another component which may be or may include a circuit panel.
  • a method for fabricating a component which may be an interposer or other device, e.g., microelectronic element or assembly including an interposer, microelectronic element, or combination thereof .
  • Such method can include forming a structure including a plurality of wire bonds each extending in an axial direction within an opening of one or more openings in an element and each wire bond spaced at least partially apart from a wall of the opening within which it extends, the element consisting essentially of a material having a coefficient of thermal expansion ("CTE") of less than 10 parts per million per degree Celsius (“ppm/°C”)-
  • the structure typically has first contacts at a first surface of the component and second contacts at a second surface of the component facing in a direction opposite from the first surface.
  • the first contacts may be first ends of the wire bonds or the first contacts may be coupled to first ends of the wire bonds.
  • the second contacts typically are electrically coupled with the wire bonds.
  • a thickness of the low CTE component can be increased beyond that which is typically possible using through-silicon via (“TSV”) processes.
  • TSV through-silicon via
  • the wire bond interconnect can be formed prior to being assembled within an opening of the low CTE element, eliminating a requirement of TSV processing wherein holes in a low CTE element are filled with a metal by deposition, e.g., plating.
  • plating e.g., plating.
  • the cost of plating within small holes exponentially increases with the depth of the holes.
  • semiconductor elements and active chips which have TSVs typically require thinning to a thickness of 100 microns or less to permit forming the TSVs by filling with a deposited metal. This requirement has led the industry into other difficulties, most notably difficulties with handling of thin wafers.
  • the thickness of a low CTE component or interposer taught herein can be much greater than that of a thinned wafer in which TSVs are formed.
  • a low CTE component may be formed from an element or block consisting essentially of low CTE material in which the thickness thereof may be greater than 50 microns, or in one example may be from 0.5 millimeter to two millimeters. In a particular example, the thickness may be about one millimeter.
  • thinning of the low CTE component during processing may not be required at all, since wire bonds can be formed which extend in a vertical direction equal to the thickness of the low CTE component .
  • incorporation of such low CTE component in a microelectronic assembly can help to address possible warpage problems when thinner low CTE interposers or chips are combined with other elements having higher CTEs. This is due at least in part to a greater thickness, e.g., up to one millimeter, of the low CTE component which is possible using the structure and methods disclosed herein.
  • the openings in the element may be uncovered by any portion of the element and may be uncovered by any other element having a CTE of less than 10 ppm/°C.
  • the forming the structure includes providing a first element having a plurality of wire bonds extending upwardly away therefrom.
  • the wire bonds may be inserted into one or more openings in the element having the CTE of less than 10 ppm/°C.
  • the method may further comprise forming at least one of: a first redistribution layer electrically coupled between the wire bonds and the first contacts, or a second redistribution layer electrically coupled between the wire bonds and the second contacts.
  • forming the structure may further include forming the wire bonds such that first ends of the wire bonds are formed on metallic elements of a first redistribution layer, and then inserting each wire bond into an opening of the one or more openings .
  • forming the structure may include inserting individual wire bonds of the plurality of wire bonds into respective openings in the element, such that each wire bond may be separated from each other wire bond by material of the element .
  • the openings may be blind openings when the individual wire bonds may be inserted therein, and the method further comprises reducing a thickness of the element after the inserting to provide access to ends of the wire bonds.
  • the inserting may comprise inserting some of the plurality of the wire bonds into a same opening of the plurality of openings .
  • an electrically insulative material may be provided within the openings in contact with the wire bonds .
  • the element may include a plurality of active devices, at least some of the first or the second contacts being electrically coupled with the plurality of active devices .
  • the element may include a monocrystalline semiconductor region, and at least some of the active devices may be disposed at least partially within the monocrystalline semiconductor region, the openings extending at least partially through the monocrystalline semiconductor region.
  • a component which comprises a plurality of wire bonds each extending in an axial direction within an opening of one or more openings in an element having a coefficient of thermal expansion ("CTE") of less than 10 parts per million per degree Celsius (“ppm/°C”) .
  • CTE coefficient of thermal expansion
  • ppm/°C parts per million per degree Celsius
  • Each wire bond can be spaced at least partially away from a wall of the opening within which it extends.
  • the component can further comprises first contacts at a first surface of the component and second contacts at a second surface of the component facing in a direction opposite from the first surface.
  • the first contacts may be first ends of the wire bonds or the first contacts may be coupled to first ends of the wire bonds.
  • the second contacts may be electrically coupled with the wire bonds .
  • the first contacts or the second contacts may be electrically coupled with the wire bonds through a redistribution layer overlying the wire bonds and overlying a surface of the element defining a plane transverse to the axial direction of the openings .
  • individual wire bonds of the plurality of wire bonds may be disposed within respective openings in the element, such that each wire bond may be separated from each other wire bond by material of the element.
  • some of the plurality of the wire bonds may be disposed within a same opening of the plurality of openings .
  • an opening may not have a wire bond disposed therein.
  • an electrically insulative material can be within the openings in contact with the wire bonds.
  • the electrically insulative material may touch or surround only portions of the wire bonds adjacent the first ends of the wire bonds, or only portions of the wire bonds adjacent the second ends of the wire bonds which are opposite the first ends, or may touch or surround only the first and the second ends of the wire bonds .
  • the element may include a plurality of active devices, wherein the first and second contacts may be electrically coupled with one another and with at least some of the plurality of active devices.
  • the element may include a monocrystalline semiconductor region, at least some of the active devices being disposed at least partially within the monocrystalline semiconductor region, and the openings extending at least partially through the monocrystalline semiconductor region.
  • the first contacts and the second contacts may be within an axial distance of less than 50 microns from the wire bonds .
  • the wire bonds may extend only partially through a thickness of the element, and the component may further comprise electrically conductive connectors extending in an axial direction from the wire bonds at least partially through a remaining portion of the thickness of the element, the connectors formed of deposited electrically conductive material.
  • the component may further comprise electrically conductive connectors extending in an axial direction from the wire bonds at least partially through a remaining portion of the thickness of the element, the connectors formed of deposited electrically conductive material. may be may be may be may be
  • At least one of: the first contacts or the second contacts may be not electrically coupled with the wire bonds through a redistribution layer overlying the wire bonds and a surface of the element defining a plane transverse to the axial direction of the openings.
  • the wire bonds may comprise wires having different diameters and the diameter of one wire bond may be larger than the diameter of the other wire bonds in one example, by at least 3%, or in another example, by at least 10%.
  • the length of at least one wire bond may be shorter than the length of other wire bonds by less than 20% of the length of the other wire bonds .
  • individual wire bonds of the plurality of wire bonds may be disposed within respective openings in the element, such that at least one or more of the wire bonds may be not separated from each other wire bond by material of the element .
  • individual wire bonds of the plurality of wire bonds may be disposed within respective openings in the element.
  • one or more of the openings in the element may not contain a wire bond.
  • individual wire bonds of the plurality of wire bonds may be disposed within respective openings in the element, and at least one or more openings in the element comprise dielectric material.
  • Fig. 1A is a sectional view of a component such as an interposer in accordance with an embodiment of the invention, as interconnected within a microelectronic assembly .
  • Fig. IB is a sectional view of an alternative component such as an interposer in accordance with an embodiment of the invention, as interconnected within a microelectronic assembly.
  • Fig. 2A is a sectional view of a component such as an interposer in accordance with a variation of an embodiment seen in Fig. 1A or IB, as interconnected within a microelectronic assembly.
  • Fig. 2B is a corresponding plan view of a component such as an interposer within a microelectronic assembly .
  • Fig. 2C is a sectional view of an interposer as interconnected within a microelectronic assembly in accordance with a further variation of an embodiment seen in Figs . 2A and 2B .
  • Fig. 3 is a sectional view of component in accordance with an embodiment of the invention.
  • FIG. 4 is a plan view of an interposer in accordance with an embodiment of the invention.
  • Fig. 5 is a sectional view of an in-process element for incorporation in a component in a fabrication method according to an embodiment of the invention.
  • Fig. 6 is a plan view and Fig. 7 a corresponding sectional view of a low CTE element for incorporation in a component in a fabrication method according to an embodiment of the invention.
  • Figs. 7, 8, 9, 10 and 11 are sectional views illustrating stages in a method of fabricating a component as seen in Fig. 3 in accordance with an embodiment of the invention .
  • FIGs. 12, 13, 14, and 15 are sectional views illustrating stages in a method of fabricating a component according to a variation of an embodiment of the invention.
  • Figs. 16, 17 and 18 are sectional views illustrating stages in a method of fabricating a component according to a variation of an embodiment of the invention.
  • Figs. 19 and 20 are sectional views illustrating stages in a method of fabricating a component according to a variation of the embodiment illustrated in Figs. 16, 17 and 18.
  • Figs. 21, 22 and 23 are sectional views illustrating stages in a method of fabricating a component according to a variation of the embodiment illustrated in Figs. 16, 17 and 18.
  • Figs. 24, 25, 26, 27 and 28 are sectional views illustrating stages in a method of fabricating a microelectronic element in accordance with an embodiment of the invention.
  • interposers, microelectronic elements, and microelectronic assemblies which include such components are described herein which comprise an element made of material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius ("low CTE material"), typically being a solid monolithic block of semiconductor material such as silicon, a III-V semiconductor compound such as GaAs, InP, etc., or a dielectric material such as a glass, quartz, alumina (e.g., A1203) or other ceramic material, among others.
  • a plurality of wire bond interconnects extend in an axial direction within one or more openings which extend through the thickness of the low CTE element.
  • Components having low CTE can be utilized advantageously in applications where differential thermal expansion ordinarily would be a concern when a low CTE component is assembled in close proximity with another component having relatively high CTE and subjected to high thermal stress.
  • first contacts at the first surface of the component are interconnected with second contacts at the second surface of the component by wire bonds.
  • Use of wire bonds as vertical interconnects extending through the thickness of the element may in some cases lead to reductions in fabrication costs and tooling costs.
  • Wire bonds can be made to project to substantial distances of tens to hundreds of microns or more above a surface of underlying structure to which they are bonded, and hence can be made to provide vertical interconnects through relatively deep openings in an element.
  • wire bond vertical interconnects can help avoid costs associated with thinning and handling of thinned elements such as thinned semiconductor wafers, among others, and use of such wire bond vertical interconnects can help avoid costs associated with forming and filling of high aspect ratio openings with deposited metal to form the vertical interconnects .
  • Each wire bond interconnect has no more than one end bonded to an underlying metal surface at a location proximate the first surface, and another end of each wire bond remote from such end unbonded and proximate the second surface .
  • Fig. 1A illustrates a microelectronic component 10 such as may be constructed in accordance with an embodiment described herein, as further assembled in a microelectronic assembly 100 with other components as well.
  • first and second contacts 46, 16 are provided at first and second opposite surfaces of the component 10, respectively. Contacts 46, 16 may in turn be electrically connected with corresponding contacts of first and second components of the microelectronic assembly which face those contacts 46, 16.
  • Components described herein such as interposers, substrates, circuit panels, microelectronic elements, and the like typically have dielectric structure at external surfaces thereof. Accordingly, as used in this disclosure, a statement that an electrically conductive element is "at" a surface of dielectric structure of a component, indicates that, when the component is not assembled with any other element, the electrically conductive element is available for contact with a theoretical point moving in a direction perpendicular to the surface of the component toward the surface of the component from outside the component. Thus, a terminal, a contact, or other conductive element which is at a surface of a component may project from such surface; may be flush with such surface; or may be recessed relative to such surface in a hole or depression in the component.
  • component 10 e.g., an interposer, having a low CTE element 19 may be electrically connected with a first component 12 having active circuit elements thereon, such as a microelectronic element, e.g., a packaged or unpackaged semiconductor die which has a face 13 facing towards the first surface 144 of the component 10 and be packaged or unpackaged as connected to the first contacts 46 of the interposer.
  • the second contacts 16 of the interposer can be electrically connected with corresponding contacts of another component of the assembly which face the contacts 16, such as contacts of a package substrate 20 in the example illustrated in Fig. 1A.
  • the first and second contacts 46, 16 can be electrically coupled through wire bonds 32 which function as vertical interconnects extending in a direction of a thickness of a low CTE element 19 of the component 10 each wire bond extending within an opening of one or more openings in the low CTE element 19.
  • a direction of the thickness of element 19 is defined as an axial direction of the component 10 and a distance in the axial direction is an axial distance.
  • a thickness of the low CTE element 19 in the axial direction can be greater than 50 microns.
  • the thickness may be between 50 microns and 1 millimeter.
  • the thickness may be within a range from 0.5 millimeter to 2 millimeters .
  • the first contacts or the second contacts, or both the first contacts and second contacts can be ends of the wire bonds.
  • the ends of the wire bonds may be ball bonds which at least partially remain after the fabrication process.
  • the ends of some of the wire bonds 32 may be contacts or may be mechanically coupled to such contacts, but such wire bonds may not all be electrically coupled with another component through contacts 46 at the first surface 144 and contacts 16 at the second surface. In a particular embodiment, there may be only one wire bond in component 10.
  • component 10 may be an interposer for electrically coupling a first component above the interposer, such as, for example, a microelectronic element 12, with a second component such as package substrate 20.
  • a first component above the interposer such as, for example, a microelectronic element 12
  • a second component such as package substrate 20.
  • some or all of the second contacts 16 may be connected with a second unpackaged or packaged semiconductor die having a surface facing the second surface 114 of the component.
  • Package substrate 20 or other component interconnected with the component 10 can, in turn be mounted to contacts 51 of a circuit panel 50, as shown in Fig. 1A.
  • the package substrate 20 may be omitted from microelectronic assembly 100 and the contacts 16 of the component 10 can be electrically coupled with corresponding contacts 51 of a circuit panel 50.
  • the package substrate 20 may be omitted from microelectronic assembly 100 and the contacts 16 of the component 10 can be electrically coupled with corresponding contacts 51 of a circuit panel 50.
  • the component 10 and the microelectronic element 12 joined thereto can form a "chip-scale package” or "CSP" .
  • Fig. IB illustrates a microelectronic assembly 102 according to a further example in which first and second microelectronic elements 12, 52 can be electrically interconnected with a component 11 through first contacts 46 at a first surface 144 of the component 11.
  • the microelectronic elements which may be packaged or unpackaged semiconductor dies, may be electrically interconnected with one another through conductive structure provided on the component 11, such as traces 54 thereon, which may extend in a direction parallel to a first surface 114 of the component.
  • Figs. 2A-2B illustrate an alternative manner in which microelectronic elements 12A, 12B may be electrically coupled with a component 10 such as an interposer.
  • the microelectronic elements 12A, 12B are coupled via wire bonds 35 with the contacts 46 at an upper surface of the interposer.
  • the contacts 46 may in some cases be ends of the wire bonds 32 which extend in the axial direction of the low CTE element of the component.
  • a redistribution structure can be disposed between ends of the wire bonds 32 and contacts 46, or between ends of the wire bonds 32 and contacts 16, or between both ends of the wire bonds and the contacts 46 and 16.
  • FIG. 2C illustrates a further variation in which microelectronic elements 112A and 112B have contact-bearing faces which face an upper surface of the component 10.
  • Fig. 2C further illustrates an additional microelectronic element 112C which may be electrically coupled with the component 10, such as in a face-up configuration with one or more wire bonds 35 coupled to contacts on the upwardly-facing surface 113 of the microelectronic element 112C and one or more contacts 46 of component 10.
  • Fig. 2C further illustrates an assembly further including a substrate 20 electrically coupled with contacts 16 at a lower surface of component 10.
  • a partial sectional view is shown further illustrating a component 10 such as shown and described above with reference to Fig. 1 or Fig. 2.
  • a plurality of wire bonds 32 extend as vertical interconnects through at least one opening 38 extending through a thickness of a low CTE element 19.
  • Low CTE element typically may comprise a solid monolithic element consisting essentially of low CTE material through which opening 38 extends.
  • the low CTE element may consist essentially of semiconductor material, e.g., silicon, germanium, a III-V semiconductor compound, or a solid block of dielectric material such as glass, quartz, or ceramic material (such as, for example, A1203), among others.
  • a dielectric material 40 may be disposed within opening 38 and may contact edge surfaces 37 of individual ones of the wire bonds 32.
  • the dielectric material 40 may fill the opening; however, in other embodiments provided herein, some portion or all of the edge surface 37 of a particular wire bond or each wire bond may not be contacted by a dielectric material.
  • An electrically conductive redistribution layer which may be insulated and/or supported by a dielectric layer 118 may electrically couple first ends 33 of wire bonds 32 with contacts 16.
  • a redistribution layer which may be insulated and/or supported by dielectric layer 152 may electrically couple second ends 39 of wire bonds with contacts 46.
  • the redistribution layer may be formed in accordance with processing typically used to form a redistribution layer on a surface of an existing component such as an interposer or semiconductor chip, wherein "layer” may mean a structure typically formed by "post-fab” processing after forming a wafer including semiconductor chips having active devices thereon in a "fab", the structure including one or more layers of dielectric material and one or more metal layers which can extend parallel to a surface thereof.
  • a plurality of the metal layers may be interconnected with one another by interconnects extending in a vertical direction extending through a thickness of at least one of the metal layers.
  • the redistribution layer can be a "back end of line” or "BEOL” structure formed by fabrication methods typically utilized in a "fab”.
  • the redistribution layer can include a BEOL structure and a post-fab portion formed thereon or electrically coupled therewith.
  • Joining elements 17, e.g., solder balls or other masses of bonding metal or electrically conductive material can be attached or formed on contacts 16. Similar masses or solder balls can be attached or formed on contacts 46.
  • the wire bonds 32 can be made of copper, gold or aluminum, and may in certain cases have a finish layer of a different metal exposed at an exterior surface of the wire bonds .
  • the diameter of each wire bond may illustratively be between 1 and 500 micrometers ("microns") in diameter.
  • the minimum pitch of adjacent wires in the in-process element may range from a minimum of around twice the smallest diameter of the wire, to a number which may be an even smaller multiple of the wire diameter when the wire diameter is relatively large.
  • the first and second contacts 46, 16 may be within an axial distance of less than 50 micrometers ("microns") from the wire bonds 32 to which they are electrically coupled.
  • Fig. 4 is a corresponding plan view looking toward either a top surface 144 or, alternatively, a bottom surface 114 of the component 10.
  • the first and second contacts 46, 16 can be made to extend in a lateral direction parallel to the top or bottom surfaces 144,114 beyond an edge surface 37 of the respective wire bond 32, as seen in the case of contacts 46A and 16A. Fabrication of component 10 can be as further described below.
  • a method of fabricating a component 10 such as an interposer will now be described.
  • an in-process element 45 can include an array of unterminated wire bonds 32 are formed extending upwardly from one or more metal surfaces to which the wire bonds are joined.
  • This wire bond array may be formed by forming wire bonds by bonding metal wire to one or more surfaces at different locations thereof, which may be locations of an array, and which may be one or more metal surfaces or a surface of a metal sheet below the wire bonds.
  • the wire bonds 32 can be formed by bonding wires to one or more surfaces such as surfaces of contacts, or to a surface of a metal sheet 42.
  • the metal sheet 42 need not provide full mechanical support for itself or for the wire bonds 32, as that function may be performed by a supporting carrier 43 which may be releasably attached or clamped to the sheet.
  • a bonding tool can bond the metal wire to an exposed surface of a layered structure which includes an unpatterned or patterned metal sheet, and which may includes one or more finish metal layers thereon.
  • wire bonds can be formed on a base having a metal layer of aluminum, copper or alloy thereof or the like, and the finish layers in one example, may include an "ENIG" finish, such as a layer of nickel deposited on the base metal by electroless deposition, followed by a layer of gold deposited on the nickel layer by an immersion process.
  • the base metal layer can have an "ENEPIG" finish, such as may be a combination of a layer of electrolessly deposited nickel deposited on the base metal, followed by a layer of electrolessly deposited palladium deposited thereon, and followed by a layer of gold deposited on the palladium by an immersion process .
  • ENEPIG "ENEPIG” finish
  • Wire bonds can be formed by bonding a metal wire to a surface by a technique as previously described in one or more of the aforementioned commonly owned and incorporated United States Applications.
  • wire bonds can be formed by ball bonding a metal wire to the surface, such as by heating the wire at a tip thereof to form a ball of molten metal and contacting the surface with the ball to form the ball bond so as to form a bulbous portion of the wire as a first end 33 or base of the wire bond, as shown in Fig. 3 for example.
  • the base of the wire bond may have a shape similar to a ball or a portion of a ball when the base is formed by ball bonding.
  • a wire bond having a base formed by ball bonding may have a shape and may be formed as described, for example, in United States Patent Application No. 13/462,158, the disclosure of which is incorporated by reference herein.
  • a wire bond may be formed by other techniques such as stitch bonding or wedge bonding in which a portion of the edge surface of a wire is bonded to a surface and may have a shape generally as seen for example, in United States Patent Application Nos . 13/404,408; 13,404,458; 13/405,125, the disclosures of which are incorporated by reference herein.
  • the base 33 may have a somewhat flattened cylindrical shape which may extend at a substantial angle (e.g., 15 to 90 degrees) away from the shaft.
  • An upwardly extending shaft portion 31 (Fig. 3) of the wire bond need not extend vertically relative to the bonded base 33, but rather can extend at a substantial angle therefrom (e.g., 15 to 90 degrees) .
  • Particular examples of the wire bonds formed this way can be as described in these incorporated applications.
  • Figs. 6 and 7 are a plan view and a cross-sectional view, respectively, of a low CTE element 19 as described above having a plurality of openings 38 therein, with portions 48 of the low CTE element 19 between adjacent openings extending to a greater thickness.
  • the openings can be as yet blind openings in that each opening may not extend entirely through a thickness of the low CTE element as seen in Fig. 7.
  • Openings 38 typically are formed by optical or mechanical ablation such as by laser, mechanical milling, dry and wet etching methods. In the example seen in Figs.
  • each opening may be sized to accommodate a plurality of adjacent wire bonds which may extend in a row in a first direction 60, and in some cases, may also extend in a column in a second direction 61 transverse to the first direction. Accordingly, each opening 38 may have a size which extends in one or more of the first and second directions 60, 61 for dimensions in each direction of tens of microns to hundreds of microns .
  • the in-process element 45 of Fig. 5 is united with low CTE element 19 of Figs. 6-7 to form in-process element 47.
  • low CTE element 19 is inverted relative to the orientation shown in Fig. 7 and then united with the in-process element 45.
  • an adhesive 49 can be provided atop bases of wire bonds 32, the adhesive bonding the portions 48 of the low CTE element 19 between the openings.
  • the low CTE element 19 may be placed in close proximity to or atop the in-process element 45 and then an underfill can be made to flow horizontally into a gap between the in-process element 45 and the low CTE element to form the structure shown in Fig 8.
  • the adhesive 49 can be a punched adhesive film or a patterned dispensed adhesive that bonds the portions 48 of the low CTE element 19 with the top surface of a metal sheet such as the metal sheet 42 of in-process element 45 shown in Fig. 5. As seen in Fig. 8, the adhesive 49 may touch or flow to the wire bonds 32. Alternatively, the adhesive 49 may not touch or flow to the wire bonds 32.
  • the low CTE element can be thinned from the top, such as, for example, by abrasive, milling chemical, polishing or ion process, or combination thereof, until the openings are exposed at the top.
  • abrasive, milling chemical, polishing or ion process, or combination thereof can be used to thin the low CTE element.
  • etching such as a reactive ion etching or plasma etching process can be used.
  • grinding, lapping or polishing can be used for coarse thinning of the low CTE element, which can be followed by selective reactive ion etching of the dielectric fill 40 to cause ends 39 of the wire bonds 32 to project above surfaces of the portions 48 of the low CTE element between the openings 38.
  • the openings can then be filled with a suitable dielectric material 40.
  • the dielectric material can be selected so as not to interfere with operation of the component 10 which in some cases may need to be used in an environment which undergoes rapid or extreme temperature fluctuations. Therefore, it may be beneficial in some cases to provide a low CTE dielectric material 40 within the openings which may have a relatively low CTE (e.g., having a CTE of less than 12 ppm/°C, or which may be the same or close to that of low CTE element.
  • molten glass is one possible low CTE filler material which can be used as the filler dielectric material 40.
  • openings can be filled with a material having a relatively high CTE, but which can be a compliant material such as a polymeric material, such material having a low Young's modulus.
  • the dielectric fill 40 may comprise a porous polymer, for example, porous polyimide .
  • the dielectric material 40 may comprise may comprise more than one type of dielectric material.
  • the majority of the dielectric may be a layer of porous polyimide or other dielectric material and such layer can be capped with an oxide, which in one example may be an oxide deposited from a tetraethyl orthosilicate (TEOS) precursor.
  • TEOS tetraethyl orthosilicate
  • the TEOS layer may comprise the RDL over ends 39 of the wire bonds surface 39.
  • the portion of the filler dielectric material extending above the portions 48 of the low CTE element is removed and ends 39 of the wire bonds can be exposed by a reveal process.
  • a redistribution layer or back end of line (“BEOL") interconnect layer can be formed atop the ends 39 of the wire bonds 32, wherein contacts 46 and optionally traces of the redistribution layer can be provided.
  • BEOL back end of line
  • the carrier 43 can then be removed and metal sheet 42, if present, can be removed, resulting in the component 10 such as seen in Fig 11, for example, or as shown and described above with reference to Fig. 3.
  • the metal sheet may be patterned to fabricate a redistribution layer or to form electrical contacts such as first contacts 46 or second contacts 16.
  • Fig. 12 illustrates a stage of fabrication in accordance with a variation of the embodiment described above relative to Figs. 5-11.
  • an in-process element 55 may comprise wire bonds 32 formed atop a redistribution layer or BEOL having traces 54 and contacts 46 pre-formed therein, the redistribution layer disposed atop carrier 43.
  • the carrier 43 may comprise a chip, a package or unpackaged device.
  • the wire bonds 32 may comprise wires of different diameters. In such example, the diameters of one or more wires may be bigger than the diameters of other wires by at least 3%. Also, the diameters of one or more wires may be bigger than the diameters of other wires by at least 10%.
  • Fig. 12 illustrates a stage of fabrication in accordance with a variation of the embodiment described above relative to Figs. 5-11.
  • an in-process element 55 may comprise wire bonds 32 formed atop a redistribution layer having traces 54 and contacts 46 pre-formed therein, the redistribution layer disposed atop carrier 43.
  • Figs. 13-14 illustrate stages of fabrication in which the in-process element 55 is united with low CTE element 19, and a dielectric material is added thereto, in like manner to that described above relative to Figs. 8 and 9.
  • Fig. 15 illustrates a further stage of processing in which contacts 16 or 16B can be formed in electrical communication with the wire bonds 32.
  • contacts 16 can be formed atop the dielectric fill 40 and contacts 16B can be formed in depressions extending from a surface 53 of the dielectric fill to the wire bonds 32.
  • the dielectric fill 40 may extend to a height above a height of the surface 121 of the low CTE element 19, for example, when contacts are formed in a manner as shown in 16B.
  • the top surface of the dielectric fill 40 can be aligned with the surface 121 of low CTE element 19.
  • one or more wire bonds 32 are shorter than the other.
  • one or more wire bonds are shorter than other wire bonds by less than 20% of the length of the other wire bonds.
  • one or more wire bonds are shorter than other wire bonds by more than 10% of the length of the other wire bonds .
  • Figs. 16-18 illustrate a variation of the above embodiment described relative to Figs. 3-11, in which each opening 138 in a low CTE element 119 is sized to accommodate a single wire bond.
  • a cylindrical shaft of each wire bond 32 of in-process element 155 can extend vertically within a single opening 138 in the low CTE element.
  • each opening 138 can be lined with a dielectric material (not shown) before uniting the in-process element therewith.
  • dielectric liner can be deposited or formed thereon by a number of possible processes which may include chemical vapor deposition, local oxidation or nitridation, among others.
  • FIG. 17 and 18 illustrate stages in a process of fabrication which are analogous to those shown in Figs. 13 and 14, wherein a dielectric fill can be formed in the openings 138 after the low CTE element has been united with the in-process element 155.
  • Fig. 18 further illustrates an exemplary component 110, e.g., interposer, formed in this manner.
  • one or more of openings 138 may not contain a wire bond.
  • an opening 138 which lacks a wire bond therein may contain dielectric material.
  • Such opening 138 may be partially or completely filled with a dielectric material.
  • an uncured dielectric material 140 e.g., a liquid material may be present in openings 138 prior to the wire bonds 32 being inserted therein. In such manner, the deposition or filling of a dielectric material after thinning the low CTE element 119 may be avoided or may be further facilitated or aided thereby.
  • the openings may not be filled with a dielectric material, but instead the axial dimension of each opening can be allowed to remain either partially or substantially completely unfilled by a dielectric material. For example, only the top and bottom ends of each opening may be plugged. In such case, air or a void remaining within each opening in the final component can serve as a dielectric having an even lower permittivity than a solid polymeric or inorganic dielectric material that may otherwise be used.
  • Figs. 19 and 20 illustrate a further variation in which a redistribution layer comprising traces 54 and contacts 46 can be formed atop the wire bonds 32 after the low CTE element 119 and a corresponding in-process element 157 are united.
  • a completed component 210 such as an interposer is illustrated in Fig. 20.
  • Figs. 21-23 illustrate another variation of the above-described process.
  • an in-process element 159 having wire bonds 32 extending therefrom is juxtaposed with low CTE element 119 such that a gap exists between the two which can accommodate flow of a dielectric material in fluid form for the purpose of filling each opening 138.
  • a dielectric material 140 can be flowed into each opening.
  • the low CTE element then can be thinned and contacts and conductive masses, e.g., solder masses added thereto to form a component 310 such as an interposer.
  • the dielectric fill material can be inorganic or polymeric material as described above.
  • the flow may be in gaseous form, such as for deposition of a dielectric coating within openings such as parylene, among others.
  • Processing in accordance with the variation seen in Figs. 21-23 to form the dielectric fill layer can be performed in any or all of the above-described embodiments.
  • the resulting component 410 is a microelectronic element, which may comprise a semiconductor chip through which wire bonds 132 extend in a direction of a thickness thereof for purposes of providing electrical interconnects between contacts 46 provided at a first surface 144 of the component 410 and contacts 16 provided at a second surface 114 of the component opposite from the first surface.
  • the microelectronic element may include a semiconductor region 419 through which wire bonds 132 extend, the semiconductor region typically formed of monocrystalline semiconductor material, but which may have a different crystalline structure in an appropriate case .
  • a plurality of active devices 421 are disposed at least partially in the semiconductor region 419, which may be transistors, diodes, or any of a variety of active devices which may comprise and utilize semiconductor regions as part of their functional structure.
  • a horizontal and vertical interconnect structure 148 which may include multiple interconnect layers such as a back end of the line (“BEOL") wiring structure or a redistribution structure, the interconnect structure being formed atop the semiconductor region 419.
  • Electrically conductive, e.g., metallic connectors 149 can electrically couple the wire bonds 132 and the interconnect structure 148 of the component 410, and may be disposed between the wire bonds and interconnect structure.
  • a dielectric fill material 440 can be disposed within the openings 438 surrounding each wire bond.
  • the dielectric fill material can be omitted, or the dielectric material may only plug the top or bottom ends or both ends of the openings 438.
  • the openings 438 may only be lined with a dielectric material as described above but not filled.
  • a process of fabricating a component such as seen in Fig. 28 can comprise uniting an in-process element 465 (Fig. 24) with a microelectronic element 470 (Fig. 25) having a plurality of active devices already formed therein.
  • the process may be considered a "via middle” process because vertical interconnects formed by the wire bonds 132 are formed after high temperature fabrication of the active devices in the semiconductor region is completed, but before the interconnect structure 148 (Fig. 28) has been formed.
  • Fig. 28 the interconnect structure 148
  • a set of openings 438 have been formed extending from a back surface 471 of the microelectronic element 470 towards a front surface 472 thereof at which active devices 421 can be disposed, the openings each sized to accommodate either a single wire bond or a plurality of wire bonds and the spacing between adjacent wire bonds.
  • the openings can be formed by any number of techniques which may involve mechanical, chemical or optical (e.g., laser ablation), techniques, among others.
  • the openings 438 extend partially through a thickness of the semiconductor region 419.
  • a carrier 443 may be attached to a front surface 472 of the semiconductor region while the openings are being formed .
  • Fig. 26 illustrates a subsequent stage of fabrication in which the in-process element 465 is united with the microelectronic element 470 and an optional dielectric fill material 440 may be provided within the openings.
  • the carrier may also be removed.
  • front surface openings 458 can then be formed extending from the front surface of the microelectronic element in alignment with the wire bonds 132.
  • a dielectric liner can then be formed within the front surface openings, after which an electrically conductive material can then be deposited into the openings to form metallic connectors 149 as seen in Fig. 28.
  • metallic connectors may be formed by various vapor deposition or plating processes, or combination thereof.
  • component may include wire bonds of substantial length in which the cylindrical shaft portion thereof may extend for tens to hundreds of microns.
  • the shaft of each wire bond may have a length from 50 microns to one millimeter .
  • microelectronic elements 410 fabricated in accordance with an embodiment of the invention can be stacked atop one another in a die stack, wherein the wire bonds 132 and connectors 149 and the interconnect structure 148 can function as through silicon vias ("TSVs").
  • TSVs through silicon vias
  • a surface 114 of a microelectronic element 410 fabricated in this way may occupy the same area as the surface of the original semiconductor chip and have peripheral edges bounding that area which correspond to the edges of the original semiconductor chip from which it is made.
  • the component 410 or processed microelectronic element can be referred to as a "chip-scale package" or "CSP" .
  • the wire bonds 32 on a metal sheet 42 could be formed atop a circuit panel or a microelectronic element such as a semiconductor chip.
  • the circuit panel or semiconductor chip instead of removing the underlying structure supporting the wire bonds, e.g., metal sheet 42, circuit panel or semiconductor chip, the circuit panel or semiconductor chip can be allowed to remain in a microelectronic assembly which includes the interposer element and the underlying circuit panel or semiconductor chip .
  • one or more additional components which may be active components, passive components, or combination thereof, can be pre-mounted on the underlying structure, e.g., a metal sheet, microelectronic element, or circuit panel, and such additional component (s) can then become embedded within the dielectric fill inside the opening in the completed component or interposer.
  • the openings in the low CTE element may extend through the entire thickness of the low CTE element before the wire bonds are inserted therein, such that there is no material of the low CTE element overlying the wire bonds in an axial direction of the wire bonds. In such case, thinning of the low CTE element described above to expose the openings 38 from the top of the low CTE element (such as thinning of the element 19 shown in Fig. 9) can be omitted.

Abstract

A component (10) such as an interposer or microelectronic element can be fabricated with a set of vertically extending interconnects (32) of wire bond structure. Such method may include forming a structure having wire bonds (32) extending in an axial direction within one of more openings (38) in an element (19) and each wire bond spaced at least partially apart from a wall of the opening within which it extends, the element (19) consisting essentially of a material having a coefficient of thermal expansion ("CTE") of less than 10 parts per million per degree Celsius ("ppm/C"). First contacts (46) can then be provided at a first surface of the component and second contacts (16) provided at a second surface (114) of the component (10) facing in a direction opposite from the first surface (144), the first contacts (46) electrically coupled with the second contacts (16) through the wire bonds (32).

Description

LOW CTE COMPONENT WITH WIRE BOND INTERCONNECTS
CROSS-REFERENCE TO RELATED APPLICATIONS
[ 0001 ] The present application is a continuation of U.S. Patent Application No. 14/289,860, filed May 29, 2014, the disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
Field of the Invention
[ 0002 ] Subject matter described in the present application involves components which have wire bond vias extending in a direction of a thickness of an element having a low coefficient of thermal expansion ("CTE"), e.g., an interposer or microelectronic element, and method of their fabrication. Such component can be assembled with one or more other elements in a microelectronic assembly.
Description of the Related Art
[ 0003 ] Microelectronic devices such as semiconductor chips typically require many input and output connections to other electronic components. The input and output contacts of a semiconductor chip or other comparable device are generally disposed in grid-like patterns that substantially cover a surface of the device (commonly referred to as an "area array") or in elongated rows which may extend parallel to and adjacent to each edge of the device's front surface, or in the center of the front surface. Typically, devices such as chips must be physically mounted on a substrate such as a printed circuit board, and the contacts of the device must be electrically connected to electrically conductive features of the circuit board.
[ 0004 ] Semiconductor chips are commonly provided in packages that facilitate handling of the chip during manufacture and during mounting of the chip on an external substrate such as a circuit board or other circuit panel. For example, many semiconductor chips are provided in packages suitable for surface mounting. Numerous packages of this general type have been proposed for various applications. Most commonly, such packages include a dielectric element, commonly referred to as a "chip carrier" with terminals formed as plated or etched metallic structures on the dielectric. These terminals typically are connected to the contacts of the chip itself by features such as thin traces extending along the chip carrier itself and by fine leads or wires extending between the contacts of the chip and the terminals or traces . In a surface mounting operation, the package is placed onto a circuit board so that each terminal on the package is aligned with a corresponding contact pad on the circuit board. Solder or other bonding material is provided between the terminals and the contact pads . The package can be permanently bonded in place by heating the assembly so as to melt or "reflow" the solder or otherwise activate the bonding material.
[0005] Many packages include solder masses in the form of solder balls, typically about 0.1 mm and about 0.8 mm (5 and 30 mils) in diameter, attached to the terminals of the package. A package having an array of solder balls projecting from its bottom surface is commonly referred to as a ball grid array or "BGA" package. Other packages, referred to as land grid array or "LGA" packages are secured to the substrate by thin layers or lands formed from solder. Packages of this type can be quite compact. Certain packages, commonly referred to as "chip scale packages, " occupy an area of the circuit board equal to, or only slightly larger than, the area of the device incorporated in the package. This is advantageous in that it reduces the overall size of the assembly and permits the use of short interconnections between various devices on the substrate, which in turn limits signal propagation time between devices and thus facilitates operation of the assembly at high speeds .
[0006] An interposer can be provided as an interconnection element having contacts and top and bottom surfaces thereof electrically connected with one or more packaged or unpackaged semiconductor dies at one of the top or bottom surface thereof, and electrically connected with another component at the other one of the top or bottom surfaces. The other component may in some cases be a package substrate or circuit panel. When the other component is a package substrate in some cases the package substrate may in turn be electrically connected with still another component which may be or may include a circuit panel.
SUMMARY OF THE INVENTION
[0007] In accordance with an aspect of the invention, a method is provided for fabricating a component which may be an interposer or other device, e.g., microelectronic element or assembly including an interposer, microelectronic element, or combination thereof . Such method can include forming a structure including a plurality of wire bonds each extending in an axial direction within an opening of one or more openings in an element and each wire bond spaced at least partially apart from a wall of the opening within which it extends, the element consisting essentially of a material having a coefficient of thermal expansion ("CTE") of less than 10 parts per million per degree Celsius ("ppm/°C")- The structure typically has first contacts at a first surface of the component and second contacts at a second surface of the component facing in a direction opposite from the first surface. The first contacts may be first ends of the wire bonds or the first contacts may be coupled to first ends of the wire bonds. The second contacts typically are electrically coupled with the wire bonds. [ 0008 ] By forming a low CTE component using wire bonds as vertical interconnects, a thickness of the low CTE component can be increased beyond that which is typically possible using through-silicon via ("TSV") processes. This is because the wire bond interconnect can be formed prior to being assembled within an opening of the low CTE element, eliminating a requirement of TSV processing wherein holes in a low CTE element are filled with a metal by deposition, e.g., plating. With TSV processing, the cost of plating within small holes exponentially increases with the depth of the holes. As a result, semiconductor elements and active chips which have TSVs typically require thinning to a thickness of 100 microns or less to permit forming the TSVs by filling with a deposited metal. This requirement has led the industry into other difficulties, most notably difficulties with handling of thin wafers.
[ 0009 ] In accordance with embodiments of the invention disclosed herein, the thickness of a low CTE component or interposer taught herein can be much greater than that of a thinned wafer in which TSVs are formed. For example, a low CTE component may be formed from an element or block consisting essentially of low CTE material in which the thickness thereof may be greater than 50 microns, or in one example may be from 0.5 millimeter to two millimeters. In a particular example, the thickness may be about one millimeter. As will be further described herein, thinning of the low CTE component during processing may not be required at all, since wire bonds can be formed which extend in a vertical direction equal to the thickness of the low CTE component .
[ 0010 ] In addition, incorporation of such low CTE component in a microelectronic assembly can help to address possible warpage problems when thinner low CTE interposers or chips are combined with other elements having higher CTEs. This is due at least in part to a greater thickness, e.g., up to one millimeter, of the low CTE component which is possible using the structure and methods disclosed herein.
[ 0011 ] In accordance with one or more aspects of the invention, the openings in the element may be uncovered by any portion of the element and may be uncovered by any other element having a CTE of less than 10 ppm/°C.
[ 0012 ] In accordance with one or more aspects of the invention, the forming the structure includes providing a first element having a plurality of wire bonds extending upwardly away therefrom. The wire bonds may be inserted into one or more openings in the element having the CTE of less than 10 ppm/°C.
[ 0013 ] In accordance with one or more aspects of the invention, the method may further comprise forming at least one of: a first redistribution layer electrically coupled between the wire bonds and the first contacts, or a second redistribution layer electrically coupled between the wire bonds and the second contacts.
[ 0014 ] In accordance with one or more aspects of the invention, forming the structure may further include forming the wire bonds such that first ends of the wire bonds are formed on metallic elements of a first redistribution layer, and then inserting each wire bond into an opening of the one or more openings .
[ 0015 ] In accordance with one or more aspects of the invention, forming the structure may include inserting individual wire bonds of the plurality of wire bonds into respective openings in the element, such that each wire bond may be separated from each other wire bond by material of the element . [ 0016 ] In accordance with one or more aspects of the invention, the openings may be blind openings when the individual wire bonds may be inserted therein, and the method further comprises reducing a thickness of the element after the inserting to provide access to ends of the wire bonds.
[ 0017 ] In accordance with one or more aspects of the invention, the inserting may comprise inserting some of the plurality of the wire bonds into a same opening of the plurality of openings .
[ 0018 ] In accordance with one or more aspects of the invention, an electrically insulative material may be provided within the openings in contact with the wire bonds .
[ 0019 ] In accordance with one or more aspects of the invention, the element may include a plurality of active devices, at least some of the first or the second contacts being electrically coupled with the plurality of active devices .
[ 0020 ] In accordance with one or more aspects of the invention, the element may include a monocrystalline semiconductor region, and at least some of the active devices may be disposed at least partially within the monocrystalline semiconductor region, the openings extending at least partially through the monocrystalline semiconductor region.
[ 0021 ] In accordance with an aspect of the invention, a component is provided which comprises a plurality of wire bonds each extending in an axial direction within an opening of one or more openings in an element having a coefficient of thermal expansion ("CTE") of less than 10 parts per million per degree Celsius ("ppm/°C") . Each wire bond can be spaced at least partially away from a wall of the opening within which it extends. The component can further comprises first contacts at a first surface of the component and second contacts at a second surface of the component facing in a direction opposite from the first surface. The first contacts may be first ends of the wire bonds or the first contacts may be coupled to first ends of the wire bonds. The second contacts may be electrically coupled with the wire bonds .
[ 0022 ] In accordance with one or more aspects of the invention, at least one of: the first contacts or the second contacts may be electrically coupled with the wire bonds through a redistribution layer overlying the wire bonds and overlying a surface of the element defining a plane transverse to the axial direction of the openings . In a particular example, individual wire bonds of the plurality of wire bonds may be disposed within respective openings in the element, such that each wire bond may be separated from each other wire bond by material of the element. In one example, some of the plurality of the wire bonds may be disposed within a same opening of the plurality of openings . In a particular example, an opening may not have a wire bond disposed therein. In one example, an electrically insulative material can be within the openings in contact with the wire bonds. In one example, the electrically insulative material may touch or surround only portions of the wire bonds adjacent the first ends of the wire bonds, or only portions of the wire bonds adjacent the second ends of the wire bonds which are opposite the first ends, or may touch or surround only the first and the second ends of the wire bonds .
[ 0023 ] In accordance with one or more aspects of the invention, the element may include a plurality of active devices, wherein the first and second contacts may be electrically coupled with one another and with at least some of the plurality of active devices. [ 0024 ] In accordance with one or more aspects of the invention, the element may include a monocrystalline semiconductor region, at least some of the active devices being disposed at least partially within the monocrystalline semiconductor region, and the openings extending at least partially through the monocrystalline semiconductor region.
[ 0025 ] In accordance with one or more aspects of the invention, the first contacts and the second contacts may be within an axial distance of less than 50 microns from the wire bonds .
[ 0026 ] In accordance with one or more aspects of the invention, the wire bonds may extend only partially through a thickness of the element, and the component may further comprise electrically conductive connectors extending in an axial direction from the wire bonds at least partially through a remaining portion of the thickness of the element, the connectors formed of deposited electrically conductive material. may be may be may be may be
[ 0027 ] In accordance with one or more aspects of the invention, at least one of: the first contacts or the second contacts may be not electrically coupled with the wire bonds through a redistribution layer overlying the wire bonds and a surface of the element defining a plane transverse to the axial direction of the openings.
[ 0028 ] In accordance with one or more aspects of the invention, the wire bonds may comprise wires having different diameters and the diameter of one wire bond may be larger than the diameter of the other wire bonds in one example, by at least 3%, or in another example, by at least 10%.
[ 0029 ] In accordance with one or more aspects of the invention, the length of at least one wire bond may be shorter than the length of other wire bonds by less than 20% of the length of the other wire bonds .
[ 0030 ] In accordance with one or more aspects of the invention, individual wire bonds of the plurality of wire bonds may be disposed within respective openings in the element, such that at least one or more of the wire bonds may be not separated from each other wire bond by material of the element .
[ 0031 ] In accordance with one or more aspects of the invention, individual wire bonds of the plurality of wire bonds may be disposed within respective openings in the element. In some embodiments, one or more of the openings in the element may not contain a wire bond.
[ 0032 ] In accordance with one or more aspects of the invention, individual wire bonds of the plurality of wire bonds may be disposed within respective openings in the element, and at least one or more openings in the element comprise dielectric material.
BRIEF DESCRIPTION OF THE DRAWINGS
[ 0033 ] Fig. 1A is a sectional view of a component such as an interposer in accordance with an embodiment of the invention, as interconnected within a microelectronic assembly .
[ 0034 ] Fig. IB is a sectional view of an alternative component such as an interposer in accordance with an embodiment of the invention, as interconnected within a microelectronic assembly.
[ 0035 ] Fig. 2A is a sectional view of a component such as an interposer in accordance with a variation of an embodiment seen in Fig. 1A or IB, as interconnected within a microelectronic assembly. [ 0036 ] Fig. 2B is a corresponding plan view of a component such as an interposer within a microelectronic assembly .
[ 0037 ] Fig. 2C is a sectional view of an interposer as interconnected within a microelectronic assembly in accordance with a further variation of an embodiment seen in Figs . 2A and 2B .
[ 0038 ] Fig. 3 is a sectional view of component in accordance with an embodiment of the invention.
[ 0039 ] Fig. 4 is a plan view of an interposer in accordance with an embodiment of the invention.
[ 0040 ] Fig. 5 is a sectional view of an in-process element for incorporation in a component in a fabrication method according to an embodiment of the invention.
[ 0041 ] Fig. 6 is a plan view and Fig. 7 a corresponding sectional view of a low CTE element for incorporation in a component in a fabrication method according to an embodiment of the invention.
[ 0042 ] Figs. 7, 8, 9, 10 and 11 are sectional views illustrating stages in a method of fabricating a component as seen in Fig. 3 in accordance with an embodiment of the invention .
[ 0043 ] Figs. 12, 13, 14, and 15 are sectional views illustrating stages in a method of fabricating a component according to a variation of an embodiment of the invention.
[ 0044 ] Figs. 16, 17 and 18 are sectional views illustrating stages in a method of fabricating a component according to a variation of an embodiment of the invention.
[ 0045 ] Figs. 19 and 20 are sectional views illustrating stages in a method of fabricating a component according to a variation of the embodiment illustrated in Figs. 16, 17 and 18. [ 0046 ] Figs. 21, 22 and 23 are sectional views illustrating stages in a method of fabricating a component according to a variation of the embodiment illustrated in Figs. 16, 17 and 18.
[ 0047 ] Figs. 24, 25, 26, 27 and 28 are sectional views illustrating stages in a method of fabricating a microelectronic element in accordance with an embodiment of the invention.
DETAILED DESCRIPTION
[ 0048 ] Components, e.g., interposers, microelectronic elements, and microelectronic assemblies which include such components are described herein which comprise an element made of material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius ("low CTE material"), typically being a solid monolithic block of semiconductor material such as silicon, a III-V semiconductor compound such as GaAs, InP, etc., or a dielectric material such as a glass, quartz, alumina (e.g., A1203) or other ceramic material, among others. A plurality of wire bond interconnects extend in an axial direction within one or more openings which extend through the thickness of the low CTE element. Components having low CTE can be utilized advantageously in applications where differential thermal expansion ordinarily would be a concern when a low CTE component is assembled in close proximity with another component having relatively high CTE and subjected to high thermal stress.
[ 0049 ] In such components, first contacts at the first surface of the component are interconnected with second contacts at the second surface of the component by wire bonds. Use of wire bonds as vertical interconnects extending through the thickness of the element may in some cases lead to reductions in fabrication costs and tooling costs. Wire bonds can be made to project to substantial distances of tens to hundreds of microns or more above a surface of underlying structure to which they are bonded, and hence can be made to provide vertical interconnects through relatively deep openings in an element. As a result, the use of such wire bond vertical interconnects can help avoid costs associated with thinning and handling of thinned elements such as thinned semiconductor wafers, among others, and use of such wire bond vertical interconnects can help avoid costs associated with forming and filling of high aspect ratio openings with deposited metal to form the vertical interconnects .
[0050] Each wire bond interconnect has no more than one end bonded to an underlying metal surface at a location proximate the first surface, and another end of each wire bond remote from such end unbonded and proximate the second surface .
[0051] By way of context, Fig. 1A illustrates a microelectronic component 10 such as may be constructed in accordance with an embodiment described herein, as further assembled in a microelectronic assembly 100 with other components as well. In the description and figures which follow, the same numerical references are used to indicate the same features and similar numeric references are used to indicate similar features. As seen in Fig. 1A, first and second contacts 46, 16 are provided at first and second opposite surfaces of the component 10, respectively. Contacts 46, 16 may in turn be electrically connected with corresponding contacts of first and second components of the microelectronic assembly which face those contacts 46, 16. Components described herein such as interposers, substrates, circuit panels, microelectronic elements, and the like typically have dielectric structure at external surfaces thereof. Accordingly, as used in this disclosure, a statement that an electrically conductive element is "at" a surface of dielectric structure of a component, indicates that, when the component is not assembled with any other element, the electrically conductive element is available for contact with a theoretical point moving in a direction perpendicular to the surface of the component toward the surface of the component from outside the component. Thus, a terminal, a contact, or other conductive element which is at a surface of a component may project from such surface; may be flush with such surface; or may be recessed relative to such surface in a hole or depression in the component.
[0052] As shown in Fig. 1A, component 10, e.g., an interposer, having a low CTE element 19 may be electrically connected with a first component 12 having active circuit elements thereon, such as a microelectronic element, e.g., a packaged or unpackaged semiconductor die which has a face 13 facing towards the first surface 144 of the component 10 and be packaged or unpackaged as connected to the first contacts 46 of the interposer. As further shown in Fig. 1A, the second contacts 16 of the interposer can be electrically connected with corresponding contacts of another component of the assembly which face the contacts 16, such as contacts of a package substrate 20 in the example illustrated in Fig. 1A. The first and second contacts 46, 16 can be electrically coupled through wire bonds 32 which function as vertical interconnects extending in a direction of a thickness of a low CTE element 19 of the component 10 each wire bond extending within an opening of one or more openings in the low CTE element 19. As used herein, a direction of the thickness of element 19 is defined as an axial direction of the component 10 and a distance in the axial direction is an axial distance. In one example, a thickness of the low CTE element 19 in the axial direction can be greater than 50 microns. In a particular example, the thickness may be between 50 microns and 1 millimeter. In a particular example, the thickness may be within a range from 0.5 millimeter to 2 millimeters .
[ 0053 ] In some cases, the first contacts or the second contacts, or both the first contacts and second contacts can be ends of the wire bonds. In some cases the ends of the wire bonds may be ball bonds which at least partially remain after the fabrication process. In some cases, the ends of some of the wire bonds 32 may be contacts or may be mechanically coupled to such contacts, but such wire bonds may not all be electrically coupled with another component through contacts 46 at the first surface 144 and contacts 16 at the second surface. In a particular embodiment, there may be only one wire bond in component 10.
[ 0054 ] As may be assembled with other components in assembly 100, component 10 may be an interposer for electrically coupling a first component above the interposer, such as, for example, a microelectronic element 12, with a second component such as package substrate 20. As an alternative to the arrangement shown in Fig. 1A or in addition thereto, some or all of the second contacts 16 may be connected with a second unpackaged or packaged semiconductor die having a surface facing the second surface 114 of the component. Package substrate 20 or other component interconnected with the component 10 can, in turn be mounted to contacts 51 of a circuit panel 50, as shown in Fig. 1A. Alternatively, in some cases the package substrate 20 may be omitted from microelectronic assembly 100 and the contacts 16 of the component 10 can be electrically coupled with corresponding contacts 51 of a circuit panel 50. [ 0055 ] In one example, an area and edges of the component
10 can be aligned with those of the microelectronic element 12 such that the surface 114 occupies an area which is a projection of an area of a surface 13 of the microelectronic element thereon. In such example, the component 10 and the microelectronic element 12 joined thereto can form a "chip-scale package" or "CSP" .
[ 0056 ] Fig. IB illustrates a microelectronic assembly 102 according to a further example in which first and second microelectronic elements 12, 52 can be electrically interconnected with a component 11 through first contacts 46 at a first surface 144 of the component 11. The microelectronic elements, which may be packaged or unpackaged semiconductor dies, may be electrically interconnected with one another through conductive structure provided on the component 11, such as traces 54 thereon, which may extend in a direction parallel to a first surface 114 of the component.
[ 0057 ] Figs. 2A-2B illustrate an alternative manner in which microelectronic elements 12A, 12B may be electrically coupled with a component 10 such as an interposer. As seen therein, the microelectronic elements 12A, 12B are coupled via wire bonds 35 with the contacts 46 at an upper surface of the interposer. The contacts 46 may in some cases be ends of the wire bonds 32 which extend in the axial direction of the low CTE element of the component. Alternatively, a redistribution structure can be disposed between ends of the wire bonds 32 and contacts 46, or between ends of the wire bonds 32 and contacts 16, or between both ends of the wire bonds and the contacts 46 and 16. As further seen in Fig. 2B, additional microelectronic elements 12C and 12D may be disposed atop the interposer, some or all of which can be electrically coupled with electrically conductive elements of the interposer. [0058] Fig. 2C illustrates a further variation in which microelectronic elements 112A and 112B have contact-bearing faces which face an upper surface of the component 10. In this case, at least some contacts of the microelectronic elements 112A and 112B face corresponding contacts 46 of the component 10 and are electrically coupled therewith by flip-chip bonds, e.g., without limitation, bonds that may include an electrically conductive material or diffusion bond coupling the contacts of the microelectronic elements 112A and 112B with the corresponding contacts 46 juxtaposed therewith. Fig. 2C further illustrates an additional microelectronic element 112C which may be electrically coupled with the component 10, such as in a face-up configuration with one or more wire bonds 35 coupled to contacts on the upwardly-facing surface 113 of the microelectronic element 112C and one or more contacts 46 of component 10. Fig. 2C further illustrates an assembly further including a substrate 20 electrically coupled with contacts 16 at a lower surface of component 10.
[0059] Referring to Fig. 3, a partial sectional view is shown further illustrating a component 10 such as shown and described above with reference to Fig. 1 or Fig. 2. As seen therein, a plurality of wire bonds 32 extend as vertical interconnects through at least one opening 38 extending through a thickness of a low CTE element 19. Low CTE element typically may comprise a solid monolithic element consisting essentially of low CTE material through which opening 38 extends. In particular examples, the low CTE element may consist essentially of semiconductor material, e.g., silicon, germanium, a III-V semiconductor compound, or a solid block of dielectric material such as glass, quartz, or ceramic material (such as, for example, A1203), among others. Optionally, as will be described further below, a dielectric material 40 may be disposed within opening 38 and may contact edge surfaces 37 of individual ones of the wire bonds 32. In the example seen in Fig. 3, the dielectric material 40 may fill the opening; however, in other embodiments provided herein, some portion or all of the edge surface 37 of a particular wire bond or each wire bond may not be contacted by a dielectric material. An electrically conductive redistribution layer which may be insulated and/or supported by a dielectric layer 118 may electrically couple first ends 33 of wire bonds 32 with contacts 16. A redistribution layer which may be insulated and/or supported by dielectric layer 152 may electrically couple second ends 39 of wire bonds with contacts 46. In one example, the redistribution layer may be formed in accordance with processing typically used to form a redistribution layer on a surface of an existing component such as an interposer or semiconductor chip, wherein "layer" may mean a structure typically formed by "post-fab" processing after forming a wafer including semiconductor chips having active devices thereon in a "fab", the structure including one or more layers of dielectric material and one or more metal layers which can extend parallel to a surface thereof. In a particular example, a plurality of the metal layers may be interconnected with one another by interconnects extending in a vertical direction extending through a thickness of at least one of the metal layers. In another example, the redistribution layer can be a "back end of line" or "BEOL" structure formed by fabrication methods typically utilized in a "fab". In yet another example, the redistribution layer can include a BEOL structure and a post-fab portion formed thereon or electrically coupled therewith. Joining elements 17, e.g., solder balls or other masses of bonding metal or electrically conductive material can be attached or formed on contacts 16. Similar masses or solder balls can be attached or formed on contacts 46.
[ 0060 ] In particular embodiments, the wire bonds 32 can be made of copper, gold or aluminum, and may in certain cases have a finish layer of a different metal exposed at an exterior surface of the wire bonds . The diameter of each wire bond may illustratively be between 1 and 500 micrometers ("microns") in diameter. The minimum pitch of adjacent wires in the in-process element may range from a minimum of around twice the smallest diameter of the wire, to a number which may be an even smaller multiple of the wire diameter when the wire diameter is relatively large. In one example, the first and second contacts 46, 16 may be within an axial distance of less than 50 micrometers ("microns") from the wire bonds 32 to which they are electrically coupled.
[ 0061 ] Fig. 4 is a corresponding plan view looking toward either a top surface 144 or, alternatively, a bottom surface 114 of the component 10. As seen in Figs. 3 and 4, the first and second contacts 46, 16 can be made to extend in a lateral direction parallel to the top or bottom surfaces 144,114 beyond an edge surface 37 of the respective wire bond 32, as seen in the case of contacts 46A and 16A. Fabrication of component 10 can be as further described below. Referring now to Fig. 5, a method of fabricating a component 10 such as an interposer will now be described. As seen in Fig. 5, an in-process element 45 can include an array of unterminated wire bonds 32 are formed extending upwardly from one or more metal surfaces to which the wire bonds are joined. This wire bond array may be formed by forming wire bonds by bonding metal wire to one or more surfaces at different locations thereof, which may be locations of an array, and which may be one or more metal surfaces or a surface of a metal sheet below the wire bonds. In one example, the wire bonds 32 can be formed by bonding wires to one or more surfaces such as surfaces of contacts, or to a surface of a metal sheet 42. In an example such as shown in Fig. 5, the metal sheet 42 need not provide full mechanical support for itself or for the wire bonds 32, as that function may be performed by a supporting carrier 43 which may be releasably attached or clamped to the sheet. In a particular example, a bonding tool can bond the metal wire to an exposed surface of a layered structure which includes an unpatterned or patterned metal sheet, and which may includes one or more finish metal layers thereon. Thus, in one example, wire bonds can be formed on a base having a metal layer of aluminum, copper or alloy thereof or the like, and the finish layers in one example, may include an "ENIG" finish, such as a layer of nickel deposited on the base metal by electroless deposition, followed by a layer of gold deposited on the nickel layer by an immersion process. In another example, the base metal layer can have an "ENEPIG" finish, such as may be a combination of a layer of electrolessly deposited nickel deposited on the base metal, followed by a layer of electrolessly deposited palladium deposited thereon, and followed by a layer of gold deposited on the palladium by an immersion process .
[ 0062 ] Wire bonds can be formed by bonding a metal wire to a surface by a technique as previously described in one or more of the aforementioned commonly owned and incorporated United States Applications. In one example, wire bonds can be formed by ball bonding a metal wire to the surface, such as by heating the wire at a tip thereof to form a ball of molten metal and contacting the surface with the ball to form the ball bond so as to form a bulbous portion of the wire as a first end 33 or base of the wire bond, as shown in Fig. 3 for example. In such example, the base of the wire bond may have a shape similar to a ball or a portion of a ball when the base is formed by ball bonding. A wire bond having a base formed by ball bonding may have a shape and may be formed as described, for example, in United States Patent Application No. 13/462,158, the disclosure of which is incorporated by reference herein. Alternatively, a wire bond may be formed by other techniques such as stitch bonding or wedge bonding in which a portion of the edge surface of a wire is bonded to a surface and may have a shape generally as seen for example, in United States Patent Application Nos . 13/404,408; 13,404,458; 13/405,125, the disclosures of which are incorporated by reference herein. In such arrangements, the base 33 may have a somewhat flattened cylindrical shape which may extend at a substantial angle (e.g., 15 to 90 degrees) away from the shaft. An upwardly extending shaft portion 31 (Fig. 3) of the wire bond need not extend vertically relative to the bonded base 33, but rather can extend at a substantial angle therefrom (e.g., 15 to 90 degrees) . Particular examples of the wire bonds formed this way can be as described in these incorporated applications.
[ 0063 ] Figs. 6 and 7 are a plan view and a cross-sectional view, respectively, of a low CTE element 19 as described above having a plurality of openings 38 therein, with portions 48 of the low CTE element 19 between adjacent openings extending to a greater thickness. The openings can be as yet blind openings in that each opening may not extend entirely through a thickness of the low CTE element as seen in Fig. 7. Openings 38 typically are formed by optical or mechanical ablation such as by laser, mechanical milling, dry and wet etching methods. In the example seen in Figs. 6 and 7, each opening may be sized to accommodate a plurality of adjacent wire bonds which may extend in a row in a first direction 60, and in some cases, may also extend in a column in a second direction 61 transverse to the first direction. Accordingly, each opening 38 may have a size which extends in one or more of the first and second directions 60, 61 for dimensions in each direction of tens of microns to hundreds of microns .
[0064] In the stage of processing seen in Fig. 8, the in-process element 45 of Fig. 5 is united with low CTE element 19 of Figs. 6-7 to form in-process element 47. For example, low CTE element 19 is inverted relative to the orientation shown in Fig. 7 and then united with the in-process element 45. In one embodiment, an adhesive 49 can be provided atop bases of wire bonds 32, the adhesive bonding the portions 48 of the low CTE element 19 between the openings. In a particular example, the low CTE element 19 may be placed in close proximity to or atop the in-process element 45 and then an underfill can be made to flow horizontally into a gap between the in-process element 45 and the low CTE element to form the structure shown in Fig 8. Alternatively, the adhesive 49 can be a punched adhesive film or a patterned dispensed adhesive that bonds the portions 48 of the low CTE element 19 with the top surface of a metal sheet such as the metal sheet 42 of in-process element 45 shown in Fig. 5. As seen in Fig. 8, the adhesive 49 may touch or flow to the wire bonds 32. Alternatively, the adhesive 49 may not touch or flow to the wire bonds 32.
[0065] Thereafter, as seen in Fig. 9, the low CTE element can be thinned from the top, such as, for example, by abrasive, milling chemical, polishing or ion process, or combination thereof, until the openings are exposed at the top. In one example, grinding, lapping or polishing can be used to thin the low CTE element. In another example, etching such as a reactive ion etching or plasma etching process can be used. In one example, grinding, lapping or polishing can be used for coarse thinning of the low CTE element, which can be followed by selective reactive ion etching of the dielectric fill 40 to cause ends 39 of the wire bonds 32 to project above surfaces of the portions 48 of the low CTE element between the openings 38.
[ 0066 ] The openings can then be filled with a suitable dielectric material 40. The dielectric material can be selected so as not to interfere with operation of the component 10 which in some cases may need to be used in an environment which undergoes rapid or extreme temperature fluctuations. Therefore, it may be beneficial in some cases to provide a low CTE dielectric material 40 within the openings which may have a relatively low CTE (e.g., having a CTE of less than 12 ppm/°C, or which may be the same or close to that of low CTE element. Low CTE materials tend to be quite stiff in that their Young's modulus (a measure of elasticity) tends to be much higher than polymeric materials; therefore, finding a filler material which has a CTE relatively close to that of the low CTE element may be needed when this approach is used. Accordingly, for this purpose, molten glass is one possible low CTE filler material which can be used as the filler dielectric material 40. Alternatively, openings can be filled with a material having a relatively high CTE, but which can be a compliant material such as a polymeric material, such material having a low Young's modulus. In some embodiments the dielectric fill 40 may comprise a porous polymer, for example, porous polyimide . In some embodiments, the dielectric material 40 may comprise may comprise more than one type of dielectric material. For example, the majority of the dielectric may be a layer of porous polyimide or other dielectric material and such layer can be capped with an oxide, which in one example may be an oxide deposited from a tetraethyl orthosilicate (TEOS) precursor. The TEOS layer may comprise the RDL over ends 39 of the wire bonds surface 39.
[ 0067 ] Next, as further seen in Fig. 10, the portion of the filler dielectric material extending above the portions 48 of the low CTE element is removed and ends 39 of the wire bonds can be exposed by a reveal process. A redistribution layer or back end of line ("BEOL") interconnect layer can be formed atop the ends 39 of the wire bonds 32, wherein contacts 46 and optionally traces of the redistribution layer can be provided. The carrier 43 can then be removed and metal sheet 42, if present, can be removed, resulting in the component 10 such as seen in Fig 11, for example, or as shown and described above with reference to Fig. 3. In some embodiments, the metal sheet may be patterned to fabricate a redistribution layer or to form electrical contacts such as first contacts 46 or second contacts 16.
[ 0068 ] Fig. 12 illustrates a stage of fabrication in accordance with a variation of the embodiment described above relative to Figs. 5-11. In this case, an in-process element 55 may comprise wire bonds 32 formed atop a redistribution layer or BEOL having traces 54 and contacts 46 pre-formed therein, the redistribution layer disposed atop carrier 43. In some embodiments the carrier 43 may comprise a chip, a package or unpackaged device. In some embodiments, the wire bonds 32 may comprise wires of different diameters. In such example, the diameters of one or more wires may be bigger than the diameters of other wires by at least 3%. Also, the diameters of one or more wires may be bigger than the diameters of other wires by at least 10%.
[ 0069 ] Fig. 12 illustrates a stage of fabrication in accordance with a variation of the embodiment described above relative to Figs. 5-11. In this case, an in-process element 55 may comprise wire bonds 32 formed atop a redistribution layer having traces 54 and contacts 46 pre-formed therein, the redistribution layer disposed atop carrier 43. Figs. 13-14 illustrate stages of fabrication in which the in-process element 55 is united with low CTE element 19, and a dielectric material is added thereto, in like manner to that described above relative to Figs. 8 and 9. Fig. 15 illustrates a further stage of processing in which contacts 16 or 16B can be formed in electrical communication with the wire bonds 32. For example, contacts 16 can be formed atop the dielectric fill 40 and contacts 16B can be formed in depressions extending from a surface 53 of the dielectric fill to the wire bonds 32. In one example, the dielectric fill 40 may extend to a height above a height of the surface 121 of the low CTE element 19, for example, when contacts are formed in a manner as shown in 16B. Alternatively, the top surface of the dielectric fill 40 can be aligned with the surface 121 of low CTE element 19. In some embodiments one or more wire bonds 32 are shorter than the other. For example one or more wire bonds are shorter than other wire bonds by less than 20% of the length of the other wire bonds. In some applications one or more wire bonds are shorter than other wire bonds by more than 10% of the length of the other wire bonds .
[0070] Figs. 16-18 illustrate a variation of the above embodiment described relative to Figs. 3-11, in which each opening 138 in a low CTE element 119 is sized to accommodate a single wire bond. For example, a cylindrical shaft of each wire bond 32 of in-process element 155 can extend vertically within a single opening 138 in the low CTE element. When the low CTE element is made of semiconductor material, each opening 138 can be lined with a dielectric material (not shown) before uniting the in-process element therewith. For example, such dielectric liner can be deposited or formed thereon by a number of possible processes which may include chemical vapor deposition, local oxidation or nitridation, among others. Figs. 17 and 18 illustrate stages in a process of fabrication which are analogous to those shown in Figs. 13 and 14, wherein a dielectric fill can be formed in the openings 138 after the low CTE element has been united with the in-process element 155. Fig. 18 further illustrates an exemplary component 110, e.g., interposer, formed in this manner. In some embodiments (not shown), one or more of openings 138 may not contain a wire bond. In such embodiment, an opening 138 which lacks a wire bond therein may contain dielectric material. Such opening 138 may be partially or completely filled with a dielectric material.
[ 0071 ] In a variation of the above-described processing, an uncured dielectric material 140, e.g., a liquid material may be present in openings 138 prior to the wire bonds 32 being inserted therein. In such manner, the deposition or filling of a dielectric material after thinning the low CTE element 119 may be avoided or may be further facilitated or aided thereby.
[ 0072 ] In another variation, the openings may not be filled with a dielectric material, but instead the axial dimension of each opening can be allowed to remain either partially or substantially completely unfilled by a dielectric material. For example, only the top and bottom ends of each opening may be plugged. In such case, air or a void remaining within each opening in the final component can serve as a dielectric having an even lower permittivity than a solid polymeric or inorganic dielectric material that may otherwise be used.
[ 0073 ] Figs. 19 and 20 illustrate a further variation in which a redistribution layer comprising traces 54 and contacts 46 can be formed atop the wire bonds 32 after the low CTE element 119 and a corresponding in-process element 157 are united. A completed component 210 such as an interposer is illustrated in Fig. 20.
[0074] Figs. 21-23 illustrate another variation of the above-described process. As seen in Fig. 21, an in-process element 159 having wire bonds 32 extending therefrom is juxtaposed with low CTE element 119 such that a gap exists between the two which can accommodate flow of a dielectric material in fluid form for the purpose of filling each opening 138. Thereafter, as seen in Fig. 22, a dielectric material 140 can be flowed into each opening. As further seen in Fig. 23, the low CTE element then can be thinned and contacts and conductive masses, e.g., solder masses added thereto to form a component 310 such as an interposer. Examples of the dielectric fill material can be inorganic or polymeric material as described above. In some cases, the flow may be in gaseous form, such as for deposition of a dielectric coating within openings such as parylene, among others. Processing in accordance with the variation seen in Figs. 21-23 to form the dielectric fill layer can be performed in any or all of the above-described embodiments.
[0075] A further variation of the above-described process is illustrated in Figs. 24-28 in which the resulting component 410 (Fig. 28) is a microelectronic element, which may comprise a semiconductor chip through which wire bonds 132 extend in a direction of a thickness thereof for purposes of providing electrical interconnects between contacts 46 provided at a first surface 144 of the component 410 and contacts 16 provided at a second surface 114 of the component opposite from the first surface. As seen in Fig. 28, the microelectronic element may include a semiconductor region 419 through which wire bonds 132 extend, the semiconductor region typically formed of monocrystalline semiconductor material, but which may have a different crystalline structure in an appropriate case . A plurality of active devices 421 are disposed at least partially in the semiconductor region 419, which may be transistors, diodes, or any of a variety of active devices which may comprise and utilize semiconductor regions as part of their functional structure. As further seen in Fig. 28, a horizontal and vertical interconnect structure 148 which may include multiple interconnect layers such as a back end of the line ("BEOL") wiring structure or a redistribution structure, the interconnect structure being formed atop the semiconductor region 419. Electrically conductive, e.g., metallic connectors 149 can electrically couple the wire bonds 132 and the interconnect structure 148 of the component 410, and may be disposed between the wire bonds and interconnect structure. As in the above-described embodiments and variations thereof, a dielectric fill material 440 can be disposed within the openings 438 surrounding each wire bond. Alternatively, the dielectric fill material can be omitted, or the dielectric material may only plug the top or bottom ends or both ends of the openings 438. In some cases, the openings 438 may only be lined with a dielectric material as described above but not filled.
[0076] A process of fabricating a component such as seen in Fig. 28 can comprise uniting an in-process element 465 (Fig. 24) with a microelectronic element 470 (Fig. 25) having a plurality of active devices already formed therein. The process may be considered a "via middle" process because vertical interconnects formed by the wire bonds 132 are formed after high temperature fabrication of the active devices in the semiconductor region is completed, but before the interconnect structure 148 (Fig. 28) has been formed. As seen in Fig. 25, a set of openings 438 have been formed extending from a back surface 471 of the microelectronic element 470 towards a front surface 472 thereof at which active devices 421 can be disposed, the openings each sized to accommodate either a single wire bond or a plurality of wire bonds and the spacing between adjacent wire bonds. The openings can be formed by any number of techniques which may involve mechanical, chemical or optical (e.g., laser ablation), techniques, among others. Thus, the openings 438 extend partially through a thickness of the semiconductor region 419. A carrier 443 may be attached to a front surface 472 of the semiconductor region while the openings are being formed .
[ 0077 ] Fig. 26 illustrates a subsequent stage of fabrication in which the in-process element 465 is united with the microelectronic element 470 and an optional dielectric fill material 440 may be provided within the openings. The carrier may also be removed.
[ 0078 ] As further shown in Fig. 27, front surface openings 458 can then be formed extending from the front surface of the microelectronic element in alignment with the wire bonds 132. A dielectric liner can then be formed within the front surface openings, after which an electrically conductive material can then be deposited into the openings to form metallic connectors 149 as seen in Fig. 28. In some examples, metallic connectors may be formed by various vapor deposition or plating processes, or combination thereof.
[ 0079 ] In each of the embodiments seen above, component may include wire bonds of substantial length in which the cylindrical shaft portion thereof may extend for tens to hundreds of microns. In particular example, the shaft of each wire bond may have a length from 50 microns to one millimeter . [ 0080 ] In certain examples, microelectronic elements 410 fabricated in accordance with an embodiment of the invention can be stacked atop one another in a die stack, wherein the wire bonds 132 and connectors 149 and the interconnect structure 148 can function as through silicon vias ("TSVs"). In one example, a surface 114 of a microelectronic element 410 fabricated in this way may occupy the same area as the surface of the original semiconductor chip and have peripheral edges bounding that area which correspond to the edges of the original semiconductor chip from which it is made. In such example, the component 410 or processed microelectronic element can be referred to as a "chip-scale package" or "CSP" .
[ 0081 ] In a variation of any or all of the embodiments described above relative to Figs. 3 through 28, instead of forming the wire bonds 32 on a metal sheet 42, the wire bonds could be formed atop a circuit panel or a microelectronic element such as a semiconductor chip. In a particular embodiment, instead of removing the underlying structure supporting the wire bonds, e.g., metal sheet 42, circuit panel or semiconductor chip, the circuit panel or semiconductor chip can be allowed to remain in a microelectronic assembly which includes the interposer element and the underlying circuit panel or semiconductor chip .
[ 0082 ] In a variation of any or all of the embodiments described above relative to Figs. 3 through 28, one or more additional components which may be active components, passive components, or combination thereof, can be pre-mounted on the underlying structure, e.g., a metal sheet, microelectronic element, or circuit panel, and such additional component (s) can then become embedded within the dielectric fill inside the opening in the completed component or interposer. In a variation of the embodiment described above, the openings in the low CTE element may extend through the entire thickness of the low CTE element before the wire bonds are inserted therein, such that there is no material of the low CTE element overlying the wire bonds in an axial direction of the wire bonds. In such case, thinning of the low CTE element described above to expose the openings 38 from the top of the low CTE element (such as thinning of the element 19 shown in Fig. 9) can be omitted.
[ 0083 ] It is to be understood that features shown and discussed with respect to one aspect, embodiment, arrangement or configuration of the invention may be used in conjunction with any other aspect, embodiment, arrangement or configuration of the invention. For example, although certain figures and their corresponding descriptions illustrate vertically extending wire bonds, it is to be understood that the wire bonds such as shown in other figures which extend in other than vertical directions may also be used in accordance with any embodiment shown or described.
[ 0084 ] Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements and combinations of the embodiments provided herein are contemplated by the present application. Further enhancements may be devised without departing from the spirit and scope of the present invention as defined in the embodiments described herein.

Claims

1. A method of fabricating a component, comprising:
forming a structure including a plurality of wire bonds each extending in an axial direction within an opening of one or more openings in an element and each wire bond spaced at least partially apart from a wall of the opening within which it extends, the element consisting essentially of a material having a coefficient of thermal expansion ("CTE") of less than 10 parts per million per degree Celsius ("ppm/°C"); the structure having first contacts at a first surface of the component and second contacts at a second surface of the component facing in a direction opposite from the first surface, the first contacts being first ends of the wire bonds or the first contacts being coupled to first ends of the wire bonds, and the second contacts electrically coupled with the wire bonds .
2. The method of claim 1, wherein the openings in the element are uncovered by any portion of the element .
3. The method of claim 1, wherein the forming the structure includes providing a first element having a plurality of wire bonds extending upwardly away therefrom; and
inserting the wire bonds into one or more openings in the element having the CTE of less than 10 ppm/°C.
4. The method of claim 1, further may comprise comprising forming at least one of: a first redistribution layer electrically coupled between the wire bonds and the first contacts, or a second redistribution layer electrically coupled between the wire bonds and the second contacts.
5. The method of claim 1, wherein forming the structure includes forming the wire bonds such that first ends of the wire bonds are formed on metallic elements of a first redistribution layer, and then inserting each wire bond into an opening of the one or more openings .
6. The method of claim 1, wherein forming the structure includes may comprise inserting individual wire bonds of the plurality of wire bonds into respective openings in the element, such that each wire bond is separated from each other wire bond by material of the element .
7. The method of claim 6, wherein the openings are blind openings when the individual wire bonds are inserted therein, and the method further may comprise reducing a thickness of the element after the inserting to provide access to ends of the wire bonds.
8. The method of claim 6, wherein the inserting may comprise inserting some of the plurality of the wire bonds into a same opening of the plurality of openings .
9. The method of claim 1, further comprising providing an electrically insulative material within the openings in contact with the wire bonds .
10. The method of claim 1, wherein the element includes a plurality of active devices, wherein at least some of the first or the second contacts electrically coupled with the plurality of active devices .
11. The method of claim 10, wherein the element includes a monocrystalline semiconductor region, at least some of the active devices being disposed at least partially within the monocrystalline semiconductor region, and the openings extending at least partially through the monocrystalline semiconductor region.
12. A component, comprising:
a plurality of wire bonds each extending in an axial direction within an opening of one or more openings in an element having a coefficient of thermal expansion ("CTE") of less than 10 parts per million per degree Celsius ("ppm/°C") and each wire bond spaced at least partially away from a wall of the opening within which it extends; first contacts at a first surface of the component and second contacts at a second surface of the component facing in a direction opposite from the first surface, the first contacts being first ends of the wire bonds or the first contacts being coupled to first ends of the wire bonds, and the second contacts electrically coupled with the wire bonds.
13. The component of claim 12, wherein at least one of the first contacts or the second contacts are electrically coupled with the wire bonds through a redistribution layer overlying the wire bonds and overlying a surface of the element defining a plane transverse to the axial direction of the openings .
14. The component of claim 12, wherein individual wire bonds of the plurality of wire bonds are disposed within respective openings in the element, such that each wire bond is separated from each other wire bond by material of the element .
15. The component of claim 12, wherein some of the plurality of the wire bonds are disposed within a same opening of the plurality of openings .
16. The component of claim 12, further comprising an electrically insulative material within the openings in contact with the wire bonds .
17. The component of claim 12, wherein the element includes a plurality of active devices, wherein the first and second contacts are electrically coupled with one another and with at least some of the plurality of active devices.
18. The component of claim 17, wherein the element includes a monocrystalline semiconductor region, at least some of the active devices being disposed at least partially within the monocrystalline semiconductor region, and the openings extending at least partially through the monocrystalline semiconductor region.
19. The component of claim 12, wherein the first contacts and the second contacts are within an axial distance of less than 50 microns from the wire bonds.
20. The component of claim 17, in which wire bonds extend only partially through a thickness of the element, further comprising electrically conductive connectors extending in an axial direction from the wire bonds at least partially through a remaining portion of the thickness of the element, the connectors formed of deposited electrically conductive material.
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US10615111B2 (en) * 2014-10-31 2020-04-07 The Board Of Trustees Of The Leland Stanford Junior University Interposer for multi-chip electronics packaging
US9443799B2 (en) 2014-12-16 2016-09-13 International Business Machines Corporation Interposer with lattice construction and embedded conductive metal structures
US9666514B2 (en) * 2015-04-14 2017-05-30 Invensas Corporation High performance compliant substrate
US9818645B2 (en) * 2016-01-08 2017-11-14 National Institute Of Advanced Industrial Science And Technology Through electrode, manufacturing method thereof, and semiconductor device and manufacturing method thereof
US20180090471A1 (en) * 2016-09-28 2018-03-29 Intel Corporation Package on Package Structure Having Package To Package Interconnect Composed of Packed Wires Having A Polygon Cross Section
KR102595102B1 (en) * 2016-11-01 2023-10-31 삼성디스플레이 주식회사 Display device
US9947634B1 (en) * 2017-06-13 2018-04-17 Northrop Grumman Systems Corporation Robust mezzanine BGA connector
GB2581149B (en) * 2019-02-05 2021-11-10 Pragmatic Printing Ltd Flexible interposer
TWI791881B (en) * 2019-08-16 2023-02-11 矽品精密工業股份有限公司 Electronic package, assemble substrate and fabrication method thereof

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5195237A (en) * 1987-05-21 1993-03-23 Cray Computer Corporation Flying leads for integrated circuits
US6459039B1 (en) * 2000-06-19 2002-10-01 International Business Machines Corporation Method and apparatus to manufacture an electronic package with direct wiring pattern
US20050194180A1 (en) * 2004-03-02 2005-09-08 Kirby Kyle K. Compliant contact pin assembly, card system and methods thereof
US20060012026A1 (en) * 2004-07-14 2006-01-19 Suk-Chae Kang Semiconductor package and method for its manufacture
US20070035033A1 (en) * 2005-05-26 2007-02-15 Volkan Ozguz Stackable tier structure comprising high density feedthrough
US20070246819A1 (en) * 2006-04-24 2007-10-25 Micron Technology, Inc. Semiconductor components and systems having encapsulated through wire interconnects (TWI) and wafer level methods of fabrication
FR2957191A1 (en) * 2010-03-04 2011-09-09 Tronic S Microsystems Electrical interconnection support structure i.e. interposer, fabricating method for e.g. micro electromechanical system integrated circuits, involves depositing electric contact point on upper face at level of wire, and removing backplate
WO2012067177A1 (en) * 2010-11-17 2012-05-24 株式会社フジクラ Wiring board and method for producing same
US20140036454A1 (en) * 2012-08-03 2014-02-06 Invensas Corporation Bva interposer
US20140070423A1 (en) * 2012-09-13 2014-03-13 Invensas Corporation Tunable composite interposer

Family Cites Families (466)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1439262B2 (en) 1963-07-23 1972-03-30 Siemens AG, 1000 Berlin u. 8000 München METHOD OF CONTACTING SEMICONDUCTOR COMPONENTS BY THERMOCOMPRESSION
US3358897A (en) 1964-03-31 1967-12-19 Tempress Res Co Electric lead wire bonding tools
US3623649A (en) 1969-06-09 1971-11-30 Gen Motors Corp Wedge bonding tool for the attachment of semiconductor leads
DE2119567C2 (en) 1970-05-05 1983-07-14 International Computers Ltd., London Electrical connection device and method for making the same
DE2228703A1 (en) 1972-06-13 1974-01-10 Licentia Gmbh PROCESS FOR MANUFACTURING A SPECIFIED SOLDER THICKNESS IN THE MANUFACTURING OF SEMI-CONDUCTOR COMPONENTS
US4327860A (en) 1980-01-03 1982-05-04 Kulicke And Soffa Ind. Inc. Method of making slack free wire interconnections
US4422568A (en) 1981-01-12 1983-12-27 Kulicke And Soffa Industries, Inc. Method of making constant bonding wire tail lengths
US4437604A (en) 1982-03-15 1984-03-20 Kulicke & Soffa Industries, Inc. Method of making fine wire interconnections
JPS59189069A (en) 1983-04-12 1984-10-26 Alps Electric Co Ltd Device and method for coating solder on terminal
JPS61125062A (en) 1984-11-22 1986-06-12 Hitachi Ltd Method and device for attaching pin
US4604644A (en) 1985-01-28 1986-08-05 International Business Machines Corporation Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making
US5917707A (en) 1993-11-16 1999-06-29 Formfactor, Inc. Flexible contact structure with an electrically conductive shell
US5476211A (en) 1993-11-16 1995-12-19 Form Factor, Inc. Method of manufacturing electrical contacts, using a sacrificial member
US4924353A (en) 1985-12-20 1990-05-08 Hughes Aircraft Company Connector system for coupling to an integrated circuit chip
US4716049A (en) 1985-12-20 1987-12-29 Hughes Aircraft Company Compressive pedestal for microminiature connections
US4793814A (en) 1986-07-21 1988-12-27 Rogers Corporation Electrical circuit board interconnect
US4695870A (en) 1986-03-27 1987-09-22 Hughes Aircraft Company Inverted chip carrier
JPS62226307A (en) 1986-03-28 1987-10-05 Toshiba Corp Robot device
US4771930A (en) 1986-06-30 1988-09-20 Kulicke And Soffa Industries Inc. Apparatus for supplying uniform tail lengths
JPS6397941A (en) 1986-10-14 1988-04-28 Fuji Photo Film Co Ltd Photosensitive material
US5138438A (en) 1987-06-24 1992-08-11 Akita Electronics Co. Ltd. Lead connections means for stacked tab packaged IC chips
KR970003915B1 (en) 1987-06-24 1997-03-22 미다 가쓰시게 Semiconductor device and the use memory module
JP2642359B2 (en) 1987-09-11 1997-08-20 株式会社日立製作所 Semiconductor device
JPS6412769A (en) 1987-07-07 1989-01-17 Sony Corp Correction circuit for image distortion
US4804132A (en) 1987-08-28 1989-02-14 Difrancesco Louis Method for cold bonding
JPH01118364A (en) 1987-10-30 1989-05-10 Fujitsu Ltd Presolder dipping method
US4998885A (en) 1989-10-27 1991-03-12 International Business Machines Corporation Elastomeric area array interposer
US5077598A (en) 1989-11-08 1991-12-31 Hewlett-Packard Company Strain relief flip-chip integrated circuit assembly with test fixturing
US5095187A (en) 1989-12-20 1992-03-10 Raychem Corporation Weakening wire supplied through a wire bonder
AU645283B2 (en) 1990-01-23 1994-01-13 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device
CA2034700A1 (en) 1990-01-23 1991-07-24 Masanori Nishiguchi Substrate for packaging a semiconductor device
US5083697A (en) 1990-02-14 1992-01-28 Difrancesco Louis Particle-enhanced joining of metal surfaces
US4975079A (en) 1990-02-23 1990-12-04 International Business Machines Corp. Connector assembly for chip testing
US4999472A (en) 1990-03-12 1991-03-12 Neinast James E Electric arc system for ablating a surface coating
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5067382A (en) 1990-11-02 1991-11-26 Cray Computer Corporation Method and apparatus for notching a lead wire attached to an IC chip to facilitate severing the wire
KR940001149B1 (en) 1991-04-16 1994-02-14 삼성전자 주식회사 Chip bonding method of semiconductor device
US5607818A (en) 1991-06-04 1997-03-04 Micron Technology, Inc. Method for making interconnects and semiconductor structures using electrophoretic photoresist deposition
JPH06510122A (en) 1991-08-23 1994-11-10 エヌチップ　インコーポレイテッド Burn-in techniques for unpackaged integrated circuits
US5220489A (en) 1991-10-11 1993-06-15 Motorola, Inc. Multicomponent integrated circuit package
JP2931936B2 (en) 1992-01-17 1999-08-09 株式会社日立製作所 Method for manufacturing lead frame for semiconductor device, lead frame for semiconductor device, and resin-sealed semiconductor device
US5831836A (en) 1992-01-30 1998-11-03 Lsi Logic Power plane for semiconductor device
US5222014A (en) 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
US5438224A (en) 1992-04-23 1995-08-01 Motorola, Inc. Integrated circuit package having a face-to-face IC chip arrangement
US5494667A (en) 1992-06-04 1996-02-27 Kabushiki Kaisha Hayahibara Topically applied hair restorer containing pine extract
US5977618A (en) 1992-07-24 1999-11-02 Tessera, Inc. Semiconductor connection components and methods with releasable lead support
US6054756A (en) 1992-07-24 2000-04-25 Tessera, Inc. Connection components with frangible leads and bus
JP3151219B2 (en) 1992-07-24 2001-04-03 テツセラ，インコーポレイテッド Semiconductor connection structure with detachable lead support and method of manufacturing the same
US6295729B1 (en) 1992-10-19 2001-10-02 International Business Machines Corporation Angled flying lead wire bonding process
US5371654A (en) 1992-10-19 1994-12-06 International Business Machines Corporation Three dimensional high performance interconnection package
US20050062492A1 (en) 2001-08-03 2005-03-24 Beaman Brian Samuel High density integrated circuit apparatus, test probe and methods of use thereof
JP2716336B2 (en) 1993-03-10 1998-02-18 日本電気株式会社 Integrated circuit device
JPH06268101A (en) 1993-03-17 1994-09-22 Hitachi Ltd Semiconductor device and its manufacture, electronic device, lead frame, and mounting substrate
US5340771A (en) 1993-03-18 1994-08-23 Lsi Logic Corporation Techniques for providing high I/O count connections to semiconductor dies
US5454161A (en) 1993-04-29 1995-10-03 Fujitsu Limited Through hole interconnect substrate fabrication process
US5811982A (en) 1995-11-27 1998-09-22 International Business Machines Corporation High density cantilevered probe for electronic devices
US20030048108A1 (en) 1993-04-30 2003-03-13 Beaman Brian Samuel Structural design and processes to control probe position accuracy in a wafer test probe assembly
JP2981385B2 (en) 1993-09-06 1999-11-22 シャープ株式会社 Structure of chip component type LED and method of manufacturing the same
US5346118A (en) 1993-09-28 1994-09-13 At&T Bell Laboratories Surface mount solder assembly of leadless integrated circuit packages to substrates
US6835898B2 (en) 1993-11-16 2004-12-28 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
US5455390A (en) 1994-02-01 1995-10-03 Tessera, Inc. Microelectronics unit mounting with multiple lead bonding
CN1117395C (en) 1994-03-18 2003-08-06 日立化成工业株式会社 Semiconductor package manufacturing method and semiconductor package
US5802699A (en) 1994-06-07 1998-09-08 Tessera, Inc. Methods of assembling microelectronic assembly with socket for engaging bump leads
US5615824A (en) 1994-06-07 1997-04-01 Tessera, Inc. Soldering with resilient contacts
JPH07335783A (en) 1994-06-13 1995-12-22 Fujitsu Ltd Semiconductor device and semiconductor device unit
US5468995A (en) 1994-07-05 1995-11-21 Motorola, Inc. Semiconductor device having compliant columnar electrical connections
US5518964A (en) 1994-07-07 1996-05-21 Tessera, Inc. Microelectronic mounting with multiple lead deformation and bonding
US5688716A (en) 1994-07-07 1997-11-18 Tessera, Inc. Fan-out semiconductor chip assembly
US5989936A (en) 1994-07-07 1999-11-23 Tessera, Inc. Microelectronic assembly fabrication with terminal formation from a conductive layer
US6177636B1 (en) 1994-12-29 2001-01-23 Tessera, Inc. Connection components with posts
US6117694A (en) 1994-07-07 2000-09-12 Tessera, Inc. Flexible lead structures and methods of making same
US6828668B2 (en) 1994-07-07 2004-12-07 Tessera, Inc. Flexible lead structures and methods of making same
US5656550A (en) 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
JPH08115989A (en) 1994-08-24 1996-05-07 Fujitsu Ltd Semiconductor device and its manufacture
US5659952A (en) 1994-09-20 1997-08-26 Tessera, Inc. Method of fabricating compliant interface for semiconductor chip
US5541567A (en) 1994-10-17 1996-07-30 International Business Machines Corporation Coaxial vias in an electronic substrate
US5495667A (en) 1994-11-07 1996-03-05 Micron Technology, Inc. Method for forming contact pins for semiconductor dice and interconnects
US5736074A (en) 1995-06-30 1998-04-07 Micro Fab Technologies, Inc. Manufacture of coated spheres
US5629241A (en) 1995-07-07 1997-05-13 Hughes Aircraft Company Microwave/millimeter wave circuit structure with discrete flip-chip mounted elements, and method of fabricating the same
US5971253A (en) 1995-07-31 1999-10-26 Tessera, Inc. Microelectronic component mounting with deformable shell terminals
US5872051A (en) 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
US5810609A (en) 1995-08-28 1998-09-22 Tessera, Inc. Socket for engaging bump leads on a microelectronic device and methods therefor
US6211572B1 (en) 1995-10-31 2001-04-03 Tessera, Inc. Semiconductor chip package with fan-in leads
JPH09134934A (en) 1995-11-07 1997-05-20 Sumitomo Metal Ind Ltd Semiconductor package and semiconductor device
JP3332308B2 (en) 1995-11-07 2002-10-07 新光電気工業株式会社 Semiconductor device and manufacturing method thereof
US5731709A (en) 1996-01-26 1998-03-24 Motorola, Inc. Method for testing a ball grid array semiconductor device and a device for such testing
US5994152A (en) 1996-02-21 1999-11-30 Formfactor, Inc. Fabricating interconnects and tips using sacrificial substrates
US6000126A (en) 1996-03-29 1999-12-14 General Dynamics Information Systems, Inc. Method and apparatus for connecting area grid arrays to printed wire board
US6821821B2 (en) 1996-04-18 2004-11-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
DE19618227A1 (en) 1996-05-07 1997-11-13 Herbert Streckfus Gmbh Method and device for soldering electronic components on a printed circuit board
JPH1012769A (en) 1996-06-24 1998-01-16 Ricoh Co Ltd Semiconductor device and its manufacture
WO1998018164A1 (en) 1996-10-17 1998-04-30 Seiko Epson Corporation Semiconductor device, method for manufacturing the same, circuit board, and flexible substrate
US5976913A (en) 1996-12-12 1999-11-02 Tessera, Inc. Microelectronic mounting with multiple lead deformation using restraining straps
US6054337A (en) 1996-12-13 2000-04-25 Tessera, Inc. Method of making a compliant multichip package
US6225688B1 (en) 1997-12-11 2001-05-01 Tessera, Inc. Stacked microelectronic assembly and method therefor
US6121676A (en) 1996-12-13 2000-09-19 Tessera, Inc. Stacked microelectronic assembly and method therefor
US6083837A (en) 1996-12-13 2000-07-04 Tessera, Inc. Fabrication of components by coining
US6133072A (en) 1996-12-13 2000-10-17 Tessera, Inc. Microelectronic connector with planar elastomer sockets
JP3400279B2 (en) 1997-01-13 2003-04-28 株式会社新川 Bump forming method
US5898991A (en) 1997-01-16 1999-05-04 International Business Machines Corporation Methods of fabrication of coaxial vias and magnetic devices
US5839191A (en) 1997-01-24 1998-11-24 Unisys Corporation Vibrating template method of placing solder balls on the I/O pads of an integrated circuit package
JPH1118364A (en) 1997-06-27 1999-01-22 Matsushita Electric Ind Co Ltd Capstan motor
US5895967A (en) 1997-07-07 1999-04-20 Texas Instruments Incorporated Ball grid array package having a deformable metal layer and method
US5896271A (en) 1997-07-21 1999-04-20 Packard Hughes Interconnect Company Integrated circuit with a chip on dot and a heat sink
KR100543836B1 (en) 1997-08-19 2006-01-23 가부시키가이샤 히타치세이사쿠쇼 Multichip module structure and method for manufacturing the same
CA2213590C (en) 1997-08-21 2006-11-07 Keith C. Carroll Flexible circuit connector and method of making same
JP3859318B2 (en) 1997-08-29 2006-12-20 シチズン電子株式会社 Electronic circuit packaging method
JP3937265B2 (en) 1997-09-29 2007-06-27 エルピーダメモリ株式会社 Semiconductor device
JP2978861B2 (en) 1997-10-28 1999-11-15 九州日本電気株式会社 Molded BGA type semiconductor device and manufacturing method thereof
US6038136A (en) 1997-10-29 2000-03-14 Hestia Technologies, Inc. Chip package with molded underfill
JPH11219984A (en) 1997-11-06 1999-08-10 Sharp Corp Semiconductor device package, its manufacture and circuit board therefor
US6222136B1 (en) 1997-11-12 2001-04-24 International Business Machines Corporation Printed circuit board with continuous connective bumps
US6002168A (en) 1997-11-25 1999-12-14 Tessera, Inc. Microelectronic component with rigid interposer
US6038133A (en) 1997-11-25 2000-03-14 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method for producing the same
JPH11163022A (en) 1997-11-28 1999-06-18 Sony Corp Semiconductor and manufacture of the same and electronic equipment
JP3988227B2 (en) 1997-12-01 2007-10-10 日立化成工業株式会社 Manufacturing method of semiconductor chip mounting substrate and semiconductor device
US6124546A (en) 1997-12-03 2000-09-26 Advanced Micro Devices, Inc. Integrated circuit chip package and method of making the same
US6260264B1 (en) 1997-12-08 2001-07-17 3M Innovative Properties Company Methods for making z-axis electrical connections
US6052287A (en) 1997-12-09 2000-04-18 Sandia Corporation Silicon ball grid array chip carrier
US5973391A (en) 1997-12-11 1999-10-26 Read-Rite Corporation Interposer with embedded circuitry and method for using the same to package microelectronic units
JPH11220082A (en) 1998-02-03 1999-08-10 Oki Electric Ind Co Ltd Semiconductor device
JP3971500B2 (en) 1998-02-20 2007-09-05 ソニー株式会社 Manufacturing method of wiring board for mounting semiconductor element
JP3536650B2 (en) 1998-02-27 2004-06-14 富士ゼロックス株式会社 Bump forming method and apparatus
KR100260997B1 (en) 1998-04-08 2000-07-01 마이클 디. 오브라이언 Semiconductor package
JPH11297889A (en) 1998-04-16 1999-10-29 Sony Corp Semiconductor package, mounting board and mounting method by use of them
KR100266693B1 (en) 1998-05-30 2000-09-15 김영환 Stackable ball grid array semiconductor package and fabrication method thereof
KR100265563B1 (en) 1998-06-29 2000-09-15 김영환 Ball grid array package and fabricating method thereof
US6414391B1 (en) 1998-06-30 2002-07-02 Micron Technology, Inc. Module assembly for stacked BGA packages with a common bus bar in the assembly
US6164523A (en) 1998-07-01 2000-12-26 Semiconductor Components Industries, Llc Electronic component and method of manufacture
US5854507A (en) 1998-07-21 1998-12-29 Hewlett-Packard Company Multiple chip assembly
US6050832A (en) 1998-08-07 2000-04-18 Fujitsu Limited Chip and board stress relief interposer
US6515355B1 (en) 1998-09-02 2003-02-04 Micron Technology, Inc. Passivation layer for packaged integrated circuits
JP2000091383A (en) 1998-09-07 2000-03-31 Ngk Spark Plug Co Ltd Wiring board
US6194250B1 (en) 1998-09-14 2001-02-27 Motorola, Inc. Low-profile microelectronic package
US6158647A (en) 1998-09-29 2000-12-12 Micron Technology, Inc. Concave face wire bond capillary
US6684007B2 (en) 1998-10-09 2004-01-27 Fujitsu Limited Optical coupling structures and the fabrication processes
US6268662B1 (en) 1998-10-14 2001-07-31 Texas Instruments Incorporated Wire bonded flip-chip assembly of semiconductor devices
JP3407275B2 (en) 1998-10-28 2003-05-19 インターナショナル・ビジネス・マシーンズ・コーポレーション Bump and method of forming the same
US6332270B2 (en) 1998-11-23 2001-12-25 International Business Machines Corporation Method of making high density integral test probe
JP3502776B2 (en) 1998-11-26 2004-03-02 新光電気工業株式会社 Metal foil with bump, circuit board, and semiconductor device using the same
US6426642B1 (en) 1999-02-16 2002-07-30 Micron Technology, Inc. Insert for seating a microelectronic device having a protrusion and a plurality of raised-contacts
US6206273B1 (en) 1999-02-17 2001-03-27 International Business Machines Corporation Structures and processes to create a desired probetip contact geometry on a wafer test probe
KR100319609B1 (en) 1999-03-09 2002-01-05 김영환 A wire arrayed chip size package and the fabrication method thereof
US6512552B1 (en) 1999-03-29 2003-01-28 Sony Corporation Subpicture stream change control
US6177729B1 (en) 1999-04-03 2001-01-23 International Business Machines Corporation Rolling ball connector
US6376769B1 (en) 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
US6258625B1 (en) 1999-05-18 2001-07-10 International Business Machines Corporation Method of interconnecting electronic components using a plurality of conductive studs
JP3398721B2 (en) 1999-05-20 2003-04-21 アムコー テクノロジー コリア インコーポレーティド Semiconductor package and manufacturing method thereof
US6782610B1 (en) 1999-05-21 2004-08-31 North Corporation Method for fabricating a wiring substrate by electroplating a wiring film on a metal base
US6181569B1 (en) 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
US6228687B1 (en) 1999-06-28 2001-05-08 Micron Technology, Inc. Wafer-level package and methods of fabricating
TW417839U (en) 1999-07-30 2001-01-01 Shen Ming Tung Stacked memory module structure and multi-layered stacked memory module structure using the same
JP4526651B2 (en) 1999-08-12 2010-08-18 富士通セミコンダクター株式会社 Semiconductor device
US6252178B1 (en) 1999-08-12 2001-06-26 Conexant Systems, Inc. Semiconductor device with bonding anchors in build-up layers
KR100842389B1 (en) 1999-09-02 2008-07-01 이비덴 가부시키가이샤 Printed circuit board and method of manufacturing printed circuit board
US6867499B1 (en) 1999-09-30 2005-03-15 Skyworks Solutions, Inc. Semiconductor packaging
TW512467B (en) 1999-10-12 2002-12-01 North Kk Wiring circuit substrate and manufacturing method therefor
JP3513444B2 (en) 1999-10-20 2004-03-31 株式会社新川 Method for forming pin-shaped wires
JP2001127246A (en) 1999-10-29 2001-05-11 Fujitsu Ltd Semiconductor device
US6362525B1 (en) 1999-11-09 2002-03-26 Cypress Semiconductor Corp. Circuit structure including a passive element formed within a grid array substrate and method for making the same
JP3619410B2 (en) 1999-11-18 2005-02-09 株式会社ルネサステクノロジ Bump forming method and system
JP3798597B2 (en) 1999-11-30 2006-07-19 富士通株式会社 Semiconductor device
JP3566156B2 (en) 1999-12-02 2004-09-15 株式会社新川 Method for forming pin-shaped wires
KR100426494B1 (en) 1999-12-20 2004-04-13 앰코 테크놀로지 코리아 주식회사 Semiconductor package and its manufacturing method
US6790757B1 (en) 1999-12-20 2004-09-14 Agere Systems Inc. Wire bonding method for copper interconnects in semiconductor devices
JP2001196407A (en) 2000-01-14 2001-07-19 Seiko Instruments Inc Semiconductor device and method of forming the same
JP3420153B2 (en) 2000-01-24 2003-06-23 Ｎｅｃエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US6710454B1 (en) 2000-02-16 2004-03-23 Micron Technology, Inc. Adhesive layer for an electronic apparatus having multiple semiconductor devices
EP1143509A3 (en) 2000-03-08 2004-04-07 Sanyo Electric Co., Ltd. Method of manufacturing the circuit device and circuit device
JP4074040B2 (en) 2000-03-14 2008-04-09 イビデン株式会社 Semiconductor module
JP2001339011A (en) 2000-03-24 2001-12-07 Shinko Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP3980807B2 (en) 2000-03-27 2007-09-26 株式会社東芝 Semiconductor device and semiconductor module
JP2001274196A (en) 2000-03-28 2001-10-05 Rohm Co Ltd Semiconductor device
KR20010094893A (en) 2000-04-07 2001-11-03 정보영 Loss protection device of valuables in bag
KR100583491B1 (en) 2000-04-07 2006-05-24 앰코 테크놀로지 코리아 주식회사 Semiconductor package and its manufacturing method
US6578754B1 (en) 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6531335B1 (en) 2000-04-28 2003-03-11 Micron Technology, Inc. Interposers including upwardly protruding dams, semiconductor device assemblies including the interposers, and methods
JP2001326236A (en) 2000-05-12 2001-11-22 Nec Kyushu Ltd Manufacturing method of semiconductor device
US6522018B1 (en) 2000-05-16 2003-02-18 Micron Technology, Inc. Ball grid array chip packages having improved testing and stacking characteristics
US6647310B1 (en) 2000-05-30 2003-11-11 Advanced Micro Devices, Inc. Temperature control of an integrated circuit
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
US6560117B2 (en) 2000-06-28 2003-05-06 Micron Technology, Inc. Packaged microelectronic die assemblies and methods of manufacture
US6476583B2 (en) 2000-07-21 2002-11-05 Jomahip, Llc Automatic battery charging system for a battery back-up DC power supply
SE517086C2 (en) 2000-08-08 2002-04-09 Ericsson Telefon Ab L M Method for securing solder beads and any components attached to one and the same side of a substrate
US6462575B1 (en) 2000-08-28 2002-10-08 Micron Technology, Inc. Method and system for wafer level testing and burning-in semiconductor components
JP3874062B2 (en) 2000-09-05 2007-01-31 セイコーエプソン株式会社 Semiconductor device
US6507104B2 (en) 2000-09-07 2003-01-14 Siliconware Precision Industries Co., Ltd. Semiconductor package with embedded heat-dissipating device
US7009297B1 (en) 2000-10-13 2006-03-07 Bridge Semiconductor Corporation Semiconductor chip assembly with embedded metal particle
US6423570B1 (en) 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
JP4505983B2 (en) 2000-12-01 2010-07-21 日本電気株式会社 Semiconductor device
JP3798620B2 (en) 2000-12-04 2006-07-19 富士通株式会社 Manufacturing method of semiconductor device
TW511405B (en) 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
KR100393102B1 (en) 2000-12-29 2003-07-31 앰코 테크놀로지 코리아 주식회사 Stacked semiconductor package
AUPR244801A0 (en) 2001-01-10 2001-02-01 Silverbrook Research Pty Ltd A method and apparatus (WSM01)
US6388322B1 (en) 2001-01-17 2002-05-14 Aralight, Inc. Article comprising a mechanically compliant bump
JP2002280414A (en) 2001-03-22 2002-09-27 Mitsubishi Electric Corp Semiconductor device and its manufacturing method
JP2002290030A (en) 2001-03-23 2002-10-04 Ngk Spark Plug Co Ltd Wiring board
JP2002289769A (en) 2001-03-26 2002-10-04 Matsushita Electric Ind Co Ltd Stacked semiconductor device and its manufacturing method
SG108245A1 (en) 2001-03-30 2005-01-28 Micron Technology Inc Ball grid array interposer, packages and methods
US7115986B2 (en) 2001-05-02 2006-10-03 Micron Technology, Inc. Flexible ball grid array chip scale packages
TW544826B (en) 2001-05-18 2003-08-01 Nec Electronics Corp Flip-chip-type semiconductor device and manufacturing method thereof
US6930256B1 (en) 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
US6754407B2 (en) 2001-06-26 2004-06-22 Intel Corporation Flip-chip package integrating optical and electrical devices and coupling to a waveguide on a board
US20030006494A1 (en) 2001-07-03 2003-01-09 Lee Sang Ho Thin profile stackable semiconductor package and method for manufacturing
TWI224382B (en) 2001-07-12 2004-11-21 Hitachi Ltd Wiring glass substrate and manufacturing method thereof, conductive paste and semiconductor module used for the same, and conductor forming method
US6765287B1 (en) 2001-07-27 2004-07-20 Charles W. C. Lin Three-dimensional stacked semiconductor package
US6451626B1 (en) 2001-07-27 2002-09-17 Charles W.C. Lin Three-dimensional stacked semiconductor package
JP4023159B2 (en) 2001-07-31 2007-12-19 ソニー株式会社 Manufacturing method of semiconductor device and manufacturing method of laminated semiconductor device
US6550666B2 (en) 2001-08-21 2003-04-22 Advanpack Solutions Pte Ltd Method for forming a flip chip on leadframe semiconductor package
WO2003019654A1 (en) 2001-08-22 2003-03-06 Tessera, Inc. Stacked chip assembly with stiffening layer
US6856007B2 (en) 2001-08-28 2005-02-15 Tessera, Inc. High-frequency chip packages
US7176506B2 (en) 2001-08-28 2007-02-13 Tessera, Inc. High frequency chip packages with connecting elements
US20030057544A1 (en) 2001-09-13 2003-03-27 Nathan Richard J. Integrated assembly protocol
JP2003122611A (en) 2001-10-11 2003-04-25 Oki Electric Ind Co Ltd Data providing method and server device
JP4257771B2 (en) 2001-10-16 2009-04-22 シンジーテック株式会社 Conductive blade
JP3875077B2 (en) 2001-11-16 2007-01-31 富士通株式会社 Electronic device and device connection method
US20030094666A1 (en) 2001-11-16 2003-05-22 R-Tec Corporation Interposer
TW498472B (en) 2001-11-27 2002-08-11 Via Tech Inc Tape-BGA package and its manufacturing process
JP2003174124A (en) 2001-12-04 2003-06-20 Sainekkusu:Kk Method of forming external electrode of semiconductor device
JP2003197669A (en) 2001-12-28 2003-07-11 Seiko Epson Corp Bonding method and bonding apparatus
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
JP4045143B2 (en) 2002-02-18 2008-02-13 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド Manufacturing method of wiring film connecting member and manufacturing method of multilayer wiring board
JP3935370B2 (en) 2002-02-19 2007-06-20 セイコーエプソン株式会社 Bumped semiconductor element manufacturing method, semiconductor device and manufacturing method thereof, circuit board, and electronic device
SG115456A1 (en) 2002-03-04 2005-10-28 Micron Technology Inc Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
US6653723B2 (en) 2002-03-09 2003-11-25 Fujitsu Limited System for providing an open-cavity low profile encapsulated semiconductor package
KR100452819B1 (en) 2002-03-18 2004-10-15 삼성전기주식회사 Chip scale package and method of fabricating the same
US6979230B2 (en) 2002-03-20 2005-12-27 Gabe Cherian Light socket
JP3717899B2 (en) 2002-04-01 2005-11-16 Ｎｅｃエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US7323767B2 (en) 2002-04-25 2008-01-29 Micron Technology, Inc. Standoffs for centralizing internals in packaging process
US7633765B1 (en) 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
JP2004047702A (en) 2002-07-11 2004-02-12 Toshiba Corp Semiconductor device laminated module
US6987032B1 (en) 2002-07-19 2006-01-17 Asat Ltd. Ball grid array package and process for manufacturing same
US6984545B2 (en) 2002-07-22 2006-01-10 Micron Technology, Inc. Methods of encapsulating selected locations of a semiconductor die assembly using a thick solder mask
TW549592U (en) 2002-08-16 2003-08-21 Via Tech Inc Integrated circuit package with a balanced-part structure
US6740546B2 (en) 2002-08-21 2004-05-25 Micron Technology, Inc. Packaged microelectronic devices and methods for assembling microelectronic devices
US6964881B2 (en) 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
US7294928B2 (en) 2002-09-06 2007-11-13 Tessera, Inc. Components, methods and assemblies for stacked packages
US7229906B2 (en) 2002-09-19 2007-06-12 Kulicke And Soffa Industries, Inc. Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine
US7259445B2 (en) 2002-09-30 2007-08-21 Advanced Interconnect Technologies Limited Thermal enhanced package for block mold assembly
US7045884B2 (en) 2002-10-04 2006-05-16 International Rectifier Corporation Semiconductor device package
US7049691B2 (en) 2002-10-08 2006-05-23 Chippac, Inc. Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package
TW567601B (en) 2002-10-18 2003-12-21 Siliconware Precision Industries Co Ltd Module device of stacked semiconductor package and method for fabricating the same
TWI221664B (en) 2002-11-07 2004-10-01 Via Tech Inc Structure of chip package and process thereof
JP2004172477A (en) 2002-11-21 2004-06-17 Kaijo Corp Wire loop form, semiconductor device having the same, wire bonding method, and semiconductor manufacturing apparatus
KR100621991B1 (en) 2003-01-03 2006-09-13 삼성전자주식회사 Chip scale stack package
JP2004221257A (en) 2003-01-14 2004-08-05 Seiko Epson Corp Wire bonding method and device thereof
TWI241700B (en) 2003-01-22 2005-10-11 Siliconware Precision Industries Co Ltd Packaging assembly with integrated circuits redistribution routing semiconductor die and method for fabrication
US6753600B1 (en) 2003-01-28 2004-06-22 Thin Film Module, Inc. Structure of a substrate for a high density semiconductor package
US20040217471A1 (en) 2003-02-27 2004-11-04 Tessera, Inc. Component and assemblies with ends offset downwardly
JP3885747B2 (en) 2003-03-13 2007-02-28 株式会社デンソー Wire bonding method
US20040183167A1 (en) 2003-03-21 2004-09-23 Texas Instruments Incorporated Recessed-bond semiconductor package substrate
JP2004343030A (en) 2003-03-31 2004-12-02 North:Kk Wiring circuit board, manufacturing method thereof, circuit module provided with this wiring circuit board
JP4199588B2 (en) 2003-04-25 2008-12-17 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド Wiring circuit board manufacturing method and semiconductor integrated circuit device manufacturing method using the wiring circuit board
DE10320646A1 (en) 2003-05-07 2004-09-16 Infineon Technologies Ag Electronic component, typically integrated circuit, system support and manufacturing method, with support containing component positions in lines and columns, starting with coating auxiliary support with photosensitive layer
US7166491B2 (en) 2003-06-11 2007-01-23 Fry's Metals, Inc. Thermoplastic fluxing underfill composition and method
JP4145730B2 (en) 2003-06-17 2008-09-03 松下電器産業株式会社 Module with built-in semiconductor
KR100604821B1 (en) 2003-06-30 2006-07-26 삼성전자주식회사 Stack type Ball grid array package and method for manufacturing the same
US20040262728A1 (en) 2003-06-30 2004-12-30 Sterrett Terry L. Modular device assemblies
US7227095B2 (en) 2003-08-06 2007-06-05 Micron Technology, Inc. Wire bonders and methods of wire-bonding
KR100546374B1 (en) 2003-08-28 2006-01-26 삼성전자주식회사 Multi chip package having center pads and method for manufacturing the same
US7372151B1 (en) 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same
US7061096B2 (en) 2003-09-24 2006-06-13 Silicon Pipe, Inc. Multi-surface IC packaging structures and methods for their manufacture
US20050085016A1 (en) 2003-09-26 2005-04-21 Tessera, Inc. Structure and method of making capped chips using sacrificial layer
US8641913B2 (en) 2003-10-06 2014-02-04 Tessera, Inc. Fine pitch microcontacts and method for forming thereof
US7462936B2 (en) 2003-10-06 2008-12-09 Tessera, Inc. Formation of circuitry with modification of feature height
JP4272968B2 (en) 2003-10-16 2009-06-03 エルピーダメモリ株式会社 Semiconductor device and semiconductor chip control method
JP4167965B2 (en) 2003-11-07 2008-10-22 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド Method for manufacturing wiring circuit member
KR100564585B1 (en) 2003-11-13 2006-03-28 삼성전자주식회사 Double stacked BGA package and multi-stacked BGA package
TWI227555B (en) 2003-11-17 2005-02-01 Advanced Semiconductor Eng Structure of chip package and the process thereof
KR100621992B1 (en) 2003-11-19 2006-09-13 삼성전자주식회사 structure and method of wafer level stack for devices of different kind and system-in-package using the same
JP2005183923A (en) 2003-11-28 2005-07-07 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
US7345361B2 (en) 2003-12-04 2008-03-18 Intel Corporation Stackable integrated circuit packaging
JP2005175019A (en) 2003-12-08 2005-06-30 Sharp Corp Semiconductor device and multilayer semiconductor device
JP5197961B2 (en) 2003-12-17 2013-05-15 スタッツ・チップパック・インコーポレイテッド Multi-chip package module and manufacturing method thereof
DE10360708B4 (en) 2003-12-19 2008-04-10 Infineon Technologies Ag Semiconductor module with a semiconductor stack, rewiring plate, and method of making the same
JP4334996B2 (en) 2003-12-24 2009-09-30 株式会社フジクラ SUBSTRATE FOR MULTILAYER WIRING BOARD, DOUBLE WIRE WIRING BOARD AND METHOD FOR PRODUCING THEM
US7495644B2 (en) 2003-12-26 2009-02-24 Semiconductor Energy Laboratory Co., Ltd. Display device and method for manufacturing display device
US6917098B1 (en) 2003-12-29 2005-07-12 Texas Instruments Incorporated Three-level leadframe for no-lead packages
US6900530B1 (en) 2003-12-29 2005-05-31 Ramtek Technology, Inc. Stacked IC
US7709968B2 (en) 2003-12-30 2010-05-04 Tessera, Inc. Micro pin grid array with pin motion isolation
US8207604B2 (en) 2003-12-30 2012-06-26 Tessera, Inc. Microelectronic package comprising offset conductive posts on compliant layer
WO2005065207A2 (en) 2003-12-30 2005-07-21 Tessera, Inc. Microelectronic packages and methods therefor
JP2005203497A (en) 2004-01-14 2005-07-28 Toshiba Corp Semiconductor device and method for manufacturing same
US20050173807A1 (en) 2004-02-05 2005-08-11 Jianbai Zhu High density vertically stacked semiconductor device
US7095105B2 (en) 2004-03-23 2006-08-22 Texas Instruments Incorporated Vertically stacked semiconductor device
JP4484035B2 (en) 2004-04-06 2010-06-16 セイコーエプソン株式会社 Manufacturing method of semiconductor device
US8092734B2 (en) 2004-05-13 2012-01-10 Aptina Imaging Corporation Covers for microelectronic imagers and methods for wafer-level packaging of microelectronics imagers
US6962864B1 (en) 2004-05-26 2005-11-08 National Chung Cheng University Wire-bonding method for chips with copper interconnects by introducing a thin layer
US7233057B2 (en) 2004-05-28 2007-06-19 Nokia Corporation Integrated circuit package with optimized mold shape
US7453157B2 (en) 2004-06-25 2008-11-18 Tessera, Inc. Microelectronic packages and methods therefor
JP4343044B2 (en) * 2004-06-30 2009-10-14 新光電気工業株式会社 Interposer, manufacturing method thereof, and semiconductor device
JP4012527B2 (en) 2004-07-14 2007-11-21 日本無線株式会社 Manufacturing method of electronic parts
US7049208B2 (en) 2004-10-11 2006-05-23 Intel Corporation Method of manufacturing of thin based substrate
EP1807239A2 (en) 2004-11-02 2007-07-18 Imasys AG Laying device, contacting device, advancing system, laying and contacting unit, production system, method for the production and a transponder unit
KR101313391B1 (en) 2004-11-03 2013-10-01 테세라, 인코포레이티드 Stacked packaging improvements
US7750483B1 (en) 2004-11-10 2010-07-06 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal
KR100674926B1 (en) 2004-12-08 2007-01-26 삼성전자주식회사 Memory card and method of fabricating the same
JP4504798B2 (en) 2004-12-16 2010-07-14 パナソニック株式会社 Multistage semiconductor module
JP2006186086A (en) 2004-12-27 2006-07-13 Itoo:Kk Method for soldering printed circuit board and guide plate for preventing bridge
DE102005006333B4 (en) 2005-02-10 2007-10-18 Infineon Technologies Ag Semiconductor device having a plurality of bonding terminals and bonded contact elements of different metal composition and method for producing the same
DE102005006995B4 (en) 2005-02-15 2008-01-24 Infineon Technologies Ag Semiconductor device with plastic housing and external connections and method for producing the same
KR100630741B1 (en) 2005-03-04 2006-10-02 삼성전자주식회사 Stack type semiconductor package having a multiple molding process and manufacturing method thereof
US7371676B2 (en) 2005-04-08 2008-05-13 Micron Technology, Inc. Method for fabricating semiconductor components with through wire interconnects
TWI284394B (en) 2005-05-12 2007-07-21 Advanced Semiconductor Eng Lid used in package structure and the package structure of having the same
JP2006324553A (en) 2005-05-20 2006-11-30 Renesas Technology Corp Semiconductor device and method of manufacturing same
US7216794B2 (en) 2005-06-09 2007-05-15 Texas Instruments Incorporated Bond capillary design for ribbon wire bonding
WO2007004137A2 (en) 2005-07-01 2007-01-11 Koninklijke Philips Electronics N.V. Electronic device
US7476608B2 (en) 2005-07-14 2009-01-13 Hewlett-Packard Development Company, L.P. Electrically connecting substrate with electrical device
US7675152B2 (en) 2005-09-01 2010-03-09 Texas Instruments Incorporated Package-on-package semiconductor assembly
US7504716B2 (en) 2005-10-26 2009-03-17 Texas Instruments Incorporated Structure and method of molded QFN device suitable for miniaturization, multiple rows and stacking
JP2007123595A (en) 2005-10-28 2007-05-17 Nec Corp Semiconductor device and its mounting structure
JP4530975B2 (en) 2005-11-14 2010-08-25 株式会社新川 Wire bonding method
JP2007142042A (en) 2005-11-16 2007-06-07 Sharp Corp Semiconductor package, manufacturing method thereof, semiconductor module, and electronic equipment
US7344917B2 (en) 2005-11-30 2008-03-18 Freescale Semiconductor, Inc. Method for packaging a semiconductor device
US8067267B2 (en) 2005-12-23 2011-11-29 Tessera, Inc. Microelectronic assemblies having very fine pitch stacking
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US20070190747A1 (en) 2006-01-23 2007-08-16 Tessera Technologies Hungary Kft. Wafer level packaging to lidded chips
SG135074A1 (en) 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
US7759782B2 (en) 2006-04-07 2010-07-20 Tessera, Inc. Substrate for a microelectronic package and method of fabricating thereof
US7390700B2 (en) 2006-04-07 2008-06-24 Texas Instruments Incorporated Packaged system of semiconductor chips having a semiconductor interposer
JP5598787B2 (en) 2006-04-17 2014-10-01 マイクロンメモリジャパン株式会社 Manufacturing method of stacked semiconductor device
US7242081B1 (en) 2006-04-24 2007-07-10 Advanced Semiconductor Engineering Inc. Stacked package structure
US7780064B2 (en) 2006-06-02 2010-08-24 Asm Technology Singapore Pte Ltd Wire bonding method for forming low-loop profiles
US7967062B2 (en) 2006-06-16 2011-06-28 International Business Machines Corporation Thermally conductive composite interface, cooled electronic assemblies employing the same, and methods of fabrication thereof
US20070290325A1 (en) 2006-06-16 2007-12-20 Lite-On Semiconductor Corporation Surface mounting structure and packaging method thereof
CN101449375B (en) 2006-06-29 2012-01-18 英特尔公司 A device, a system and a method applied to the connection without leads in the encapsulation of an integrate circuit
KR100792352B1 (en) 2006-07-06 2008-01-08 삼성전기주식회사 Bottom substrate of pop and manufacturing method thereof
KR100800478B1 (en) 2006-07-18 2008-02-04 삼성전자주식회사 Stack type semiconductor package and method of fabricating the same
US20080023805A1 (en) 2006-07-26 2008-01-31 Texas Instruments Incorporated Array-Processed Stacked Semiconductor Packages
US8048479B2 (en) 2006-08-01 2011-11-01 Qimonda Ag Method for placing material onto a target board by means of a transfer board
JP2008039502A (en) 2006-08-03 2008-02-21 Alps Electric Co Ltd Contact and its manufacturing method
US7486525B2 (en) 2006-08-04 2009-02-03 International Business Machines Corporation Temporary chip attach carrier
US7425758B2 (en) 2006-08-28 2008-09-16 Micron Technology, Inc. Metal core foldover package structures
KR20080020069A (en) 2006-08-30 2008-03-05 삼성전자주식회사 Semiconductor package and method for fabricating the same
KR100891516B1 (en) 2006-08-31 2009-04-06 주식회사 하이닉스반도체 Stackable fbga type semiconductor package and stack package using the same
KR100770934B1 (en) 2006-09-26 2007-10-26 삼성전자주식회사 Semiconductor package and semiconductor system in package
TWI336502B (en) 2006-09-27 2011-01-21 Advanced Semiconductor Eng Semiconductor package and semiconductor device and the method of making the same
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
TWI312561B (en) 2006-10-27 2009-07-21 Advanced Semiconductor Eng Structure of package on package and method for fabricating the same
KR100817073B1 (en) 2006-11-03 2008-03-26 삼성전자주식회사 Semiconductor chip stack package with reinforce member for preventing package warpage connected to pcb
US8193034B2 (en) 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
WO2008065896A1 (en) 2006-11-28 2008-06-05 Kyushu Institute Of Technology Method for manufacturing semiconductor device having dual-face electrode structure and semiconductor device manufactured by the method
US7659617B2 (en) 2006-11-30 2010-02-09 Tessera, Inc. Substrate for a flexible microelectronic assembly and a method of fabricating thereof
US8598717B2 (en) 2006-12-27 2013-12-03 Spansion Llc Semiconductor device and method for manufacturing the same
KR100757345B1 (en) 2006-12-29 2007-09-10 삼성전자주식회사 Flip chip package and method of manufacturing the same
US20080156518A1 (en) 2007-01-03 2008-07-03 Tessera, Inc. Alignment and cutting of microelectronic substrates
TWI332702B (en) 2007-01-09 2010-11-01 Advanced Semiconductor Eng Stackable semiconductor package and the method for making the same
US7719122B2 (en) 2007-01-11 2010-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. System-in-package packaging for minimizing bond wire contamination and yield loss
JP4823089B2 (en) 2007-01-31 2011-11-24 株式会社東芝 Manufacturing method of stacked semiconductor device
CN101617400A (en) 2007-01-31 2009-12-30 富士通微电子株式会社 Semiconductor device and manufacture method thereof
US8685792B2 (en) 2007-03-03 2014-04-01 Stats Chippac Ltd. Integrated circuit package system with interposer
EP2575166A3 (en) 2007-03-05 2014-04-09 Invensas Corporation Chips having rear contacts connected by through vias to front contacts
US7517733B2 (en) 2007-03-22 2009-04-14 Stats Chippac, Ltd. Leadframe design for QFN package with top terminal leads
JPWO2008117488A1 (en) 2007-03-23 2010-07-08 三洋電機株式会社 Semiconductor device and manufacturing method thereof
WO2008120755A1 (en) 2007-03-30 2008-10-09 Nec Corporation Circuit board incorporating functional element, method for manufacturing the circuit board, and electronic device
JP4926787B2 (en) 2007-03-30 2012-05-09 アオイ電子株式会社 Manufacturing method of semiconductor device
US7589394B2 (en) 2007-04-10 2009-09-15 Ibiden Co., Ltd. Interposer
JP5003260B2 (en) 2007-04-13 2012-08-15 日本電気株式会社 Semiconductor device and manufacturing method thereof
US7994622B2 (en) 2007-04-16 2011-08-09 Tessera, Inc. Microelectronic packages having cavities for receiving microelectric elements
KR20080094251A (en) 2007-04-19 2008-10-23 삼성전자주식회사 Wafer level package and method for the manufacturing same
US20080284045A1 (en) 2007-05-18 2008-11-20 Texas Instruments Incorporated Method for Fabricating Array-Molded Package-On-Package
JP2008306128A (en) 2007-06-11 2008-12-18 Shinko Electric Ind Co Ltd Semiconductor device and its production process
KR100865125B1 (en) 2007-06-12 2008-10-24 삼성전기주식회사 Semiconductor and method for manufacturing thereof
US7944034B2 (en) 2007-06-22 2011-05-17 Texas Instruments Incorporated Array molded package-on-package having redistribution lines
JP5179787B2 (en) 2007-06-22 2013-04-10 ラピスセミコンダクタ株式会社 Semiconductor device and manufacturing method thereof
SG148901A1 (en) 2007-07-09 2009-01-29 Micron Technology Inc Packaged semiconductor assemblies and methods for manufacturing such assemblies
KR20090007120A (en) 2007-07-13 2009-01-16 삼성전자주식회사 An wafer level stacked package having a via contact in encapsulation portion and manufacturing method thereof
US7781877B2 (en) 2007-08-07 2010-08-24 Micron Technology, Inc. Packaged integrated circuit devices with through-body conductive vias, and methods of making same
JP2009044110A (en) 2007-08-13 2009-02-26 Elpida Memory Inc Semiconductor device and its manufacturing method
SG150396A1 (en) 2007-08-16 2009-03-30 Micron Technology Inc Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
US8558379B2 (en) 2007-09-28 2013-10-15 Tessera, Inc. Flip chip interconnection with double post
JP2009088254A (en) 2007-09-28 2009-04-23 Toshiba Corp Electronic component package, and manufacturing method for electronic component package
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
KR20090033605A (en) 2007-10-01 2009-04-06 삼성전자주식회사 Stack-type semicondoctor package, method of forming the same and electronic system including the same
US20090091009A1 (en) 2007-10-03 2009-04-09 Corisis David J Stackable integrated circuit package
US8008183B2 (en) 2007-10-04 2011-08-30 Texas Instruments Incorporated Dual capillary IC wirebonding
TWI389220B (en) 2007-10-22 2013-03-11 矽品精密工業股份有限公司 Semiconductor package and method for fabricating the same
TWI360207B (en) 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
US20090127686A1 (en) 2007-11-21 2009-05-21 Advanced Chip Engineering Technology Inc. Stacking die package structure for semiconductor devices and method of the same
KR100886100B1 (en) 2007-11-29 2009-02-27 앰코 테크놀로지 코리아 주식회사 Semiconductor package and method for manufacturing the same
US7902644B2 (en) 2007-12-07 2011-03-08 Stats Chippac Ltd. Integrated circuit package system for electromagnetic isolation
US7964956B1 (en) 2007-12-10 2011-06-21 Oracle America, Inc. Circuit packaging and connectivity
US8390117B2 (en) 2007-12-11 2013-03-05 Panasonic Corporation Semiconductor device and method of manufacturing the same
US20090170241A1 (en) 2007-12-26 2009-07-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
US8120186B2 (en) 2008-02-15 2012-02-21 Qimonda Ag Integrated circuit and method
US8258015B2 (en) 2008-02-22 2012-09-04 Stats Chippac Ltd. Integrated circuit package system with penetrable film adhesive
US7919871B2 (en) 2008-03-21 2011-04-05 Stats Chippac Ltd. Integrated circuit package system for stackable devices
JP5043743B2 (en) 2008-04-18 2012-10-10 ラピスセミコンダクタ株式会社 Manufacturing method of semiconductor device
KR20090123680A (en) 2008-05-28 2009-12-02 주식회사 하이닉스반도체 Stacked semiconductor package
US8021907B2 (en) 2008-06-09 2011-09-20 Stats Chippac, Ltd. Method and apparatus for thermally enhanced semiconductor package
US7932170B1 (en) 2008-06-23 2011-04-26 Amkor Technology, Inc. Flip chip bump structure and fabrication method
TWI372453B (en) 2008-09-01 2012-09-11 Advanced Semiconductor Eng Copper bonding wire, wire bonding structure and method for processing and bonding a wire
US8384203B2 (en) 2008-07-18 2013-02-26 United Test And Assembly Center Ltd. Packaging structural member
US8004093B2 (en) 2008-08-01 2011-08-23 Stats Chippac Ltd. Integrated circuit package stacking system
JPWO2010024233A1 (en) 2008-08-27 2012-01-26 日本電気株式会社 Wiring board capable of incorporating functional elements and method for manufacturing the same
KR20100033012A (en) 2008-09-19 2010-03-29 주식회사 하이닉스반도체 Semiconductor package and stacked semiconductor package having the same
US7842541B1 (en) 2008-09-24 2010-11-30 Amkor Technology, Inc. Ultra thin package and fabrication method
US8063475B2 (en) 2008-09-26 2011-11-22 Stats Chippac Ltd. Semiconductor package system with through silicon via interposer
JP5185062B2 (en) 2008-10-21 2013-04-17 パナソニック株式会社 Multilayer semiconductor device and electronic device
MY149251A (en) 2008-10-23 2013-07-31 Carsem M Sdn Bhd Wafer-level package using stud bump coated with solder
KR101461630B1 (en) 2008-11-06 2014-11-20 삼성전자주식회사 Wafer level chip on chip package, package on package improving solder joint reliability but reducing mounting height and manufacturing method thereof
US7838337B2 (en) 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
TW201023308A (en) 2008-12-01 2010-06-16 Advanced Semiconductor Eng Package-on-package device, semiconductor package and method for manufacturing the same
KR101011863B1 (en) 2008-12-02 2011-01-31 앰코 테크놀로지 코리아 주식회사 Semiconductor package and fabricating?method thereof
US7858441B2 (en) 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
US7642128B1 (en) 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US8012797B2 (en) 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
JP2010177597A (en) 2009-01-30 2010-08-12 Sanyo Electric Co Ltd Semiconductor module and portable device
JP5471605B2 (en) 2009-03-04 2014-04-16 日本電気株式会社 Semiconductor device and manufacturing method thereof
JP2010206007A (en) 2009-03-04 2010-09-16 Nec Corp Semiconductor device and method of manufacturing the same
US8106498B2 (en) 2009-03-05 2012-01-31 Stats Chippac Ltd. Integrated circuit packaging system with a dual board-on-chip structure and method of manufacture thereof
US8258010B2 (en) 2009-03-17 2012-09-04 Stats Chippac, Ltd. Making a semiconductor device having conductive through organic vias
US20100244276A1 (en) 2009-03-25 2010-09-30 Lsi Corporation Three-dimensional electronics package
US20100289142A1 (en) 2009-05-15 2010-11-18 Il Kwon Shim Integrated circuit packaging system with coin bonded interconnects and method of manufacture thereof
US8020290B2 (en) 2009-06-14 2011-09-20 Jayna Sheats Processes for IC fabrication
TWI379367B (en) 2009-06-15 2012-12-11 Kun Yuan Technology Co Ltd Chip packaging method and structure thereof
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
JP5214554B2 (en) 2009-07-30 2013-06-19 ラピスセミコンダクタ株式会社 Semiconductor chip built-in package and manufacturing method thereof, and package-on-package semiconductor device and manufacturing method thereof
US7923304B2 (en) 2009-09-10 2011-04-12 Stats Chippac Ltd. Integrated circuit packaging system with conductive pillars and method of manufacture thereof
US8164158B2 (en) 2009-09-11 2012-04-24 Stats Chippac, Ltd. Semiconductor device and method of forming integrated passive device
US8264091B2 (en) 2009-09-21 2012-09-11 Stats Chippac Ltd. Integrated circuit packaging system with encapsulated via and method of manufacture thereof
JP5590869B2 (en) * 2009-12-07 2014-09-17 新光電気工業株式会社 WIRING BOARD, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR PACKAGE
US8390108B2 (en) 2009-12-16 2013-03-05 Stats Chippac Ltd. Integrated circuit packaging system with stacking interconnect and method of manufacture thereof
US8169065B2 (en) 2009-12-22 2012-05-01 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
US8278752B2 (en) 2009-12-23 2012-10-02 Intel Corporation Microelectronic package and method for a compression-based mid-level interconnect
TWI392066B (en) 2009-12-28 2013-04-01 矽品精密工業股份有限公司 Package structure and fabrication method thereof
US7928552B1 (en) 2010-03-12 2011-04-19 Stats Chippac Ltd. Integrated circuit packaging system with multi-tier conductive interconnects and method of manufacture thereof
US9496152B2 (en) 2010-03-12 2016-11-15 STATS ChipPAC Pte. Ltd. Carrier system with multi-tier conductive posts and method of manufacture thereof
KR101667656B1 (en) 2010-03-24 2016-10-20 삼성전자주식회사 Method of forming package on package
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8217502B2 (en) 2010-06-08 2012-07-10 Stats Chippac Ltd. Integrated circuit packaging system with multipart conductive pillars and method of manufacture thereof
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
KR20120007839A (en) 2010-07-15 2012-01-25 삼성전자주식회사 Manufacturing method of stack type package
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
KR101683814B1 (en) 2010-07-26 2016-12-08 삼성전자주식회사 Semiconductor apparatus having through vias
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8304900B2 (en) 2010-08-11 2012-11-06 Stats Chippac Ltd. Integrated circuit packaging system with stacked lead and method of manufacture thereof
US20120063090A1 (en) 2010-09-09 2012-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling mechanism for stacked die package and method of manufacturing the same
US8409922B2 (en) 2010-09-14 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect
US8618646B2 (en) 2010-10-12 2013-12-31 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US8697492B2 (en) 2010-11-02 2014-04-15 Tessera, Inc. No flow underfill
US8525318B1 (en) 2010-11-10 2013-09-03 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
KR101075241B1 (en) 2010-11-15 2011-11-01 테세라, 인코포레이티드 Microelectronic package with terminals on dielectric mass
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8502387B2 (en) 2010-12-09 2013-08-06 Stats Chippac Ltd. Integrated circuit packaging system with vertical interconnection and method of manufacture thereof
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US20120184116A1 (en) 2011-01-18 2012-07-19 Tyco Electronics Corporation Interposer
US8476115B2 (en) 2011-05-03 2013-07-02 Stats Chippac, Ltd. Semiconductor device and method of mounting cover to semiconductor die and interposer with adhesive material
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9117811B2 (en) * 2011-06-13 2015-08-25 Tessera, Inc. Flip chip assembly and process with sintering material on metal bumps
US20130037929A1 (en) 2011-08-09 2013-02-14 Kay S. Essig Stackable wafer level packages and related methods
KR101800440B1 (en) 2011-08-31 2017-11-23 삼성전자주식회사 Semiconductor package having plural semiconductor chips and method of forming the same
US9177832B2 (en) 2011-09-16 2015-11-03 Stats Chippac, Ltd. Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnect
US9105552B2 (en) 2011-10-31 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US8912651B2 (en) 2011-11-30 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) structure including stud bulbs and method
US8680684B2 (en) 2012-01-09 2014-03-25 Invensas Corporation Stackable microelectronic package structures
US8978247B2 (en) 2012-05-22 2015-03-17 Invensas Corporation TSV fabrication using a removable handling structure
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9209156B2 (en) * 2012-09-28 2015-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuits stacking approach
US8909933B2 (en) 2012-10-25 2014-12-09 International Business Machines Corporation Decoupled cryptographic schemes using a visual channel
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9646917B2 (en) * 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
WO2016009974A1 (en) 2014-07-15 2016-01-21 富士フイルム株式会社 Detection system and detection method

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5195237A (en) * 1987-05-21 1993-03-23 Cray Computer Corporation Flying leads for integrated circuits
US6459039B1 (en) * 2000-06-19 2002-10-01 International Business Machines Corporation Method and apparatus to manufacture an electronic package with direct wiring pattern
US20050194180A1 (en) * 2004-03-02 2005-09-08 Kirby Kyle K. Compliant contact pin assembly, card system and methods thereof
US20060012026A1 (en) * 2004-07-14 2006-01-19 Suk-Chae Kang Semiconductor package and method for its manufacture
US20070035033A1 (en) * 2005-05-26 2007-02-15 Volkan Ozguz Stackable tier structure comprising high density feedthrough
US20070246819A1 (en) * 2006-04-24 2007-10-25 Micron Technology, Inc. Semiconductor components and systems having encapsulated through wire interconnects (TWI) and wafer level methods of fabrication
FR2957191A1 (en) * 2010-03-04 2011-09-09 Tronic S Microsystems Electrical interconnection support structure i.e. interposer, fabricating method for e.g. micro electromechanical system integrated circuits, involves depositing electric contact point on upper face at level of wire, and removing backplate
WO2012067177A1 (en) * 2010-11-17 2012-05-24 株式会社フジクラ Wiring board and method for producing same
US20140036454A1 (en) * 2012-08-03 2014-02-06 Invensas Corporation Bva interposer
US20140070423A1 (en) * 2012-09-13 2014-03-13 Invensas Corporation Tunable composite interposer

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