WO2015111623A1 - Lead frame and method for manufacturing same, semiconductor device and method for manufacturing same - Google Patents

Lead frame and method for manufacturing same, semiconductor device and method for manufacturing same Download PDF

Info

Publication number
WO2015111623A1
WO2015111623A1 PCT/JP2015/051545 JP2015051545W WO2015111623A1 WO 2015111623 A1 WO2015111623 A1 WO 2015111623A1 JP 2015051545 W JP2015051545 W JP 2015051545W WO 2015111623 A1 WO2015111623 A1 WO 2015111623A1
Authority
WO
WIPO (PCT)
Prior art keywords
lead
die pad
portions
lead frame
outer peripheral
Prior art date
Application number
PCT/JP2015/051545
Other languages
French (fr)
Japanese (ja)
Inventor
永田　昌博
雅樹 矢崎
幸治 冨田
Original Assignee
大日本印刷株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 大日本印刷株式会社 filed Critical 大日本印刷株式会社
Publication of WO2015111623A1 publication Critical patent/WO2015111623A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Definitions

  • the present invention relates to a lead frame and a manufacturing method thereof, and a semiconductor device and a manufacturing method thereof.
  • the present invention has been made in view of the above points, and can increase the number of terminal portions (number of pins) connected to the outside, a lead frame, a manufacturing method thereof, and a semiconductor device and a manufacturing method thereof. It aims to provide a method.
  • the present invention provides a lead frame for a semiconductor device, a die pad on which a semiconductor element is mounted, a plurality of outer peripheral lead portions provided around the die pad, each including a first terminal portion, the die pad, and the outer peripheral lead.
  • a connection ring that surrounds the die pad and a plurality of inner lead portions that are supported by the connection ring and each include a second terminal portion, wherein the plurality of inner lead portions are long inner leads. And a short inner lead portion, wherein the long inner lead portion and the short inner lead portion are alternately arranged along the connection ring.
  • the present invention is the lead frame characterized in that the plurality of inner lead portions extend from both the inner side and the outer side of the connection ring.
  • the short inner lead portion extending from the inner side of the connection ring and the long inner lead portion extending from the outer side of the connection ring are opposite to each other via the connection ring.
  • the lead frame is disposed at a side position.
  • the present invention is the lead frame characterized in that a concave groove is formed along the connection ring on the surface of the connection ring.
  • the present invention is the lead frame characterized in that the inner lead portion has a connection lead coupled to the connection ring, and the connection lead is thinned from the back side.
  • the present invention is the lead frame characterized in that the inner lead portion has a connection lead coupled to the connection ring, and the connection lead is thinned from the surface side.
  • the plurality of outer peripheral lead portions include a long outer peripheral lead portion and a short outer peripheral lead portion, and the long outer peripheral lead portions and the short outer peripheral lead portion are alternately arranged, and the plurality of inner lead portions Extending from at least the outside of the connection ring, wherein the long outer periphery lead portion and the short inner lead portion face each other, and the short outer periphery lead portion and the long inner lead portion face each other. It is a frame.
  • the present invention is a lead frame characterized in that it is made of a metal material having a tensile strength of 750 Mpa to 1100 Mpa.
  • the present invention provides a lead frame for a semiconductor device, a die pad on which a semiconductor element is mounted, a plurality of outer peripheral lead portions provided around the die pad, each including a first terminal portion, the die pad, and the outer peripheral lead.
  • a lead connecting portion disposed between the lead connecting portion and a plurality of inner lead portions each supported by the lead connecting portion and including a second terminal portion, wherein the plurality of inner lead portions include a long inner lead portion and And a short inner lead portion, wherein the long inner lead portion and the short inner lead portion are alternately arranged along the lead connecting portion.
  • the present invention is a semiconductor device, and is disposed around a die pad, a plurality of outer peripheral lead portions each including a first terminal portion, and between the die pad and the outer peripheral lead portion. And a plurality of second terminal portions separated from the outer periphery lead portion, a semiconductor element mounted on the die pad, and electrically connecting the semiconductor element and each outer periphery lead portion; and A sealing member that seals the connection member that electrically connects the second terminal portion, the die pad, the plurality of outer peripheral lead portions, the plurality of second terminal portions, the semiconductor element, and the connection member.
  • a plurality of outer peripheral lead portions wherein the first terminal portion is positioned relatively on the inner side, and the first terminal portion is positioned relatively on the outer side.
  • the long outer periphery lead portions and the short outer periphery lead portions are alternately arranged, and surround the die pad in a region between the outer periphery lead portion and the die pad on the back surface of the sealing resin.
  • a semiconductor device is characterized in that a recess is formed.
  • the present invention is a semiconductor device, and is disposed around a die pad, a plurality of outer peripheral lead portions each including a first terminal portion, and between the die pad and the outer peripheral lead portion. And a plurality of second terminal portions separated from the outer periphery lead portion, a semiconductor element mounted on the die pad, and electrically connecting the semiconductor element and each outer periphery lead portion; and A sealing member that seals the connection member that electrically connects the second terminal portion, the die pad, the plurality of outer peripheral lead portions, the plurality of second terminal portions, the semiconductor element, and the connection member.
  • a plurality of outer peripheral lead portions wherein the first terminal portion is positioned relatively on the inner side, and the first terminal portion is positioned relatively on the outer side.
  • the long outer periphery lead portions and the short outer periphery lead portions are alternately arranged, and a recess is formed in a region between the outer periphery lead portion and the die pad on the back surface of the sealing resin.
  • the present invention provides a method of manufacturing a lead frame, comprising: preparing a metal substrate; and etching the metal substrate to provide the metal substrate with the die pad, the outer peripheral lead portion, the connection ring, and the inner lead portion. And a step of forming the lead frame.
  • the present invention provides a method of manufacturing a semiconductor device, wherein a step of preparing a lead frame, a step of mounting the semiconductor element on the die pad of the lead frame, and the semiconductor element and each outer peripheral lead portion are electrically connected by a connecting member. Connecting the die ring, the plurality of outer peripheral lead portions, the semiconductor element, and the connecting member with a sealing resin, and connecting the connection ring from the back side of the lead frame. And a step of individually separating the plurality of second terminal portions by removing at least part of the semiconductor device.
  • the present invention provides a method of manufacturing a lead frame, comprising: preparing a metal substrate; and etching the metal substrate to form the die pad, the outer peripheral lead portion, the lead connection portion, and the inner lead portion on the metal substrate. And a step of forming a lead frame.
  • the present invention provides a method of manufacturing a semiconductor device, wherein a step of preparing a lead frame, a step of mounting the semiconductor element on the die pad of the lead frame, and the semiconductor element and each outer peripheral lead portion are electrically connected by a connecting member. Connecting the die pad, the plurality of outer peripheral lead portions, the semiconductor element, and the connection member with a sealing resin, and the lead connection portion from the back side of the lead frame. And a step of individually separating the plurality of second terminal portions by removing at least a part of the semiconductor device.
  • the number of terminal portions (number of pins) connected to the outside can be increased.
  • the present invention is a lead frame including a plurality of unit lead frames connected to each other via a support member, and each unit lead frame is provided around a die pad on which a semiconductor element is mounted, the die pad, and a terminal. And a plurality of lead portions including an inner lead extending inward from the terminal portion, the lead portion is supported by the support member provided between the adjacent unit lead frames, and the lead frame is It is made of a metal material having a tensile strength of 850 MPa to 1100 MPa, and among the lead portions of each unit lead frame, a portion in the vicinity of the support member has a width of 75 ⁇ m to 90 ⁇ m and a thickness of 60 ⁇ m to 75 ⁇ m. This is a featured lead frame.
  • the present invention is the lead frame characterized in that the terminal portions of the plurality of lead portions are alternately arranged in a staggered manner when viewed from the plane so as to be located inside and outside between the adjacent lead portions. is there.
  • the present invention is the lead frame characterized in that the inner lead is thinner than the terminal portion.
  • the present invention is the lead frame characterized in that the lead portion includes a connection lead extending outward from the terminal portion, and the connection lead is thinner than the terminal portion.
  • the present invention is the lead frame characterized in that, of the inner leads of the lead part, the vicinity of the terminal part has a width of 75 ⁇ m to 90 ⁇ m and a thickness of 60 ⁇ m to 75 ⁇ m.
  • the metal material is a Corson alloy (Cu—Ni—Si), a nickel tin copper alloy (Cu—Ni—Sn), or a titanium copper alloy (Cu—Ti). It is.
  • the present invention is a lead frame including a plurality of unit lead frames connected to each other via a support member, and each unit lead frame is provided around a die pad on which a semiconductor element is mounted, the die pad, and a terminal. And a plurality of lead portions including an inner lead extending inward from the terminal portion, the lead portion is supported by the support member provided between the adjacent unit lead frames, and the lead frame is It is made of a metal material having a tensile strength of 750 MPa to 1100 MPa, and among the lead parts of each unit lead frame, the vicinity of the support member has a width of 60 ⁇ m to 90 ⁇ m and a thickness of 50 ⁇ m to 75 ⁇ m. This is a featured lead frame.
  • the present invention is a semiconductor device manufactured using a lead frame, and includes a plurality of the die pads and the inner leads provided around the die pads and extending inward from the terminal portions, respectively.
  • a semiconductor device comprising an element and a sealing resin that seals the connection member.
  • the present invention includes a plurality of unit lead frames connected to each other via a support member, and each unit lead frame is provided around a die pad on which a semiconductor element is mounted, and the terminal portion and the terminal portion, respectively.
  • a method of manufacturing a lead frame comprising a plurality of lead portions including an inner lead extending inward from a metal substrate, the step of preparing a metal substrate made of a metal material having a tensile strength of 850 MPa to 1100 MPa; Forming the die pad and the lead portion on the metal substrate by etching, and when forming the die pad and the lead portion on the metal substrate, of the lead portions of each unit lead frame In the vicinity of the support member, the width is 75 ⁇ m to 90 ⁇ m and the thickness is 60 ⁇ m. Is a manufacturing method of a lead frame, characterized in that the 75 [mu] m.
  • the present invention includes a plurality of unit lead frames connected to each other via a support member, and each unit lead frame is provided around a die pad on which a semiconductor element is mounted, and the terminal portion and the terminal portion, respectively.
  • a method of manufacturing a lead frame comprising a plurality of lead portions including an inner lead extending inwardly from a metal substrate, the step of preparing a metal substrate made of a metal material having a tensile strength of 750 MPa to 1100 MPa; Forming the die pad and the lead portion on the metal substrate by etching, and when forming the die pad and the lead portion on the metal substrate, of the lead portions of each unit lead frame
  • the vicinity of the support member has a width of 60 ⁇ m to 90 ⁇ m and a thickness of 50 ⁇ m. Is a manufacturing method of a lead frame, characterized in that the 75 [mu] m.
  • the present invention relates to a method of manufacturing a semiconductor device, the step of manufacturing a lead frame by a method of manufacturing a lead frame, the step of mounting the semiconductor element on the die pad of the lead frame, the semiconductor element and each lead portion A step of electrically connecting the inner lead with a connecting member; and a step of sealing the die pad, the plurality of lead portions, the semiconductor element, and the connecting member with a sealing resin.
  • a method for manufacturing a semiconductor device the step of manufacturing a lead frame by a method of manufacturing a lead frame, the step of mounting the semiconductor element on the die pad of the lead frame, the semiconductor element and each lead portion
  • a step of electrically connecting the inner lead with a connecting member and a step of sealing the die pad, the plurality of lead portions, the semiconductor element, and the connecting member with a sealing resin.
  • the strength of the lead portion is suppressed from being lowered, it is possible to prevent the lead portion from being deformed and to narrow the interval between the adjacent lead portions.
  • the present invention is a lead frame for a semiconductor device, comprising a die pad on which a semiconductor element is mounted, and an inner lead provided around the die pad and extending inward from the first terminal portion, respectively.
  • the connection ring is supported by at least one of the inner leads, and a recess is regularly formed along the connection ring.
  • the lead frame is characterized in that a thick portion is formed between the recesses.
  • deformation of the inner lead can be prevented and the number of terminal portions (number of pins) connected to the outside can be increased.
  • FIG. 1 is a plan view showing a lead frame according to a first embodiment of the present invention.
  • FIG. 2 is a bottom view showing the lead frame according to the first embodiment of the present invention.
  • 3A is a cross-sectional view (a cross-sectional view taken along the line IIIA-IIIA in FIG. 1) of the lead frame according to the first embodiment of the present invention, and
  • FIG. 3B is a cross-sectional view of the first embodiment of the present invention. Sectional drawing which shows the lead frame by a form (IIIB-IIIB sectional view taken on the line of FIG. 1).
  • FIG. 4 is a plan view showing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 4 is a plan view showing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 5 is a sectional view showing the semiconductor device according to the first embodiment of the present invention (a sectional view taken along line VV in FIG. 4).
  • 6 (a) to 6 (f) are cross-sectional views showing a lead frame manufacturing method according to the first embodiment of the present invention.
  • 7A to 7F are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 8 is a plan view showing a lead frame according to the second embodiment of the present invention.
  • FIG. 9 is a bottom view showing a lead frame according to a second embodiment of the present invention.
  • 10A is a cross-sectional view (cross-sectional view taken along the line XA-XA in FIG.
  • FIG. 10B is a cross-sectional view of the second embodiment of the present invention.
  • Sectional drawing which shows the lead frame by form (XB-XB sectional view taken on the line of FIG. 8).
  • FIG. 11 is a plan view showing a semiconductor device according to the second embodiment of the present invention.
  • FIG. 12 is a plan view showing a lead frame according to the third embodiment of the present invention.
  • FIG. 13 is a bottom view showing a lead frame according to a third embodiment of the present invention.
  • 14A is a cross-sectional view (cross-sectional view taken along the line XIVA-XIVA in FIG. 12) of the lead frame according to the third embodiment of the present invention, and FIG.
  • FIG. 14B is a cross-sectional view of the third embodiment of the present invention. Sectional drawing which shows the lead frame by a form (XIVB-XIVB sectional view taken on the line of FIG. 12).
  • FIG. 15 is a plan view showing a semiconductor device according to the third embodiment of the present invention.
  • FIG. 16 is a sectional view showing a semiconductor device according to the third embodiment of the present invention (cross-sectional view taken along line XVI-XVI in FIG. 15).
  • FIG. 17 is a plan view showing a lead frame according to a modification of the third embodiment of the present invention.
  • FIG. 18 is a plan view showing a lead frame according to the fourth embodiment of the present invention.
  • FIG. 19 is a bottom view showing a lead frame according to the fourth embodiment of the present invention.
  • FIG. 20 is a plan view showing a semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 21 is a plan view showing a lead frame according to a modification of the fourth embodiment of the present invention.
  • FIG. 22 is a plan view showing a lead frame according to the fifth embodiment of the present invention.
  • 23 is a cross-sectional view showing a lead frame according to the fifth embodiment of the present invention (cross-sectional view taken along line XXIII-XXIII in FIG. 22).
  • FIG. 24 is an enlarged plan view showing a lead frame according to the fifth embodiment of the present invention (partial enlarged view of FIG. 22).
  • FIG. 25 (a)-(b) are cross-sectional views of the lead portion (cross-sectional views taken along the line XXVA-XXVA and XXVB-XXVB in FIG. 24, respectively).
  • 26A to 26C are cross-sectional views of the lead portion (cross-sectional view taken along line XXVIA-XXVIA, cross-sectional view taken along line XXVIB-XXVIB, and cross-sectional view taken along line XXVIC-XXVIC in FIG. 24).
  • FIG. 27 is a plan view showing a semiconductor device according to the fifth embodiment of the present invention.
  • FIG. 28 is a sectional view showing a semiconductor device according to the fifth embodiment of the present invention (cross-sectional view taken along line XXVIII-XXVIII in FIG. 27).
  • 29 (a)-(f) are cross-sectional views showing a method for manufacturing a lead frame according to a fifth embodiment of the present invention.
  • 30 (a) to 30 (e) are cross-sectional views showing a method of manufacturing a semiconductor device according to the fifth embodiment of the present invention.
  • FIG. 31 is a plan view showing a lead frame according to a sixth embodiment of the present invention.
  • FIG. 32A is a cross-sectional view (cross-sectional view taken along the line XXXIIA-XXXIIA in FIG.
  • FIG. 31 showing a lead frame according to the sixth embodiment of the present invention
  • FIG. 32B is a cross-sectional view of the sixth embodiment of the present invention.
  • Sectional drawing which shows the lead frame by form (XXXIIB-XXXIIB sectional view taken on the line of FIG. 31).
  • FIG. 33 is a plan view showing a semiconductor device according to a sixth embodiment of the present invention.
  • FIG. 34 is a plan view showing a semiconductor device according to a modification of the sixth embodiment of the present invention.
  • FIG. 1 is a plan view showing a lead frame according to this embodiment
  • FIG. 2 is a bottom view showing the lead frame according to this embodiment
  • 3A and 3B are cross-sectional views showing the lead frame according to the present embodiment, respectively.
  • the lead frame 10 is provided around a die pad 11 on which a semiconductor element 21 (described later) is mounted, and connects the semiconductor element 21 and an external circuit (not shown).
  • a plurality of elongated outer peripheral lead portions 12A and 12B and a connection ring 14 provided between the die pad 11 and the outer peripheral lead portions 12A and 12B are provided.
  • a plurality of inner lead portions 26A to 26D each having the second terminal portion 18 are supported by the connection ring 14.
  • the lead frame 10 includes a plurality of unit lead frames 10a, each of which corresponds to a semiconductor device 20 (described later).
  • the unit lead frame 10a is an area located inside the virtual line in FIG.
  • the plurality of unit lead frames 10 a are connected to each other via support leads (support members) 13.
  • the support leads 13 support the die pad 11, the outer peripheral lead portions 12A and 12B, and the connection ring 14, and extend in the X direction and the Y direction perpendicular to the X direction.
  • the die pad 11 has a substantially rectangular plane shape, and its four sides extend along either the X direction or the Y direction. Further, suspension leads 16 are connected to the four corners of the die pad 11. The die pad 11 is connected and supported to the support lead 13 through the four suspension leads 16.
  • the plurality of outer peripheral lead portions 12A and 12B are provided along the outer periphery of each unit lead frame 10a, and include a relatively long long outer peripheral lead portion 12A and a relatively short short outer peripheral lead portion 12B. It is out.
  • the long outer periphery lead portion 12A and the short outer periphery lead portion 12B are collectively referred to as outer periphery lead portions 12A and 12B.
  • the configuration of the outer peripheral lead portions 12A and 12B will be further described.
  • each of the outer peripheral lead portions 12A and 12B has a connection lead 52 and a first terminal portion 53, respectively.
  • the 1st terminal part 53 has the internal terminal 15A on the surface.
  • the internal terminal 15A is a region that is electrically connected to the semiconductor element 21 via a bonding wire 22 as will be described later. For this reason, the plating part 25 which improves adhesiveness with the bonding wire 22 is provided on the internal terminal 15A.
  • the connection lead 52 is located on the outer side (support lead 13 side) than the first terminal portion 53, and the base end portion thereof is coupled to the support lead 13.
  • the connection lead 52 extends perpendicular to the support lead 13 to which the connection lead 52 is coupled.
  • connection leads 52 of the outer peripheral lead portions 12A and 12B are formed thin by half etching from the back surface side (opposite the surface on which the semiconductor element 21 is mounted). ing.
  • the first terminal portion 53 has the same thickness as the die pad 11 and the support lead 13 without being half-etched.
  • Half-etching means that the material to be etched is etched halfway in the thickness direction.
  • External terminals 17A and 17B that are electrically connected to external mounting boards are formed on the back surfaces of the first terminal portions 53 of the outer peripheral lead portions 12A and 12B, respectively.
  • the external terminals 17A and 17B are exposed outward from the semiconductor device 20 after the semiconductor device 20 (described later) is manufactured.
  • the first terminal portion 53 of the long outer periphery lead portion 12A is located relatively inside (on the die pad 11 side), and the first terminal portion 53 of the short outer periphery lead portion 12B is It is located relatively outside (support lead 13 side).
  • the external terminals 17A and 17B of the outer peripheral lead portions 12A and 12B are alternately arranged in a staggered manner when viewed from the plane so as to be located inside and outside between the adjacent outer peripheral lead portions 12A and 12B. That is, in the periphery of the die pad 11, the outer peripheral lead portion 12 ⁇ / b> A having the external terminal (inner external terminal) 17 ⁇ / b> A positioned relatively inside (die pad 11 side) and relatively outside (support lead 13 side). Short outer peripheral lead portions 12B having external terminals (outside external terminals) 17B are alternately arranged along each side of the support lead 13.
  • the external terminal 17A and the external terminal 17B all have the same planar shape.
  • the plurality of external terminals 17A are all arranged along a straight line parallel to one side of the die pad 11 when viewed from above.
  • the plurality of external terminals 17B are all arranged along a straight line parallel to one side of the die pad 11 when viewed from the plane. That is, the plurality of external terminals 17A and 17B are arranged in two rows along a straight line parallel to either the X direction or the Y direction.
  • the interval between the outer peripheral lead portions 12A and 12B adjacent to each other is preferably 90 ⁇ m to 150 ⁇ m.
  • the through portion between the adjacent outer peripheral lead portions 12A and 12B can be reliably formed by etching.
  • the number of external terminals 17A and 17B (number of pins) of each semiconductor device 20 can be secured at a certain number or more.
  • connection ring 14 and the inner lead portions 26A to 26D will be described.
  • connection ring 14 is disposed so as to surround the die pad 11 on the distal end side of the outer peripheral lead portions 12A and 12B.
  • the connection ring 14 has a substantially rectangular shape as a whole, and each side thereof extends along the X direction or the Y direction.
  • Suspension leads 16 are coupled to the four corners of the connection ring 14, and the connection ring 14 is supported by the support leads 13 via the four suspension leads 16.
  • a concave groove 14 a is formed on the surface of the connection ring 14 along the longitudinal direction of the connection ring 14.
  • the concave groove 14a is formed by half etching, and has a certain depth without penetrating in the thickness direction. Further, the concave groove 14a is formed at a substantially central portion in the width direction of the connection ring 14, and bank portions 14b that are not half-etched are formed on both sides in the width direction of the concave groove 14a.
  • the cross section perpendicular to the longitudinal direction of the connection ring 14 is substantially concave or U-shaped.
  • the concave grooves 14a are provided on the entire circumference except for the four corners of the connection ring 14.
  • connection ring 14 may be provided on the entire circumference including the four corners of the connection ring 14, for example. good.
  • the concave groove 14 is not provided in the connection ring 14, and the whole connection ring 14 may be in the state with the plate
  • connection ring 14 Since the volume of the connection ring 14 is reduced by providing the concave groove 14a in this manner, the connection ring 14 can be easily removed by etching when the plurality of second terminal portions 18 are individually separated, as will be described later. It has become.
  • a plurality of inner lead portions 26A to 26D extend from the connection ring 14, respectively.
  • the plurality of inner lead portions 26A to 26D include relatively long long inner lead portions 26A and 26C and relatively short short inner lead portions 26B and 26D.
  • the long inner lead portions 26A and 26C and the short inner lead portions 26B and 26D are collectively referred to as inner lead portions 26A to 26D.
  • Each inner lead portion 26A to 26D has a second terminal portion 18 at the tip thereof.
  • the second terminal portion 18 is connected to the semiconductor element 21 via a bonding wire 22 as will be described later.
  • the plurality of second terminal portions 18 are arranged along the connection ring 14 at intervals, and are connected and supported by the connection ring 14 respectively. As will be described later, the second terminal portions 18 are separated from each other after the connection ring 14 is removed when the semiconductor device 20 is manufactured. That is, each second terminal portion 18 is separated from any of the die pad 11, the connection ring 14, and the other second terminal portions 18 after removing the connection ring 14.
  • the second terminal portions 18 of the long inner lead portions 26A and 26C are located in a portion relatively separated from the connection ring 14, and the short inner lead portions 26B and 26D.
  • the second terminal portion 18 is located in a portion relatively close to the connection ring 14.
  • the longer inner lead portion 26A and the shorter inner lead portion 26B each extend from the outer side of the connection ring 14 (the support lead 13 side).
  • the long inner lead portions 26 ⁇ / b> A and the short inner lead portions 26 ⁇ / b> B are alternately arranged outside the connection ring 14.
  • the long inner lead portion 26C and the short inner lead portion 26D extend from the inner side (die pad 11 side) of the connection ring 14, respectively.
  • These long inner lead portions 26 ⁇ / b> C and short inner lead portions 26 ⁇ / b> D are alternately arranged inside the connection ring 14.
  • each of the inner lead portions 26A to 26D has a connection lead 57 coupled to the connection ring 14, and each connection lead 57 is thinned from the back side. .
  • the sealing resin 23 enters from the back side toward the connection leads 57 after sealing with the sealing resin 23 ( (See FIG. 5).
  • Each second terminal portion 18 has an internal terminal 15B provided on the front surface side and external terminals 17C to 17F provided on the back surface side.
  • the internal terminal 15 ⁇ / b> B is electrically connected to the semiconductor element 21 through the bonding wire 22.
  • the plating part 25 for improving adhesiveness with the bonding wire 22 is provided on the internal terminal 15B like the internal terminal 15A.
  • the external terminals 17C to 17F are electrically connected to an external mounting board (not shown), and are provided at the tips of the inner lead portions 26A to 26D, respectively.
  • the external terminals 17C and 17D of the inner lead portions 26A and 26B located on the outer side (support lead 13 side) of the connection ring 14 are located on the inner and outer sides between the adjacent inner lead portions 26A and 26B. Thus, they are alternately arranged in a staggered manner when viewed from above. That is, in the periphery of the die pad 11, the external terminal 17 ⁇ / b> D positioned relatively on the inner side (die pad 11 side) and the external terminal 17 ⁇ / b> C positioned relatively on the outer side (support lead 13 side) are connected to each side of the connection ring 14. Are arranged alternately. Thereby, even when the inner lead portions 26A and 26B are provided close to each other, a problem that the external terminals 17C and 17D come into contact with each other is prevented.
  • the external terminals 17E and 17F of the inner lead portions 26C and 26D located on the inner side (die pad 11 side) of the connection ring 14 are arranged so as to be located on the inner side and the outer side between the adjacent inner lead portions 26C and 26D. It is arranged in a staggered pattern alternately. That is, around the die pad 11, the external terminals 17 ⁇ / b> E positioned relatively on the inner side (die pad 11 side) and the external terminals 17 ⁇ / b> F positioned relatively on the outer side (support lead 13 side) are connected to each side of the connection ring 14. Are arranged alternately. Thereby, even when the inner lead portions 26C and 26D are provided close to each other, a problem that the external terminals 17E and 17F come into contact with each other is prevented.
  • the plurality of external terminals 17C to 17F described above are all arranged along a straight line parallel to one side of the die pad 11 when viewed from above. That is, the plurality of external terminals 17C to 17F are arranged in four rows along a straight line parallel to either the X direction or the Y direction.
  • the lead frame 10 described above is made of a metal such as copper, copper alloy, 42 alloy (Ni 42% Fe alloy) as a whole.
  • the lead frame 10 may have a thickness of 80 ⁇ m to 250 ⁇ m, although it depends on the configuration of the semiconductor device 20 to be manufactured.
  • the lead frame 10 is preferably made of a metal material having a tensile strength of 750 Mpa to 1100 Mpa.
  • the lead portions 12A, 12B, and 26A to 26D need to be made thinner than the conventional one, but this should be made from the metal as described above. Thus, it is possible to obtain the lead frame 10 having the lead portions 12A, 12B, and 26A to 26D that are thin and hardly deformed.
  • the outer peripheral lead portions 12A and 12B and the inner lead portions 26A to 26D are arranged along all four sides of the die pad 11, but the present invention is not limited to this. It may be arranged along only two sides.
  • the inner lead portions 26A to 26D extend from both the outer side (support lead 13 side) and the inner side (die pad 11 side) of the connection ring 14.
  • the present invention is not limited to this. You may extend only from one side inside.
  • FIGS. 4 and 5 are diagrams showing a semiconductor device (DR-QFN (Dual Row QFN) type) according to the present embodiment.
  • the semiconductor device (semiconductor package) 20 includes a die pad 11, a plurality of outer peripheral lead portions 12A and 12B arranged around the die pad 11, and the die pad 11 and the outer peripheral lead portions 12A and 12B. And a plurality of second terminal portions 18 disposed between them.
  • the semiconductor element 21 is mounted on the die pad 11, and the semiconductor element 21, the first terminal portion 53 of each of the outer peripheral lead portions 12A and 12B, and the second terminal portion 18 of each of the inner lead portions 26A to 26D are each bonded to a bonding wire.
  • (Connecting member) 22 is electrically connected.
  • the die pad 11, the outer peripheral lead portions 12 ⁇ / b> A and 12 ⁇ / b> B, the second terminal portion 18, the semiconductor element 21, and the bonding wire 22 are resin-sealed with a sealing resin 23.
  • the die pad 11, the outer peripheral lead portions 12A and 12B, and the inner lead portions 26A to 26D are manufactured from the lead frame 10 described above.
  • the configurations of the die pad 11, the outer periphery lead portions 12A and 12B, and the inner lead portions 26A to 26D are substantially the same as those shown in FIGS. 1 to 3 except for the region not included in the unit lead frame 10a. Then, detailed description is abbreviate
  • connection ring 14 described above is resin-sealed with a sealing resin 23 and then removed from the back side by etching. Therefore, as shown in FIGS. 4 and 5, the second terminal portions 18 of the inner lead portions 26A to 26D are separated from the die pad 11, the outer peripheral lead portions 12A and 12B, and the other second terminal portions 18. Electrically independent of these members.
  • a recess 27 is formed in a region between 26C and 26D.
  • the recess 27 substantially corresponds to the shape of the connection ring 14 and has a planar rectangular shape so as to surround the die pad 11.
  • the protrusion part 27a which consists of a part of sealing resin 23 protrudes (refer FIG. 5).
  • the protrusion 27a has a shape corresponding to the concave groove 14a of the connection ring 14 described above.
  • the recess 27 may be filled with the same or different type of insulating resin as the sealing resin 23.
  • the semiconductor element 21 various semiconductor elements generally used in the past can be used, and are not particularly limited.
  • an integrated circuit, a large-scale integrated circuit, a transistor, a thyristor, a diode, or the like is used. it can.
  • the semiconductor element 21 has a plurality of electrodes 21a to which bonding wires 22 are attached.
  • the semiconductor element 21 is fixed to the surface of the die pad 11 with an adhesive 24 such as a die bonding paste.
  • Each bonding wire 22 is made of a material having good conductivity such as gold or copper.
  • Each bonding wire 22 has one end connected to the electrode 21a of the semiconductor element 21 and the other end connected to the internal terminal 15A of each of the outer peripheral lead portions 12A and 12B or the internal terminal 15B of the second terminal portion 18. ing.
  • the internal terminals 15 ⁇ / b> A and 15 ⁇ / b> B are each provided with a plating portion 25 that improves the adhesion with the bonding wire 22.
  • the sealing resin 23 a thermosetting resin such as a silicone resin or an epoxy resin, or a thermoplastic resin such as a PPS resin can be used.
  • the total thickness of the sealing resin 23 can be about 500 ⁇ m to 1000 ⁇ m.
  • the display of the sealing resin 23 located on the surface side of the die pad 11, the outer peripheral lead portions 12A and 12B, and the inner lead portions 26A to 26D is omitted.
  • one side of the semiconductor device 20 may be, for example, 8 mm to 16 mm.
  • FIGS. 6A to 6F are cross-sectional views (a diagram corresponding to FIG. 3B) showing a method for manufacturing the lead frame 10.
  • FIG. 6A to 6F are cross-sectional views (a diagram corresponding to FIG. 3B) showing a method for manufacturing the lead frame 10.
  • a flat metal substrate 31 is prepared.
  • a substrate made of a metal such as copper, a copper alloy, or a 42 alloy (Ni 42% Fe alloy) can be used.
  • photosensitive resists 32a and 33a are applied to the entire front and back surfaces of the metal substrate 31, respectively, and dried (FIG. 6B).
  • photosensitive resists 32a and 33a conventionally known resists can be used.
  • the metal substrate 31 is exposed through a photomask and developed to form etching resist layers 32 and 33 having desired openings 32b and 33b (FIG. 6C).
  • etching is performed on the metal substrate 31 with a corrosive solution using the etching resist layers 32 and 33 as corrosion resistant films (FIG. 6D).
  • the corrosive liquid can be appropriately selected according to the material of the metal substrate 31 to be used. For example, when a copper alloy is used as the metal substrate 31, a ferric chloride aqueous solution is usually used from both sides of the metal substrate 31. It can be performed by spray etching.
  • the spray etching is performed from both sides of the metal substrate 31 .
  • the present invention is not limited to this.
  • two stages of spray etching may be performed for each side of the metal substrate 31. Specifically, first, resist layers 32 and 33 for etching having a predetermined pattern are formed (see FIG. 6C), and then an etching-resistant sealing layer (not shown) is formed on the back side of the metal substrate 31. In this state, only the surface side of the metal substrate 31 is etched. Next, the sealing layer on the back side is peeled off, and a sealing layer (not shown) is provided on the front side of the metal substrate 31.
  • the sealing layer on the surface side also enters the recess on the surface side of the etched metal substrate 31. Subsequently, by etching only the exposed back surface of the metal substrate 31, and then peeling off the sealing layer on the front surface side, the die pad 11, the plurality of outer peripheral lead portions 12A and 12B, the connection ring 14, and the plurality of inner lead portions. 26A to 26D are formed. By performing spray etching on each side of the metal substrate 31 in this way, it is possible to easily avoid the deformation of the outer peripheral lead portions 12A and 12B and the inner lead portions 26A to 26D.
  • the internal terminals 15A and 15B are respectively plated to form the plated portions 25 (FIG. 6F).
  • the type of plating selected is not limited as long as the adhesion to the bonding wire 22 can be ensured.
  • single-layer plating such as Ag or Au may be used, or Ni / Pd or Ni / Pd / Au may be used.
  • Multi-layer plating laminated in this order may be used.
  • the plating portion 25 may be provided only on the connection portion with the bonding wire 22 among the outer peripheral lead portions 12A and 12B and the inner lead portions 26A to 26D, or may be provided on the entire surface of the lead frame 10.
  • FIGS. 7A to 7F are cross-sectional views (corresponding to FIG. 5) showing the method for manufacturing the semiconductor device 20.
  • the lead frame 10 is manufactured by the method shown in FIGS. 6A to 6F (described above).
  • the semiconductor element 21 is mounted on the die pad 11 of the lead frame 10.
  • the semiconductor element 21 is mounted on the die pad 11 and fixed using an adhesive 24 such as a die bonding paste (FIG. 7A).
  • the electrodes 21a of the semiconductor element 21 and the plating portions 25 (internal terminals 15A) of the outer peripheral lead portions 12A and 12B are electrically connected to each other by bonding wires (connection members) 22, respectively.
  • the electrodes 21a of the semiconductor element 21 and the plating portions 25 (internal terminals 15B) of the inner lead portions 26A to 26D are electrically connected to each other by bonding wires (connection members) 22 (wire bonding step). (FIG. 7B).
  • the lead frame 10 is placed on the heat block 36 of the wire bonding apparatus.
  • the outer circumferential lead portions 12A and 12B and the inner lead portions 26A to 26D are heated from the back side thereof by the heat block 36.
  • the electrodes 21a of the semiconductor element 21 and the plating portions of the outer peripheral lead portions 12A and 12B and the inner lead portions 26A to 26D. 25 are electrically connected to each other using bonding wires 22.
  • a sealing resin 23 is formed by injection molding or transfer molding of a thermosetting resin or a thermoplastic resin to the lead frame 10 (FIG. 7C).
  • the die pad 11, the plurality of outer peripheral lead portions 12A and 12B, the plurality of inner lead portions 26A to 26D, the semiconductor element 21, and the bonding wire 22 are sealed with resin.
  • an etching resist layer 34 having a predetermined opening 34a is provided on the back surface of the lead frame 10 and the sealing resin 23 (FIG. 7D).
  • a photosensitive resist is applied to the entire back surface of the lead frame 10 and the sealing resin 23, respectively. Subsequently, the photosensitive resist is exposed through a photomask and developed to form an etching resist layer 34 having a desired opening 34a.
  • the etching resist layer 34 covers the entire back surface of the lead frame 10 and the sealing resin 23 except for the opening 34a.
  • the opening 34a has a substantially rectangular band shape substantially corresponding to the position of the connection ring 14, and the back surface (metal part) of the connection ring 14 is exposed from the opening 34a.
  • a known dry film resist can be used as the etching resist layer 34.
  • the lead frame 10 is etched with a corrosive solution using the etching resist layer 34 as a corrosion-resistant film (FIG. 7E).
  • the corrosive liquid entering from the opening 34 a dissolves and removes the entire connection ring 14.
  • a part of the connection lead 57 of the inner lead portions 26A to 26D may be removed together with the connection ring 14.
  • the concave groove 14a is provided on the surface of the connection ring 14
  • the corrosive liquid entering from the opening 34a does not dissolve the second terminal portion 18 and the outer circumferential lead portions 12A and 12B more than necessary.
  • the connection ring 14 can be removed appropriately.
  • connection ring 14 is removed, and the inner lead portions 26A to 26D are separated from each other.
  • the second terminal portions 18 are individually separated and are electrically independent from the die pad 11, the outer peripheral lead portions 12 ⁇ / b> A and 12 ⁇ / b> B, and the other second terminal portions 18.
  • the corrosion liquid can use the ferric chloride aqueous solution, for example similarly to the above (refer FIG.6 (d)).
  • the etching resist layer 34 is peeled off and removed. Thereafter, the lead frame 10 and the sealing resin 23 between the semiconductor elements 21 are diced to separate the lead frame 10 for each unit lead frame 10a (see FIG. 1). At this time, the lead frame 10 and the sealing resin 23 between the unit lead frames 10a may be cut while rotating a blade (not shown) made of, for example, a diamond grindstone. Note that after removing the etching resist layer 34, a step of filling the recess 27 with the same or different type of insulating resin as the sealing resin 23 may be provided.
  • the long outer periphery lead portion 12A in which the first terminal portion 53 is positioned relatively inside, and the short outer periphery lead portion 12B in which the first terminal portion 53 is positioned relatively outside Are arranged alternately.
  • interval of outer periphery lead part 12A, 12B can be narrowed and the number can be increased, the number of the 1st terminal parts 53 can be increased.
  • the semiconductor device 20 when the semiconductor device 20 is manufactured, the plurality of second terminal portions 18 are individually separated by removing the connection ring 14. Therefore, in addition to the first terminal portion 53 of the outer peripheral lead portions 12A and 12B, the second terminal portion 18 of the inner lead portions 26A to 26D can be used, and the number of terminal portions (pins) connected to an external mounting board Number) can be further increased. Thereby, high density of the semiconductor device 20 can be realized.
  • the long inner lead portions 26A and 26C that are positioned in a portion where the second terminal portion 18 is relatively separated from the connection ring 14 and the second terminal portion 18 are relatively connected to the connection ring 14.
  • the short inner lead portions 26B and 26D located in the vicinity of the connection ring 14 are alternately arranged along the connection ring 14.
  • the plurality of inner lead portions 26A to 26D extend from both the inner side and the outer side of the connection ring 14. As a result, the interval between the inner lead portions 26A to 26D can be reduced and the number of the inner lead portions 26A to 26D can be increased, so that the number of second terminal portions 18 can be increased.
  • connection ring 14 is removed by etching
  • the present invention is not limited to this.
  • only a part of the connection ring 14 may be removed by etching, and a part of the connection ring 14 that has not been removed may be left in the semiconductor device 20.
  • the external terminals 17C and 17D of the inner lead portions 26A and 26B are adjacent to the inner lead portions 26A and 26B (the inner lead portions 26C and 26C).
  • 26D an example has been described in which they are alternately arranged in two rows in a staggered manner as viewed from the plane so as to be located inside and outside.
  • the present invention is not limited thereto, and the external terminals 17C and 17D of the inner lead portions 26A and 26B (the external terminals 17E and 17F of the inner lead portions 26C and 26D) are aligned along each side of the connection ring 14. Also good.
  • FIGS. 8 to 11 are views showing a second embodiment of the present invention.
  • the second embodiment shown in FIGS. 8 to 11 instead of providing the inner leads 26 ⁇ / b> A to 26 ⁇ / b> D having the second terminal portions in the connection ring 14, a part of the connection ring 14 is separately separated and the second embodiment is provided.
  • the point which becomes the terminal part 28 is different, and the other structure is substantially the same as the first embodiment described above. 8 to 11, the same parts as those of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
  • each recess 14c is formed by half etching, and has a certain depth without penetrating in the thickness direction.
  • Each concave portion 14 c is formed at a substantially central portion in the width direction of the connection ring 14.
  • a second terminal portion 28 is formed between the recesses 14c adjacent to each other. That is, the recesses 14 c and the second terminal portions 28 are alternately arranged along the length direction of the connection ring 14.
  • the second terminal portion 28 is not half-etched and has the same thickness as the die pad 11 and the support lead 13.
  • the plating part 25 which improves the adhesiveness with the bonding wire 22 is provided on the surface of each second terminal part 28.
  • connection ring 14 when the semiconductor device 20A (see FIG. 11) is manufactured, only a part of the connection ring 14 is removed by etching. Specifically, the peripheral area of each recess 14c in the connection ring 14 is removed. On the other hand, the part located between each recessed part 14c among the connection rings 14 is isolate
  • the openings 34a of the etching resist layer 34 are formed in the regions corresponding to the respective recesses 14c and the periphery thereof. Keep it. And the surrounding area
  • the concave portion 14c is provided on the surface of the connection ring 14, the corrosive liquid entering from the opening 34a can be connected without dissolving the second terminal portion 28 and the outer peripheral lead portions 12A and 12B more than necessary. Only the peripheral region of each recess 14c in the ring 14 can be appropriately removed. In this way, the second terminal portions 28 remain between the two recesses 14c adjacent to each other in the connection ring 14.
  • the recess 14c is formed at a position corresponding to the tip of the long outer periphery lead portion 12A, but is not limited thereto, and is formed at a position corresponding to the tip of the short outer periphery lead portion 12B. May be.
  • the several recessed part 14c is provided over the circumferential direction whole region of the connection ring 14, it is not restricted to this, You may provide in only one part of the connection ring 14. FIG.
  • a semiconductor device 20A shown in FIG. 11 is manufactured from the lead frame 10A shown in FIGS.
  • the second terminal portions 28 are arranged at intervals from each other along all four sides (four sides parallel to the X direction or the Y direction in FIG. 11) around the die pad 11. .
  • each second terminal portion 28 is separated from the die pad 11, the outer peripheral lead portions 12 ⁇ / b> A and 12 ⁇ / b> B, and the other second terminal portions 28, and is electrically independent from these members. ing. Further, the second terminal portion 28 is not half-etched and has the same thickness as the die pad 11. Furthermore, an external terminal 17 ⁇ / b> C that is electrically connected to an external mounting substrate (not shown) is formed on the back surface of the second terminal portion 28.
  • the die pad 11 is formed in the region between the outer peripheral lead portions 12A and 12B and the die pad 11 on the back surface of the sealing resin 23.
  • a recess 27 is formed so as to surround.
  • the semiconductor device 20A when the semiconductor device 20A is manufactured, a part of the connection ring 14 is removed, and the part of the connection ring 14 that is not removed is individually separated to become the second terminal portion 28.
  • the number of terminal portions (number of pins) connected to an external mounting substrate can be increased, and the density of the semiconductor device 20 can be further increased. Can be realized.
  • some of the second terminal portions 28 are formed larger than the other second terminal portions 28, and a plurality of bonding wires 22 are connected to the second terminal portions 28, thereby adjusting the electric signal. It may be used as a bus bar or ground (GND) terminal for the purpose. Thereby, the heat generation accompanying the increase in the number of terminals can be reduced, and the semiconductor device 20A with higher reliability can be obtained.
  • GND ground
  • the manufacturing method of the lead frame 10A and the manufacturing method of the semiconductor device 20A according to the present embodiment are the same as the manufacturing method of the lead frame 10 (FIGS. 6A to 6F) according to the first embodiment and the semiconductor device 20. This is substantially the same as the manufacturing method (FIGS. 7A to 7F).
  • FIGS. 12 to 17 are views showing a third embodiment of the present invention.
  • the third embodiment shown in FIGS. 12 to 17 mainly differs in the arrangement of the inner lead portions 26A to 26D and the point that the connection lead 57 is thinned from the surface side. This is substantially the same as the first embodiment described above. 12 to 17, the same parts as those in the first embodiment are denoted by the same reference numerals and detailed description thereof is omitted.
  • the long inner lead portion 26C extending from the inner side of the connection ring 14 among the plurality of inner lead portions 26A to 26D, and the connection ring Short inner lead portions 26 ⁇ / b> B extending from the outer side of 14 are arranged at positions opposite to each other via the connection ring 14. That is, the long inner lead portion 26 ⁇ / b> C and the corresponding short inner lead portion 26 ⁇ / b> B are positioned on a straight line across the connection ring 14.
  • a short inner lead portion 26D extending from the inside of the connection ring 14 and a long inner lead portion 26A extending from the outside of the connection ring 14 are arranged at positions opposite to each other via the connection ring 14. That is, the short inner lead portion 26 ⁇ / b> D and the corresponding long inner lead portion 26 ⁇ / b> A are positioned on a straight line across the connection ring 14. Thereby, the inter-terminal distance between the external terminal 17D and the external terminal 17F can be ensured, and the problem of contact between these terminals can be prevented.
  • connection ring 14 and the long outer peripheral lead portion 12A face each other
  • long inner lead portion 26A extending from the outer side of the connection ring 14 and the short outer peripheral lead portion 12B face each other. Yes.
  • connection leads 57 of the inner lead portions 26A to 26D are thinned from the surface side.
  • the connection lead 57 since the connection lead 57 is exposed on the back side, the operation of removing the connection lead 57 together with the connection ring 14 can be easily performed. Further, when the connection ring 14 is removed by etching (see FIG. 7E), it can be easily confirmed from the back side whether or not the connection ring 14 and the connection lead 57 have been reliably removed. This facilitates the work of making the external terminals 17C to 17F independent.
  • the connection lead 57 may be thinned from the surface side.
  • connection lead 57 is removed together with the connection ring 14.
  • the present invention is not limited to this, and a part of the connection lead 57 may be left in the semiconductor device 20B. The entire 57 may be left.
  • FIG. 17 shows a lead frame 10C according to a modification of the present embodiment.
  • the short inner lead portion 26 ⁇ / b> D extends from the inside of the connection ring 14, and the long inner lead portion 26 ⁇ / b> C does not extend.
  • the external terminals 17A to 17D and 17F are arranged in five rows around the die pad 11. In this case, a large area of the die pad 11 can be ensured with respect to the size of the semiconductor device 20B.
  • the long inner lead portion 26 ⁇ / b> C need not be provided inside the connection ring 14.
  • the manufacturing method of the lead frames 10B and 10C and the manufacturing method of the semiconductor device 20B according to the present embodiment are the same as those of the manufacturing method of the lead frame 10 according to the first embodiment (FIGS. 6A to 6F) and the semiconductor. This is substantially the same as the method for manufacturing the device 20 (FIGS. 7A to 7F).
  • all of the lead frame 10B shown in FIG. 12 (external terminals 17A to 17F have 6 rows) and the lead frame 10C shown in FIG. 17 (external terminals 17A to 17D, 17F have 5 rows)
  • the external terminals 17A to 17F can be arranged in a zigzag manner in which the intervals between the external terminals 17A to 17F are equal. As a result, it is possible to suppress the occurrence of solder bridges when the board is mounted, and it is possible to improve the mounting reliability.
  • the lead frame 10B shown in FIG. 12 increases the number of terminal portions (number of pins) to 308 pins. be able to.
  • the number of terminal portions (number of pins) can be increased to 280 pins.
  • a semiconductor device on which a high-performance LSI can be mounted can be manufactured at low cost.
  • the number of terminals is increased from 208 pins to 216 pins. Is possible.
  • the number of pins corresponds to the number of pins equivalent to the conventional 28 mm ⁇ QFP (Quad Flat Package).
  • FIGS. 18 to 21 are views showing a fourth embodiment of the present invention.
  • the fourth embodiment shown in FIGS. 18 to 21 is mainly different from the first embodiment in that a lead connection portion (connection bar) 64 is provided in place of the connection ring 14, and the other configuration is the first embodiment described above.
  • This is substantially the same as the embodiment. 18 to 21, the same parts as those of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
  • a lead connection portion 64 is disposed between the die pad 11 and the outer peripheral lead portions 12A and 12B.
  • the lead connecting portions 64 support a plurality of inner lead portions 26A to 26D each having the second terminal portion 18.
  • the lead connection portion 64 is not half-etched and has the same thickness as the die pad 11. However, the present invention is not limited to this, and the thickness may be reduced by half etching from the surface side of the lead connection portion 64.
  • the lead connection portion 64 extends linearly, and both ends thereof are coupled to the suspension lead 16.
  • the suspension lead 16 is thinned by half etching from the back side. Note that the lead connecting portion 64 does not necessarily have to be connected to the suspension lead 16, and may be connected to the die pad 11, for example.
  • the die pad 11 has a substantially rectangular plane shape, its long side is parallel to the X direction, and its short side is parallel to the Y direction.
  • two lead connection portions 64 are provided for each unit lead frame 10 a, and each extend parallel to the long side of the die pad 11.
  • the present invention is not limited to this, and one or three or more lead connection portions 64 may be provided per unit lead frame 10a.
  • the shape of the lead connecting portion 64 is not limited to a linear shape, and may be a curved shape such as a substantially arc, a substantially V shape, a substantially L shape, a substantially U shape, or the like.
  • a continuous part (for example, four) external terminals 17A are connected by the connecting part 65, and a continuous part (for example, three) external terminals 17E are connected by the connecting part 66.
  • the connecting portions 65 and 66 may be used as, for example, a bus bar or a ground (GND) terminal.
  • a semiconductor device 20D shown in FIG. 20 is manufactured from the lead frame 10D shown in FIGS.
  • the lead connection portion 64 is removed, and accordingly, the inner lead portion 26A, between the outer peripheral lead portions 12A and 12B and the die pad 11 on the back surface of the sealing resin 23.
  • a recess 67 is formed in a region between 26B and the inner lead portions 26C and 26D. Two recesses 67 are provided for each semiconductor device 20D, and each of the recesses 67 extends in a straight line parallel to the long side of the die pad 11 substantially corresponding to the shape of the lead connection portion 64.
  • the lead connection portion 64 extends along only two sides of the die pad 11, the area can be expanded by extending the die pad 11 in a direction where the lead connection portion 64 is not provided. it can. Thereby, it becomes easy to mount a large semiconductor element 21 or a plurality of semiconductor elements 21 on the die pad 11.
  • FIG. 21 shows a lead frame 10E according to a modification of the present embodiment.
  • the short inner lead portion 26D extends from the inside of each lead connection portion 64, and the long inner lead portion 26C does not extend.
  • the area of the die pad 11 can be expanded to each lead connection part 64 side.
  • the manufacturing method of the lead frames 10D and 10E and the manufacturing method of the semiconductor device 20D according to the present embodiment are the same as those of the manufacturing method of the lead frame 10 according to the first embodiment (FIGS. 6A to 6F) and the semiconductor. This is substantially the same as the method for manufacturing the device 20 (FIGS. 7A to 7F).
  • FIGS. 22 to 30 are views showing a fifth embodiment of the present invention. 22 to 30, the same reference numerals are given to the same parts, and a part of the detailed description may be omitted.
  • 22 to 26 are views showing a lead frame according to the present embodiment.
  • the lead frame 10F includes a plurality of unit lead frames 10a.
  • Each unit lead frame 10a is provided with a planar rectangular die pad 11 on which a semiconductor element 21 (described later) is mounted, and a plurality of elongated leads that are provided around the die pad 11 and connect the semiconductor element 21 and an external circuit (not shown). Parts 12A and 12B.
  • Each unit lead frame 10a is a region corresponding to a semiconductor device 20F (described later), and is a region located inside a virtual line in FIG.
  • the plurality of unit lead frames 10 a are connected to each other via support leads (support members) 13.
  • the support leads 13 support the die pad 11 and the lead portions 12A and 12B, and extend along the X direction and the Y direction perpendicular to the X direction.
  • suspension leads 16 are coupled to the four corners of the die pad 11, and the die pad 11 is coupled and supported to the support leads 13 through the four suspension leads 16.
  • Adjacent lead portions 12A and 12B are shaped to be electrically insulated from each other after manufacturing a semiconductor device 20F (described later). Each lead portion 12A, 12B is shaped to be electrically insulated from the die pad 11 after the semiconductor device 20F is manufactured. External terminals 17A and 17B that are electrically connected to external mounting boards (not shown) are formed on the back surfaces of the lead portions 12A and 12B, respectively. The external terminals 17A and 17B are exposed outward from the semiconductor device 20F after the manufacture of the semiconductor device 20F (described later).
  • the external terminals 17A and 17B of the plurality of lead portions 12A and 12B are alternately arranged in a staggered manner when viewed from the plane so as to be located inside and outside between the adjacent lead portions 12A and 12B. That is, around the die pad 11, a lead portion 12A having an external terminal 17A located relatively inside (die pad 11 side) and a lead portion having an external terminal 17B located relatively outside (support lead 13 side). 12B are alternately arranged over the entire circumference. Thereby, the malfunction that the external terminals 17A and 17B of the lead portions 12A and 12B come into contact with the adjacent lead portions 12B and 12A is prevented.
  • the external terminal 17A located on the inner side is also referred to as the inner external terminal 17A
  • the external terminal 17B located on the outer side is also referred to as the outer external terminal 17B.
  • the inner external terminal 17A and the outer external terminal 17B all have the same planar shape.
  • the plurality of inner external terminals 17A are all arranged along a straight line parallel to one side of the die pad 11 when viewed from the plane.
  • the plurality of outer external terminals 17 ⁇ / b> B are all arranged on a straight line parallel to one side of the die pad 11 when viewed from the plane. That is, the plurality of inner external terminals 17A and the plurality of outer external terminals 17B are arranged in two rows along a straight line parallel to either the X direction or the Y direction.
  • the present invention is not limited to this.
  • the plurality of inner external terminals 17A and / or the plurality of outer external terminals 17B may be arranged on an arc as viewed from the plane.
  • the lead portion 12A having the inner external terminal 17A has an inner lead 51, a connection lead 52, and a terminal portion (first terminal portion) 53. Yes.
  • the inner lead 51 extends inward (on the die pad 11 side) from the terminal portion 53, and the internal terminal 15 is formed on the inner end surface thereof.
  • the internal terminal 15 is a region that is electrically connected to the semiconductor element 21 via a bonding wire 22 as will be described later. For this reason, on the internal terminal 15, the plating part 25 which improves adhesiveness with the bonding wire 22 is provided.
  • the inner lead 51 extends obliquely with respect to the support lead 13.
  • connection lead 52 is located outside the terminal portion 53 (on the support lead 13 side), and its outer end is connected to the support lead 13.
  • the connection lead 52 extends perpendicularly to the support lead 13 to which the connection lead 52 is coupled. Further, an inner external terminal 17 ⁇ / b> A is formed on the back surface of the terminal portion 53.
  • the inner lead 51 and the connection lead 52 of the lead portion 12A are formed thin by half-etching from the back side (the side opposite to the surface on which the semiconductor element 21 is mounted).
  • the terminal portion 53 has the same thickness as the die pad 11 and the support lead 13 without being half-etched.
  • Half-etching means that the material to be etched is etched halfway in the thickness direction.
  • the lead part 12B having the outer external terminal 17B among the lead parts 12A and 12B has an inner lead 61, a connection lead 62, and a terminal part 63.
  • the inner lead 61 is located on the inner side (on the die pad 11 side) than the terminal portion 63, and the inner terminal 15 is formed on the inner end surface thereof.
  • the inner lead 61 has a straight part 61b extending perpendicularly to the support lead 13 and a sloped part 61a extending inclined from the straight part 61b.
  • connection lead 62 is positioned on the outer side (support lead 13 side) than the terminal portion 63, and the outer end portion thereof is coupled to the support lead 13.
  • the connection lead 62 extends perpendicular to the support lead 13 to which the connection lead 62 is coupled.
  • an outer external terminal 17B is formed on the back surface of the terminal portion 63.
  • the inner lead 61 and the connection lead 62 of the lead portion 12B are formed thin by half-etching from the back surface side (the side opposite to the surface on which the semiconductor element 21 is mounted). Moreover, the terminal part 63 has the same thickness as the die pad 11 and the support lead 13 without being half-etched. As described above, since the inner lead 61 and the connecting lead 62 are thinner than the terminal portion 63, the narrow lead portion 12B can be formed with high accuracy, and the semiconductor device 20F is small and has a large number of pins. Can be obtained.
  • each lead portion 12A, 12B (the cross-sectional shape along the direction parallel to the support lead 13 supporting each lead portion 12A, 12B). Further explanation will be given.
  • the inner lead 51 and the connection lead 52 of the lead portion 12A are each subjected to half-etching from the back surface side, so that each has a substantially rectangular shape, a substantially trapezoidal shape, or It has a cross-section that is substantially kamaboko.
  • the inner lead 61 and the connecting lead 62 of the lead portion 12B are also half-etched from the back surface side, so that each has a substantially quadrangular, trapezoidal, or substantially semi-cylindrical cross section. Yes.
  • the terminal portion 53 of the lead portion 12A has a shape in which both side surfaces are curved inward.
  • the width w A2 of the inner external terminal 17A (the back surface of the terminal portion 53) is wider than the width w A1 of the surface of the terminal portion 53.
  • the terminal portion 63 of the lead portion 12B similarly has a shape in which both side surfaces are curved inward, and the outer external terminal 17B (terminal portion).
  • width w B2 of the back surface) of 63 is wider than the width w B1 of the surface of the terminal portion 63.
  • the width w c is in the 60 [mu] m ⁇ 90 [mu] m or 75 [mu] m ⁇ 90 [mu] m.
  • the thickness t c of the neighboring portion 55 is 50 ⁇ m to 75 ⁇ m or 60 ⁇ m to 75 ⁇ m.
  • the width w c of the vicinity portion 55 is set to 60 ⁇ m or 75 ⁇ m or more, and the thickness t c is set to 50 ⁇ m or 60 ⁇ m or more, thereby maintaining the strength of the portion corresponding to the root of the lead portions 12A and 12B (the vicinity portion 55). ing. For this reason, even if it is a case where the space
  • the interval between the lead portions 12A and 12B can be narrowed, and the external terminals 17A and 16A of each semiconductor device 20F can be reduced.
  • the number of 17B (number of pins) can be increased.
  • near portion 56 of the terminal portions 53 and 63 has a width w d is in the 60 [mu] m ⁇ 90 [mu] m or 75 [mu] m ⁇ 90 [mu] m.
  • the thickness t d of the neighboring portion 56 is 50 ⁇ m to 75 ⁇ m or 60 ⁇ m to 75 ⁇ m.
  • the width w d of the portion near 56 and 60 ⁇ m or 75 ⁇ m or more, by the thickness t d was 50 ⁇ m or 60 ⁇ m or more, maintains the strength of the portion (portion near 56) corresponding to the base of the inner leads 51 and 61 It is possible to suppress the strength of the inner leads 51 and 61 from being lowered, and to prevent the inner leads 51 and 61 from being deformed. Further, by setting the width w d of the neighboring portion 56 to 90 ⁇ m or less and the thickness t d to 75 ⁇ m or less, the interval between the lead portions 12A and 12B can be narrowed, so that the external terminal 17A of each semiconductor device 20F can be reduced. , 17B (number of pins) can be increased.
  • the distance d between the adjacent lead portions 12A and 12B is preferably 90 ⁇ m to 150 ⁇ m. As described above, by setting the distance d to 90 ⁇ m or more, it is possible to reliably form through portions between the adjacent lead portions 12A and 12B by etching. Further, by setting the distance d to 150 ⁇ m or less, the number of external terminals 17A and 17B (number of pins) of each semiconductor device 20F can be secured at a certain number or more. Specifically, the number of external terminals 17A and 17B (number of pins) can be set to 80 to 250 pins, for example.
  • the lead frame 10F described above is made of a metal material having a tensile strength of 750 MPa to 1100 MPa or 850 MPa to 1100 MPa, preferably a tensile strength of 920 MPa to 1010 MPa. Since the lead frame 10F is made of a metal material having a tensile strength of 750 MPa or 850 MPa or more, the strength of the lead portions 12A and 12B is prevented from being reduced and deformation is prevented, so the distance between the lead portions 12A and 12B Can be narrowed. In general, a metal material having high tensile strength tends to have low conductivity. For this reason, it can prevent that the electroconductivity of lead part 12A, 12B falls by comprising the lead frame 10F from the metal material which has a tensile strength of 1100 Mpa or less.
  • Examples of such a metal material include a copper alloy, and specifically, for example, a Corson alloy (Cu—Ni—Si), a nickel tin copper alloy (Cu—Ni—Sn), a titanium copper alloy (Cu—). Ti).
  • a Corson alloy Cu—Ni—Si
  • a nickel tin copper alloy Cu—Ni—Sn
  • a titanium copper alloy Cu—).
  • the thickness of the lead frame 10F can be set to 80 ⁇ m to 250 ⁇ m depending on the configuration of the semiconductor device 20F to be manufactured.
  • the lead portions 12A and 12B are arranged along all four sides of the die pad 11, but the present invention is not limited to this.
  • the lead portions 12A and 12B are arranged along only two opposite sides of the die pad 11. May be.
  • FIGS. 27 and 28 are diagrams showing a semiconductor device (DR-QFN (Dual Row QFN) type) according to the present embodiment.
  • the semiconductor device (semiconductor package) 20F includes a die pad 11, a plurality of lead portions 12A and 12B arranged around the die pad 11, and a semiconductor element 21 mounted on the die pad 11. And a plurality of bonding wires (connection members) 22 for electrically connecting the lead portions 12A and 12B and the semiconductor element 21.
  • the die pad 11, the lead portions 12 ⁇ / b> A and 12 ⁇ / b> B, the semiconductor element 21 and the bonding wire 22 are resin-sealed with a sealing resin 23.
  • the die pad 11 and the lead portions 12A and 12B are manufactured from the lead frame 10F described above.
  • the configurations of the die pad 11 and the lead portions 12A and 12B are the same as those shown in FIGS. 22 to 26 described above except for the region not included in the unit lead frame 10a, and detailed description thereof will be omitted here.
  • the configurations of the semiconductor element 21, the bonding wire 22, the sealing resin 23, the adhesive 24, and the plating portion 25 are substantially the same as those in the first embodiment, and thus detailed description thereof is omitted.
  • 29A to 29F are cross-sectional views (corresponding to FIG. 23) showing the manufacturing method of the lead frame 10F.
  • a flat metal substrate 31 is prepared.
  • the metal substrate 31 one having a tensile strength of 750 MPa to 1100 MPa or 850 MPa to 1100 MPa is used.
  • Corson alloy Cu—Ni—Si
  • nickel tin copper alloy Cu—Ni—Sn
  • titanium A substrate made of a copper alloy such as a copper alloy can be used.
  • photosensitive resists 32a and 33a are applied to the entire front and back surfaces of the metal substrate 31, respectively, and dried (FIG. 29B).
  • photosensitive resists 32a and 33a conventionally known resists can be used.
  • the metal substrate 31 is exposed through a photomask and developed to form etching resist layers 32 and 33 having desired openings 32b and 33b (FIG. 29C).
  • etching is performed on the metal substrate 31 with the etching solution using the etching resist layers 32 and 33 as corrosion resistant films (FIG. 29D).
  • the corrosive liquid can be appropriately selected according to the material of the metal substrate 31 to be used.
  • a ferric chloride aqueous solution is usually used from both sides of the metal substrate 31. It can be performed by spray etching. As in the case of the first embodiment, two stages of spray etching may be performed for each side of the metal substrate 31.
  • the internal terminal 15 is plated to form a plated portion 25 (FIG. 29 (f)).
  • the type of plating selected is not limited as long as the adhesion to the bonding wire 22 can be ensured.
  • single-layer plating such as Ag or Au may be used, or Ni / Pd or Ni / Pd / Au may be used.
  • Multi-layer plating laminated in this order may be used.
  • the plating part 25 may be provided only on the connection part with the bonding wire 22 among the lead parts 12A and 12B, or may be provided on the entire surface of the lead frame 10F.
  • the lead frame 10F is manufactured by the method shown in FIGS. 29A to 29F (FIG. 30A).
  • the semiconductor element 21 is mounted on the die pad 11 of the lead frame 10F.
  • the semiconductor element 21 is mounted on the die pad 11 and fixed using an adhesive 24 such as a die bonding paste (die attachment step) (FIG. 30B).
  • the electrodes 21a of the semiconductor element 21 and the plating portions 25 (internal terminals 15) of the lead portions 12A and 12B are electrically connected to each other by bonding wires (connection members) 22 (wire bonding step). (FIG. 30 (c)).
  • the lead frame 10F is placed on the heat block 36 of the wire bonding apparatus.
  • the heat block 36 heats from the back side of the inner lead 51 of the lead portion 12A and the inner lead 61 of the lead portion 12B.
  • the electrodes 21a of the semiconductor element 21 and the plating portions 25 of the lead portions 12A and 12B are electrically connected using the bonding wires 22. Connect.
  • the lead portions 12A and 12B are stably placed on the heat block 36. be able to. Thereby, the bonding wire 22 can be stably connected to the plating portion 25.
  • the sealing resin 23 is formed by injection molding or transfer molding of a thermosetting resin or a thermoplastic resin to the lead frame 10F (FIG. 30D). In this way, the lead frame 10F, the semiconductor element 21, the lead portions 12A and 12B, and the bonding wire 22 are sealed.
  • the lead frame 10F is separated for each unit lead frame 10a (see FIG. 22) by dicing the sealing resin 23 between the semiconductor elements 21.
  • the lead frames 10F and the sealing resin 23 between the unit lead frames 10a may be cut while rotating a blade (not shown) made of, for example, a diamond grindstone.
  • the lead frame 10F is made of a metal material having a tensile strength of 750 MPa to 1100 MPa or 850 MPa to 1100 MPa, and in the vicinity of the support lead 13 among the lead portions 12A and 12B of each unit lead frame 10a.
  • the width of the portion 55 is 60 ⁇ m to 90 ⁇ m or 75 ⁇ m to 90 ⁇ m, and the thickness of the neighboring portion 55 is 50 ⁇ m to 75 ⁇ m or 60 ⁇ m to 75 ⁇ m.
  • the strength of the lead portions 12A and 12B can be prevented from lowering, and therefore, for example, in the manufacturing process of the semiconductor device 20F described above, it is possible to prevent the lead portions 12A and 12B from being deformed such as distortion or bending. it can.
  • the distance d (pitch) between the adjacent lead portions 12A and 12B can be reduced, and the number of external terminals 17A and 17B (number of pins) of the semiconductor device 20F can be increased.
  • the pitch of the lead portions 12A and 12B can be narrowed by 10% or more as compared with the conventional semiconductor device. For example, when the size of the semiconductor device 20F is 14 mm ⁇ 14 mm, the number of external terminals 17A and 17B (number of pins) can be increased to 200 pins or more.
  • the strength of the lead portions 12A and 12B is suppressed from decreasing, and the lead portions 12A and 12B are deformed to cause external terminals 17A and 17B. It is possible to prevent a problem that the position shift occurs. Thereby, the yield of the lead frame 10F can be increased.
  • the length of the lead portions 12A and 12B can be increased by increasing the strength of the lead portions 12A and 12B, the internal terminal 15 can be brought closer to the die pad 11. Thereby, the usage-amount of the expensive bonding wire 22 can be reduced, and the manufacturing cost of the lead frame 10F can be reduced.
  • the lead frame 10F may have a plurality of lead portions having the same length (QFN type).
  • the present invention is not limited to this, and the external terminals are arranged in three or more rows. May be.
  • Example 1 A lead frame 10F (Example 1) having the configuration according to the present embodiment was manufactured.
  • a copper alloy Fluukawa
  • a metal substrate 31 manufactured by Denki Kogyo Co., Ltd. and trade name EFTEC-98S was prepared. The thickness of the metal substrate 31 was 200 ⁇ m, and the tensile strength of the metal substrate 31 was 860 MPa.
  • the tensile strength of the metal substrate 31 was measured by cutting the metal substrate 31 into a width of 20 mm, preparing a test piece based on JIS Z2201, and using a tensile tester.
  • the metal substrate 31 was cut into a size of 300 mm ⁇ 100 mm and etched to obtain a lead frame 10F (Example 1) having a size of 250 mm ⁇ 70 mm.
  • spray etching is performed from both surfaces of the metal substrate (etching process), and then the resist is stripped by an alkaline aqueous solution by a spray method (resist stripping process), and the final cleaning is performed by a spray method (final water washing step). ).
  • the total spray time in the above three steps was 10 minutes, and the spray pressure was 0.2 MPa.
  • the obtained lead frame had a shape (with 56 surfaces) in which 56 chips could be arranged, and the number of lead portions per surface was 156. Further, in each of the lead portions 12A and 12B, the width of the vicinity portion 55 of the support lead 13 is 75 ⁇ m, and the thickness of the vicinity portion 55 is 60 ⁇ m.
  • Example 2 Example 1 except that the tensile strength of the metal substrate 31 is 780 MPa, the width of the vicinity 55 of the support lead 13 of each lead portion 12A, 12B is 60 ⁇ m, and the thickness of the vicinity 55 is 50 ⁇ m. In the same manner, a lead frame having the same shape as in Example 1 was produced.
  • Example 1 Copper alloy containing 3.0% by mass of Ni, 0.65% by mass of Si, 0.15% by mass of Mg as the material of the metal substrate, with the balance being copper and inevitable impurities (JX Nippon Mining & Metals Corporation)
  • a lead frame having the same shape as in Example 1 was produced in the same manner as in Example 1 except that the product made by the company, trade name C7025 1 / 2H) was used.
  • the tensile strength of the metal substrate was measured and found to be 726 MPa.
  • Example 1 The above-mentioned three types of lead frames (Example 1, Example 2 and Comparative Example 1) were each tested for whether or not the lead part was deformed.
  • This test method was carried out by determining whether or not the lead portion was deformed during the production of each lead frame. That is, in the etching step, resist stripping step, and final water washing step, it was confirmed whether or not the impacted portion had a desired strength by receiving an impact by spraying.
  • the deformation of the vicinity of the external terminal provided on the inner lead and the support lead was measured.
  • this measurement method depth of focus measurement using a metal microscope was used, and the height of the lead frame deformed in the thickness direction was measured. When the deformed height is 30 ⁇ m or less, which is difficult to determine even by visual inspection of the appearance, it was determined that no deformation occurred.
  • Example 2 In all of Example 1, Example 2, and Comparative Example 1, 10 lead frames were produced. For each manufactured lead frame, the number of lead portions where deformation occurred was measured, and the number of deformed leads per lead frame was calculated. Further, the number of lead portions deformed per chip (with one surface) was calculated from the calculated number of deformed lead portions per lead frame. The results are shown in Table 1.
  • FIGS. 31 to 34 are views showing a sixth embodiment of the present invention.
  • the half-etched portion (recessed portion) of the connection ring 14 is not provided continuously over the entire circumference of the connection ring 14 but is provided regularly along the connection ring 14.
  • a thick portion 28a is formed between the etched portions.
  • the same parts as those in the first to fifth embodiments are denoted by the same reference numerals, and detailed description thereof is omitted.
  • connection ring 14 is provided on the distal end side of the inner lead 51 of the lead portions 12A and 12B, and is disposed so as to surround the die pad 11. Yes.
  • Inner leads 51 of the lead portions 12 ⁇ / b> A and 12 ⁇ / b> B are coupled to the outer peripheral edge (the support lead 13 side peripheral edge) of the connection ring 14.
  • a connecting bar 19 extends from the connection ring 14 toward the inside (on the die pad 11 side).
  • the connection ring 14 is connected to and supported by all the inner leads 51, but the present invention is not limited to this, and the connection ring 14 may be connected to and supported by only some of the inner leads 51.
  • a recess 14 c is formed on the surface of the connection ring 14 and in the vicinity of the tip of each inner lead 51.
  • Each recess 14c is formed by half etching, and has a certain depth without penetrating in the thickness direction.
  • Each concave portion 14 c is formed at a substantially central portion in the width direction of the connection ring 14.
  • a thick portion 28a is formed between the concave portions 14c adjacent to each other. That is, the concave portions 14 c and the thick portions 28 a are alternately arranged along the length direction of the connection ring 14. In this case, the thick portion 28 a is not half-etched and has the same thickness as the die pad 11 and the support lead 13. Two connecting bars 19 are connected to all four sides of the die pad 11. The die pad 11 is supported by a connection ring 14 and a connection bar 19.
  • the suspension leads are not provided at the four corners of the die pad 11, the lead portions 12 ⁇ / b> A and 12 ⁇ / b> B can be arranged near the four corners of the die pad 11. For this reason, compared with the case where the die pad 11 is supported via a suspension lead, the number of lead parts 12A and 12B can be increased.
  • a thick wall portion located between the bank portion around each recess 14c in the connection ring 14 and each recess portion 14c in the connection ring 14. 28a begins to be etched at the same time, but the removal of the thick portion 28a takes more time than the region in which the concave portions 14c are provided, and this allows the etching progress of the connection ring 14 itself to be adjusted. is there.
  • connection ring 14 when the connection ring 14 is etched away from the back surface side of the lead frame 10G (see FIG. 7E), the position corresponding to the connection ring 14 of the etching resist layer 34 on the back surface of the lead frame 10 and the sealing resin 23.
  • An opening 34a is provided in the front.
  • the recesses 14c and the thick portions 28a in the connection ring 14 are appropriately dissolved and removed by the corrosive liquid entering from the openings 34a.
  • the concave portion 14c is provided on the surface of the connection ring 14, the corrosive liquid entering from the opening 34a properly dissolves the entire connection ring 14 without dissolving the lead portions 12A and 12B more than necessary. Can be removed.
  • the recesses 14 c are provided in the vicinity of the tips of all the inner leads 51.
  • the present invention is not limited to this, and the recesses 14 c may be provided only in the vicinity of the tips of some of the inner leads 51.
  • the concave portions 14c are provided in the form of dots at regular intervals along the connection ring 14, and the thick portions 28a are formed between the concave portions 14c. Ingress and dissolution can be adjusted as appropriate.
  • a semiconductor device 20H shown in FIG. 34 shows a modification of the present embodiment, in which the thick portion 28a is not completely removed and is left inside the semiconductor device 20H.
  • This semiconductor device 20H is manufactured from the lead frame 10G shown in FIGS. 31 and 32A and 32B, and the thick portion 28a is left without being completely removed, and the second terminal Part.
  • the thick portions 28a are arranged at intervals from each other along all four sides (four sides parallel to the X direction or Y direction in FIG. 34) around the die pad 11.
  • the thick portion 28a is formed from a part of the connection ring 14, it is arranged along a straight line connecting the vicinity of the tip of each inner lead 51.
  • the plurality of thick portions 28 a are arranged in a rectangular shape in a region between the die pad 11 and the tip of the inner lead 51.
  • each thick part 28a is separated from the die pad 11, the lead parts 12A and 12B, and the other thick part 28a, and constitutes a second terminal part electrically independently from these members.
  • the thick portion 28 a is not half-etched and has the same thickness as the die pad 11.
  • an external terminal 17C that is electrically connected to an external mounting substrate (not shown) is formed on the back surface of the thick portion 28a.
  • the plating part 25 which improves adhesiveness with the bonding wire 22 is provided in the surface of the thick part 28a, and the bonding wire 22 is connected to each.
  • connection ring 14 excluding the thick portion 28a
  • a recess 27 is formed in the region between the lead portions 12A and 12B and the die pad 11 on the back surface of the sealing resin 23. Is done.
  • connection ring 14 when manufacturing the semiconductor device 20H, a part of the connection ring 14 is removed, and a part of the connection ring 14 that is not removed is individually separated to become the second terminal portion. A portion 28a is formed. As described above, since a large number of thick portions 28a are formed, the number of terminal portions (number of pins) connected to an external mounting substrate can be increased, and the density of the semiconductor device 20 can be further increased. Can be realized.
  • the thick part 28a left in the semiconductor device 20H is not necessarily used as an external terminal (second terminal part).
  • the thick portion 28a left in the semiconductor device 20H may serve to prevent deformation around the die pad 11 when an impact is applied to the semiconductor device 20H.
  • the thick portion 28a may serve to improve the heat dissipation of the semiconductor device 20H by increasing the number of metal portions exposed on the back surface of the semiconductor device 20H.
  • the manufacturing method of the lead frame 10G and the manufacturing method of the semiconductor devices 20G and 20C according to the present embodiment are the same as the manufacturing method of the lead frame 10 according to the first embodiment (FIGS. 6A to 6F) and the semiconductor. This is substantially the same as the method for manufacturing the device 20 (FIGS. 7A to 7F).

Abstract

　A lead frame (10), provided with: a die pad (11) on which a semiconductor element (21) is mounted; a plurality of long outer periphery lead parts (12A) and short outer periphery lead parts (12B) provided around the die pad (11), each of the long outer periphery lead parts (12A) and the short outer periphery lead parts (12B) including a first terminal part (53); and a connection ring (14) disposed between the die pad (11) and the long outer periphery lead parts (12A) and the short outer periphery lead parts (12B), the connection ring (14) enclosing the die pad (11). A plurality of inside leads (26A-26D) include long inside leads (26A, 26C) and short inside leads (26B, 26D). The long inside leads (26A, 26C) and the short inside leads (26B, 26D) are arranged alternatingly along the connection ring (14).

Description

リードフレームおよびその製造方法、ならびに半導体装置およびその製造方法Lead frame and manufacturing method thereof, and semiconductor device and manufacturing method thereof
　本発明は、リードフレームおよびその製造方法、ならびに半導体装置およびその製造方法に関する。 The present invention relates to a lead frame and a manufacturing method thereof, and a semiconductor device and a manufacturing method thereof.
　近年、基板に実装される半導体装置の小型化および薄型化が要求されてきている。このような要求に対応すべく、従来、リードフレームを用い、その搭載面に搭載した半導体素子を封止樹脂によって封止するとともに、裏面側にリードの一部分を露出させて構成された、いわゆるＱＦＮ（Quad Flat Non-lead）タイプの半導体装置が種々提案されている。 In recent years, there has been a demand for miniaturization and thinning of semiconductor devices mounted on a substrate. In order to meet such demands, conventionally, a lead frame is used, and a semiconductor element mounted on the mounting surface is sealed with a sealing resin, and a part of the lead is exposed on the back surface side, so-called QFN. Various (Quad Flat Non-lead) type semiconductor devices have been proposed.
　しかしながら、従来一般的な構造からなるＱＦＮの場合、端子数が増加するにしたがってパッケージが大きくなるため、実装信頼性を確保することが難しくなるという課題があった。これに対して、多ピン化されたＱＦＮを実現するための技術として、外部端子を２列に配列したパッケージの開発が進められている（例えば特許文献１）。このようなパッケージは、ＤＲ－ＱＦＮ（Dual Row QFN）パッケージともよばれている。 However, in the case of a QFN having a conventional general structure, there is a problem that it is difficult to ensure mounting reliability because the package becomes larger as the number of terminals increases. On the other hand, as a technique for realizing a multi-pin QFN, development of a package in which external terminals are arranged in two rows is underway (for example, Patent Document 1). Such a package is also called a DR-QFN (DualDRow QFN) package.
特開２００６－１９７６７号公報JP 2006-19767 A
　近年、ＤＲ－ＱＦＮパッケージを生産するにあたり、チップサイズを変更することなく、リード部の数（ピン数）を増やすことが求められてきている。これに対して、従来、ピン数を増やすために、パッケージサイズを大きくする手法がとられてきた。しかしながら、パッケージを電子機器へ搭載する上での制約があるため、パッケージサイズを大きくすることには限界がある。また、パッケージサイズが大きくなることに伴い、インナーリードの長さが長くなるため、インナーリードに変形が生じやすくなるという問題もある。 In recent years, in producing a DR-QFN package, it has been required to increase the number of leads (number of pins) without changing the chip size. On the other hand, conventionally, in order to increase the number of pins, a method of increasing the package size has been taken. However, there is a limit in increasing the package size due to restrictions on mounting the package on the electronic device. In addition, as the package size increases, the length of the inner lead increases, which causes a problem that the inner lead is likely to be deformed.
　本発明はこのような点を考慮してなされたものであり、外部と接続される端子部の数（ピン数）を増やすことが可能な、リードフレームおよびその製造方法、ならびに半導体装置およびその製造方法を提供することを目的とする。 The present invention has been made in view of the above points, and can increase the number of terminal portions (number of pins) connected to the outside, a lead frame, a manufacturing method thereof, and a semiconductor device and a manufacturing method thereof. It aims to provide a method.
　本発明は、半導体装置用のリードフレームであって、半導体素子が搭載されるダイパッドと、前記ダイパッド周囲に設けられ、それぞれ第１端子部を含む複数の外周リード部と、前記ダイパッドと前記外周リード部との間に配置され、前記ダイパッドを取り囲む接続リングと、前記接続リングによって支持され、それぞれ第２端子部を含む複数の内側リード部とを備え、前記複数の内側リード部は、長内側リード部と、短内側リード部とを含み、前記長内側リード部と前記短内側リード部とが前記接続リングに沿って交互に配置されていることを特徴とするリードフレームである。 The present invention provides a lead frame for a semiconductor device, a die pad on which a semiconductor element is mounted, a plurality of outer peripheral lead portions provided around the die pad, each including a first terminal portion, the die pad, and the outer peripheral lead. A connection ring that surrounds the die pad and a plurality of inner lead portions that are supported by the connection ring and each include a second terminal portion, wherein the plurality of inner lead portions are long inner leads. And a short inner lead portion, wherein the long inner lead portion and the short inner lead portion are alternately arranged along the connection ring.
　本発明は、前記複数の内側リード部は、前記接続リングの内側および外側の両方から延びていることを特徴とするリードフレームである。 The present invention is the lead frame characterized in that the plurality of inner lead portions extend from both the inner side and the outer side of the connection ring.
　本発明は、前記複数の内側リード部のうち、前記接続リングの内側から延びる前記短内側リード部と、前記接続リングの外側から延びる前記長内側リード部とが、前記接続リングを介して互いに反対側の位置に配置されていることを特徴とするリードフレームである。 In the present invention, among the plurality of inner lead portions, the short inner lead portion extending from the inner side of the connection ring and the long inner lead portion extending from the outer side of the connection ring are opposite to each other via the connection ring. The lead frame is disposed at a side position.
　本発明は、前記接続リングの表面に、前記接続リングに沿って凹溝が形成されていることを特徴とするリードフレームである。 The present invention is the lead frame characterized in that a concave groove is formed along the connection ring on the surface of the connection ring.
　本発明は、前記内側リード部は、前記接続リングに連結される接続リードを有し、前記接続リードは、裏面側から薄肉化されていることを特徴とするリードフレームである。 The present invention is the lead frame characterized in that the inner lead portion has a connection lead coupled to the connection ring, and the connection lead is thinned from the back side.
　本発明は、前記内側リード部は、前記接続リングに連結される接続リードを有し、前記接続リードは、表面側から薄肉化されていることを特徴とするリードフレームである。 The present invention is the lead frame characterized in that the inner lead portion has a connection lead coupled to the connection ring, and the connection lead is thinned from the surface side.
　本発明は、前記複数の外周リード部は、長外周リード部と、短外周リード部とを含み、前記長外周リード部と前記短外周リード部とが交互に配置され、前記複数の内側リード部は、前記接続リングの少なくとも外側から延びており、前記長外周リード部と前記短内側リード部とが互いに向かい合い、前記短外周リード部と前記長内側リード部とが互いに向かい合うことを特徴とするリードフレームである。 In the present invention, the plurality of outer peripheral lead portions include a long outer peripheral lead portion and a short outer peripheral lead portion, and the long outer peripheral lead portions and the short outer peripheral lead portion are alternately arranged, and the plurality of inner lead portions Extending from at least the outside of the connection ring, wherein the long outer periphery lead portion and the short inner lead portion face each other, and the short outer periphery lead portion and the long inner lead portion face each other. It is a frame.
　本発明は、７５０Ｍｐａ～１１００Ｍｐａの引っ張り強度をもつ金属材料から構成されていることを特徴とするリードフレームである。 The present invention is a lead frame characterized in that it is made of a metal material having a tensile strength of 750 Mpa to 1100 Mpa.
　本発明は、半導体装置用のリードフレームであって、半導体素子が搭載されるダイパッドと、前記ダイパッド周囲に設けられ、それぞれ第１端子部を含む複数の外周リード部と、前記ダイパッドと前記外周リード部との間に配置されたリード接続部と、前記リード接続部によって支持され、それぞれ第２端子部を含む複数の内側リード部とを備え、前記複数の内側リード部は、長内側リード部と、短内側リード部とを含み、前記長内側リード部と前記短内側リード部とが前記リード接続部に沿って交互に配置されていることを特徴とするリードフレームである。 The present invention provides a lead frame for a semiconductor device, a die pad on which a semiconductor element is mounted, a plurality of outer peripheral lead portions provided around the die pad, each including a first terminal portion, the die pad, and the outer peripheral lead. A lead connecting portion disposed between the lead connecting portion and a plurality of inner lead portions each supported by the lead connecting portion and including a second terminal portion, wherein the plurality of inner lead portions include a long inner lead portion and And a short inner lead portion, wherein the long inner lead portion and the short inner lead portion are alternately arranged along the lead connecting portion.
　本発明は、半導体装置であって、ダイパッドと、前記ダイパッド周囲に設けられ、それぞれ第１端子部を含む複数の外周リード部と、前記ダイパッドと前記外周リード部との間に配置され、前記ダイパッドおよび前記外周リード部から分離された複数の第２端子部と、前記ダイパッド上に搭載された半導体素子と、前記半導体素子と各外周リード部とを電気的に接続するとともに、前記半導体素子と各第２端子部とを電気的に接続する接続部材と、前記ダイパッドと、前記複数の外周リード部と、前記複数の第２端子部と、前記半導体素子と、前記接続部材とを封止する封止樹脂とを備え、前記複数の外周リード部は、前記第１端子部が相対的に内側に位置する長外周リード部と、前記第１端子部が相対的に外側に位置する短外周リード部とを含み、前記長外周リード部と前記短外周リード部とが交互に配置され、前記封止樹脂の裏面のうち、前記外周リード部と前記ダイパッドとの間の領域に、前記ダイパッドを取り囲むように凹部が形成されていることを特徴とする半導体装置である。 The present invention is a semiconductor device, and is disposed around a die pad, a plurality of outer peripheral lead portions each including a first terminal portion, and between the die pad and the outer peripheral lead portion. And a plurality of second terminal portions separated from the outer periphery lead portion, a semiconductor element mounted on the die pad, and electrically connecting the semiconductor element and each outer periphery lead portion; and A sealing member that seals the connection member that electrically connects the second terminal portion, the die pad, the plurality of outer peripheral lead portions, the plurality of second terminal portions, the semiconductor element, and the connection member. A plurality of outer peripheral lead portions, wherein the first terminal portion is positioned relatively on the inner side, and the first terminal portion is positioned relatively on the outer side. The long outer periphery lead portions and the short outer periphery lead portions are alternately arranged, and surround the die pad in a region between the outer periphery lead portion and the die pad on the back surface of the sealing resin. A semiconductor device is characterized in that a recess is formed.
　本発明は、半導体装置であって、ダイパッドと、前記ダイパッド周囲に設けられ、それぞれ第１端子部を含む複数の外周リード部と、前記ダイパッドと前記外周リード部との間に配置され、前記ダイパッドおよび前記外周リード部から分離された複数の第２端子部と、前記ダイパッド上に搭載された半導体素子と、前記半導体素子と各外周リード部とを電気的に接続するとともに、前記半導体素子と各第２端子部とを電気的に接続する接続部材と、前記ダイパッドと、前記複数の外周リード部と、前記複数の第２端子部と、前記半導体素子と、前記接続部材とを封止する封止樹脂とを備え、前記複数の外周リード部は、前記第１端子部が相対的に内側に位置する長外周リード部と、前記第１端子部が相対的に外側に位置する短外周リード部とを含み、前記長外周リード部と前記短外周リード部とが交互に配置され、前記封止樹脂の裏面のうち、前記外周リード部と前記ダイパッドとの間の領域に凹部が形成されていることを特徴とする半導体装置である。 The present invention is a semiconductor device, and is disposed around a die pad, a plurality of outer peripheral lead portions each including a first terminal portion, and between the die pad and the outer peripheral lead portion. And a plurality of second terminal portions separated from the outer periphery lead portion, a semiconductor element mounted on the die pad, and electrically connecting the semiconductor element and each outer periphery lead portion; and A sealing member that seals the connection member that electrically connects the second terminal portion, the die pad, the plurality of outer peripheral lead portions, the plurality of second terminal portions, the semiconductor element, and the connection member. A plurality of outer peripheral lead portions, wherein the first terminal portion is positioned relatively on the inner side, and the first terminal portion is positioned relatively on the outer side. The long outer periphery lead portions and the short outer periphery lead portions are alternately arranged, and a recess is formed in a region between the outer periphery lead portion and the die pad on the back surface of the sealing resin. A semiconductor device characterized by the above.
　本発明は、リードフレームの製造方法において、金属基板を準備する工程と、前記金属基板をエッチング加工することにより、前記金属基板に前記ダイパッド、前記外周リード部、前記接続リングおよび前記内側リード部を形成する工程とを備えたことを特徴とするリードフレームの製造方法である。 The present invention provides a method of manufacturing a lead frame, comprising: preparing a metal substrate; and etching the metal substrate to provide the metal substrate with the die pad, the outer peripheral lead portion, the connection ring, and the inner lead portion. And a step of forming the lead frame.
　本発明は、半導体装置の製造方法において、リードフレームを準備する工程と、前記リードフレームの前記ダイパッド上に前記半導体素子を搭載する工程と、前記半導体素子と各外周リード部とを接続部材により電気的に接続する工程と、前記ダイパッドと、前記複数の外周リード部と、前記半導体素子と、前記接続部材とを封止樹脂により封止する工程と、前記リードフレームの裏面側から前記接続リングの少なくとも一部を除去することにより、前記複数の第２端子部をそれぞれ個別に分離する工程とを備えたことを特徴とする半導体装置の製造方法である。 The present invention provides a method of manufacturing a semiconductor device, wherein a step of preparing a lead frame, a step of mounting the semiconductor element on the die pad of the lead frame, and the semiconductor element and each outer peripheral lead portion are electrically connected by a connecting member. Connecting the die ring, the plurality of outer peripheral lead portions, the semiconductor element, and the connecting member with a sealing resin, and connecting the connection ring from the back side of the lead frame. And a step of individually separating the plurality of second terminal portions by removing at least part of the semiconductor device.
　本発明は、リードフレームの製造方法において、金属基板を準備する工程と、前記金属基板をエッチング加工することにより、前記金属基板に前記ダイパッド、前記外周リード部、前記リード接続部および前記内側リード部を形成する工程とを備えたことを特徴とするリードフレームの製造方法である。 The present invention provides a method of manufacturing a lead frame, comprising: preparing a metal substrate; and etching the metal substrate to form the die pad, the outer peripheral lead portion, the lead connection portion, and the inner lead portion on the metal substrate. And a step of forming a lead frame.
　本発明は、半導体装置の製造方法において、リードフレームを準備する工程と、前記リードフレームの前記ダイパッド上に前記半導体素子を搭載する工程と、前記半導体素子と各外周リード部とを接続部材により電気的に接続する工程と、前記ダイパッドと、前記複数の外周リード部と、前記半導体素子と、前記接続部材とを封止樹脂により封止する工程と、前記リードフレームの裏面側から前記リード接続部の少なくとも一部を除去することにより、前記複数の第２端子部をそれぞれ個別に分離する工程とを備えたことを特徴とする半導体装置の製造方法である。 The present invention provides a method of manufacturing a semiconductor device, wherein a step of preparing a lead frame, a step of mounting the semiconductor element on the die pad of the lead frame, and the semiconductor element and each outer peripheral lead portion are electrically connected by a connecting member. Connecting the die pad, the plurality of outer peripheral lead portions, the semiconductor element, and the connection member with a sealing resin, and the lead connection portion from the back side of the lead frame. And a step of individually separating the plurality of second terminal portions by removing at least a part of the semiconductor device.
　本発明によれば、外部と接続される端子部の数（ピン数）を増やすことができる。 According to the present invention, the number of terminal portions (number of pins) connected to the outside can be increased.
　本発明は、互いに支持部材を介して連結された複数の単位リードフレームを含むリードフレームであって、各単位リードフレームは、半導体素子が搭載されるダイパッドと、前記ダイパッド周囲に設けられ、それぞれ端子部と前記端子部から内側に延びるインナーリードとを含む複数のリード部とを備え、前記リード部は、隣り合う前記単位リードフレーム間に設けられた前記支持部材によって支持され、前記リードフレームは、８５０ＭＰａ～１１００ＭＰａの引張強度をもつ金属材料から構成され、各単位リードフレームの前記リード部のうち、前記支持部材の近傍部分は、幅が７５μｍ～９０μｍであり、厚みが６０μｍ～７５μｍであることを特徴とするリードフレームである。 The present invention is a lead frame including a plurality of unit lead frames connected to each other via a support member, and each unit lead frame is provided around a die pad on which a semiconductor element is mounted, the die pad, and a terminal. And a plurality of lead portions including an inner lead extending inward from the terminal portion, the lead portion is supported by the support member provided between the adjacent unit lead frames, and the lead frame is It is made of a metal material having a tensile strength of 850 MPa to 1100 MPa, and among the lead portions of each unit lead frame, a portion in the vicinity of the support member has a width of 75 μm to 90 μm and a thickness of 60 μm to 75 μm. This is a featured lead frame.
　本発明は、前記複数のリード部の前記端子部は、隣り合う前記リード部間で内側および外側に位置するよう平面から見て交互に千鳥状に配置されていることを特徴とするリードフレームである。 The present invention is the lead frame characterized in that the terminal portions of the plurality of lead portions are alternately arranged in a staggered manner when viewed from the plane so as to be located inside and outside between the adjacent lead portions. is there.
　本発明は、前記インナーリードは前記端子部よりも厚さが薄いことを特徴とするリードフレームである。 The present invention is the lead frame characterized in that the inner lead is thinner than the terminal portion.
　本発明は、前記リード部は、前記端子部から外側に延びる接続リードを含み、前記接続リードは前記端子部よりも厚さが薄いことを特徴とするリードフレームである。 The present invention is the lead frame characterized in that the lead portion includes a connection lead extending outward from the terminal portion, and the connection lead is thinner than the terminal portion.
　本発明は、前記リード部の前記インナーリードのうち、前記端子部の近傍部分は、幅が７５μｍ～９０μｍであり、厚みが６０μｍ～７５μｍであることを特徴とするリードフレームである。 The present invention is the lead frame characterized in that, of the inner leads of the lead part, the vicinity of the terminal part has a width of 75 μm to 90 μm and a thickness of 60 μm to 75 μm.
　本発明は、前記金属材料は、コルソン系合金（Ｃｕ－Ｎｉ－Ｓｉ）、ニッケル錫銅合金（Ｃｕ－Ｎｉ－Ｓｎ）、又はチタニウム銅合金（Ｃｕ－Ｔｉ）であることを特徴とするリードフレームである。 According to the present invention, the metal material is a Corson alloy (Cu—Ni—Si), a nickel tin copper alloy (Cu—Ni—Sn), or a titanium copper alloy (Cu—Ti). It is.
　本発明は、互いに支持部材を介して連結された複数の単位リードフレームを含むリードフレームであって、各単位リードフレームは、半導体素子が搭載されるダイパッドと、前記ダイパッド周囲に設けられ、それぞれ端子部と前記端子部から内側に延びるインナーリードとを含む複数のリード部とを備え、前記リード部は、隣り合う前記単位リードフレーム間に設けられた前記支持部材によって支持され、前記リードフレームは、７５０ＭＰａ～１１００ＭＰａの引張強度をもつ金属材料から構成され、各単位リードフレームの前記リード部のうち、前記支持部材の近傍部分は、幅が６０μｍ～９０μｍであり、厚みが５０μｍ～７５μｍであることを特徴とするリードフレームである。 The present invention is a lead frame including a plurality of unit lead frames connected to each other via a support member, and each unit lead frame is provided around a die pad on which a semiconductor element is mounted, the die pad, and a terminal. And a plurality of lead portions including an inner lead extending inward from the terminal portion, the lead portion is supported by the support member provided between the adjacent unit lead frames, and the lead frame is It is made of a metal material having a tensile strength of 750 MPa to 1100 MPa, and among the lead parts of each unit lead frame, the vicinity of the support member has a width of 60 μm to 90 μm and a thickness of 50 μm to 75 μm. This is a featured lead frame.
　本発明は、リードフレームを用いて作製された半導体装置であって、前記ダイパッドと、前記ダイパッド周囲に設けられ、それぞれ前記端子部と前記端子部から内側に延びる前記インナーリードとを含む複数の前記リード部と、前記ダイパッド上に搭載された半導体素子と、前記半導体素子と各リード部の前記インナーリードとを電気的に接続する接続部材と、前記ダイパッドと、前記複数のリード部と、前記半導体素子と、前記接続部材とを封止する封止樹脂とを備えたことを特徴とする半導体装置である。 The present invention is a semiconductor device manufactured using a lead frame, and includes a plurality of the die pads and the inner leads provided around the die pads and extending inward from the terminal portions, respectively. A lead part; a semiconductor element mounted on the die pad; a connecting member for electrically connecting the semiconductor element and the inner lead of each lead part; the die pad; the plurality of lead parts; and the semiconductor. A semiconductor device comprising an element and a sealing resin that seals the connection member.
　本発明は、互いに支持部材を介して連結された複数の単位リードフレームを含み、各単位リードフレームは、半導体素子が搭載されるダイパッドと、前記ダイパッド周囲に設けられ、それぞれ端子部と前記端子部から内側に延びるインナーリードとを含む複数のリード部とを備えた、リードフレームの製造方法において、８５０ＭＰａ～１１００ＭＰａの引張強度をもつ金属材料から構成される金属基板を準備する工程と、前記金属基板をエッチング加工することにより、前記金属基板に前記ダイパッドおよび前記リード部を形成する工程とを備え、前記金属基板に前記ダイパッドおよび前記リード部を形成する際、各単位リードフレームの前記リード部のうち、前記支持部材の近傍部分は、幅が７５μｍ～９０μｍとなり、厚みが６０μｍ～７５μｍとなることを特徴とするリードフレームの製造方法である。 The present invention includes a plurality of unit lead frames connected to each other via a support member, and each unit lead frame is provided around a die pad on which a semiconductor element is mounted, and the terminal portion and the terminal portion, respectively. A method of manufacturing a lead frame comprising a plurality of lead portions including an inner lead extending inward from a metal substrate, the step of preparing a metal substrate made of a metal material having a tensile strength of 850 MPa to 1100 MPa; Forming the die pad and the lead portion on the metal substrate by etching, and when forming the die pad and the lead portion on the metal substrate, of the lead portions of each unit lead frame In the vicinity of the support member, the width is 75 μm to 90 μm and the thickness is 60 μm. Is a manufacturing method of a lead frame, characterized in that the 75 [mu] m.
　本発明は、互いに支持部材を介して連結された複数の単位リードフレームを含み、各単位リードフレームは、半導体素子が搭載されるダイパッドと、前記ダイパッド周囲に設けられ、それぞれ端子部と前記端子部から内側に延びるインナーリードとを含む複数のリード部とを備えた、リードフレームの製造方法において、７５０ＭＰａ～１１００ＭＰａの引張強度をもつ金属材料から構成される金属基板を準備する工程と、前記金属基板をエッチング加工することにより、前記金属基板に前記ダイパッドおよび前記リード部を形成する工程とを備え、前記金属基板に前記ダイパッドおよび前記リード部を形成する際、各単位リードフレームの前記リード部のうち、前記支持部材の近傍部分は、幅が６０μｍ～９０μｍとなり、厚みが５０μｍ～７５μｍとなることを特徴とするリードフレームの製造方法である。 The present invention includes a plurality of unit lead frames connected to each other via a support member, and each unit lead frame is provided around a die pad on which a semiconductor element is mounted, and the terminal portion and the terminal portion, respectively. A method of manufacturing a lead frame comprising a plurality of lead portions including an inner lead extending inwardly from a metal substrate, the step of preparing a metal substrate made of a metal material having a tensile strength of 750 MPa to 1100 MPa; Forming the die pad and the lead portion on the metal substrate by etching, and when forming the die pad and the lead portion on the metal substrate, of the lead portions of each unit lead frame The vicinity of the support member has a width of 60 μm to 90 μm and a thickness of 50 μm. Is a manufacturing method of a lead frame, characterized in that the 75 [mu] m.
　本発明は、半導体装置の製造方法において、リードフレームの製造方法によりリードフレームを製造する工程と、前記リードフレームの前記ダイパッド上に前記半導体素子を搭載する工程と、前記半導体素子と各リード部の前記インナーリードとを接続部材により電気的に接続する工程と、前記ダイパッドと、前記複数のリード部と、前記半導体素子と、前記接続部材とを封止樹脂により封止する工程とを備えたことを特徴とする半導体装置の製造方法である。 The present invention relates to a method of manufacturing a semiconductor device, the step of manufacturing a lead frame by a method of manufacturing a lead frame, the step of mounting the semiconductor element on the die pad of the lead frame, the semiconductor element and each lead portion A step of electrically connecting the inner lead with a connecting member; and a step of sealing the die pad, the plurality of lead portions, the semiconductor element, and the connecting member with a sealing resin. A method for manufacturing a semiconductor device.
　本発明によれば、リード部の強度が低下することが抑えられるので、リード部に変形が生じることを防止することができ、隣接するリード部同士の間隔を狭くすることができる。 According to the present invention, since the strength of the lead portion is suppressed from being lowered, it is possible to prevent the lead portion from being deformed and to narrow the interval between the adjacent lead portions.
　本発明は、半導体装置用のリードフレームであって、半導体素子が搭載されるダイパッドと、前記ダイパッド周囲に設けられ、それぞれ第１端子部と前記第１端子部から内側に延びるインナーリードとを含む複数のリード部と、前記インナーリードの先端側に設けられ、前記ダイパッドを取り囲む接続リングとを備え、前記接続リングは、少なくとも１つの前記インナーリードによって支持され、前記接続リングに沿って凹部が規則的に設けられ、各凹部の間には厚肉部が形成されていることを特徴とするリードフレームである。 The present invention is a lead frame for a semiconductor device, comprising a die pad on which a semiconductor element is mounted, and an inner lead provided around the die pad and extending inward from the first terminal portion, respectively. A plurality of lead portions; and a connection ring that is provided on a distal end side of the inner lead and surrounds the die pad. The connection ring is supported by at least one of the inner leads, and a recess is regularly formed along the connection ring. The lead frame is characterized in that a thick portion is formed between the recesses.
　本発明によれば、インナーリードの変形を防止するとともに、外部と接続される端子部の数（ピン数）を増やすことができる。 According to the present invention, deformation of the inner lead can be prevented and the number of terminal portions (number of pins) connected to the outside can be increased.
図１は、本発明の第１の実施の形態によるリードフレームを示す平面図。FIG. 1 is a plan view showing a lead frame according to a first embodiment of the present invention. 図２は、本発明の第１の実施の形態によるリードフレームを示す底面図。FIG. 2 is a bottom view showing the lead frame according to the first embodiment of the present invention. 図３（ａ）は、本発明の第１の実施の形態によるリードフレームを示す断面図（図１のIIIA－IIIA線断面図）、図３（ｂ）は、本発明の第１の実施の形態によるリードフレームを示す断面図（図１のIIIB－IIIB線断面図）。3A is a cross-sectional view (a cross-sectional view taken along the line IIIA-IIIA in FIG. 1) of the lead frame according to the first embodiment of the present invention, and FIG. 3B is a cross-sectional view of the first embodiment of the present invention. Sectional drawing which shows the lead frame by a form (IIIB-IIIB sectional view taken on the line of FIG. 1). 図４は、本発明の第１の実施の形態による半導体装置を示す平面図。FIG. 4 is a plan view showing the semiconductor device according to the first embodiment of the present invention. 図５は、本発明の第１の実施の形態による半導体装置を示す断面図（図４のＶ－Ｖ線断面図）。FIG. 5 is a sectional view showing the semiconductor device according to the first embodiment of the present invention (a sectional view taken along line VV in FIG. 4). 図６（ａ）－（ｆ）は、本発明の第１の実施の形態によるリードフレームの製造方法を示す断面図。6 (a) to 6 (f) are cross-sectional views showing a lead frame manufacturing method according to the first embodiment of the present invention. 図７（ａ）－（ｆ）は、本発明の第１の実施の形態による半導体装置の製造方法を示す断面図。7A to 7F are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention. 図８は、本発明の第２の実施の形態によるリードフレームを示す平面図。FIG. 8 is a plan view showing a lead frame according to the second embodiment of the present invention. 図９は、本発明の第２の実施の形態によるリードフレームを示す底面図。FIG. 9 is a bottom view showing a lead frame according to a second embodiment of the present invention. 図１０（ａ）は、本発明の第２の実施の形態によるリードフレームを示す断面図（図８のXA－XA線断面図）、図１０（ｂ）は、本発明の第２の実施の形態によるリードフレームを示す断面図（図８のXB－XB線断面図）。10A is a cross-sectional view (cross-sectional view taken along the line XA-XA in FIG. 8) of the lead frame according to the second embodiment of the present invention, and FIG. 10B is a cross-sectional view of the second embodiment of the present invention. Sectional drawing which shows the lead frame by form (XB-XB sectional view taken on the line of FIG. 8). 図１１は、本発明の第２の実施の形態による半導体装置を示す平面図。FIG. 11 is a plan view showing a semiconductor device according to the second embodiment of the present invention. 図１２は、本発明の第３の実施の形態によるリードフレームを示す平面図。FIG. 12 is a plan view showing a lead frame according to the third embodiment of the present invention. 図１３は、本発明の第３の実施の形態によるリードフレームを示す底面図。FIG. 13 is a bottom view showing a lead frame according to a third embodiment of the present invention. 図１４（ａ）は、本発明の第３の実施の形態によるリードフレームを示す断面図（図１２のXIVA－XIVA線断面図）、図１４（ｂ）は、本発明の第３の実施の形態によるリードフレームを示す断面図（図１２のXIVB－XIVB線断面図）。14A is a cross-sectional view (cross-sectional view taken along the line XIVA-XIVA in FIG. 12) of the lead frame according to the third embodiment of the present invention, and FIG. 14B is a cross-sectional view of the third embodiment of the present invention. Sectional drawing which shows the lead frame by a form (XIVB-XIVB sectional view taken on the line of FIG. 12). 図１５は、本発明の第３の実施の形態による半導体装置を示す平面図。FIG. 15 is a plan view showing a semiconductor device according to the third embodiment of the present invention. 図１６は、本発明の第３の実施の形態による半導体装置を示す断面図（図１５のXVI－XVI線断面図）。FIG. 16 is a sectional view showing a semiconductor device according to the third embodiment of the present invention (cross-sectional view taken along line XVI-XVI in FIG. 15). 図１７は、本発明の第３の実施の形態の変形例によるリードフレームを示す平面図。FIG. 17 is a plan view showing a lead frame according to a modification of the third embodiment of the present invention. 図１８は、本発明の第４の実施の形態によるリードフレームを示す平面図。FIG. 18 is a plan view showing a lead frame according to the fourth embodiment of the present invention. 図１９は、本発明の第４の実施の形態によるリードフレームを示す底面図。FIG. 19 is a bottom view showing a lead frame according to the fourth embodiment of the present invention. 図２０は、本発明の第４の実施の形態による半導体装置を示す平面図。FIG. 20 is a plan view showing a semiconductor device according to the fourth embodiment of the present invention. 図２１は、本発明の第４の実施の形態の変形例によるリードフレームを示す平面図。FIG. 21 is a plan view showing a lead frame according to a modification of the fourth embodiment of the present invention. 図２２は、本発明の第５の実施の形態によるリードフレームを示す平面図。FIG. 22 is a plan view showing a lead frame according to the fifth embodiment of the present invention. 図２３は、本発明の第５の実施の形態によるリードフレームを示す断面図（図２２のXXIII－XXIII線断面図）。23 is a cross-sectional view showing a lead frame according to the fifth embodiment of the present invention (cross-sectional view taken along line XXIII-XXIII in FIG. 22). 図２４は、本発明の第５の実施の形態によるリードフレームを示す拡大平面図（図２２の部分拡大図）。FIG. 24 is an enlarged plan view showing a lead frame according to the fifth embodiment of the present invention (partial enlarged view of FIG. 22). 図２５（ａ）－（ｂ）は、リード部の断面図（それぞれ図２４のXXVA－XXVA線断面図、XXVB－XXVB線断面図）。25 (a)-(b) are cross-sectional views of the lead portion (cross-sectional views taken along the line XXVA-XXVA and XXVB-XXVB in FIG. 24, respectively). 図２６（ａ）－（ｃ）は、リード部の断面図（それぞれ図２４のXXVIA－XXVIA線断面図、XXVIB－XXVIB線断面図、XXVIC－XXVIC線断面図）。26A to 26C are cross-sectional views of the lead portion (cross-sectional view taken along line XXVIA-XXVIA, cross-sectional view taken along line XXVIB-XXVIB, and cross-sectional view taken along line XXVIC-XXVIC in FIG. 24). 図２７は、本発明の第５の実施の形態による半導体装置を示す平面図。FIG. 27 is a plan view showing a semiconductor device according to the fifth embodiment of the present invention. 図２８は、本発明の第５の実施の形態による半導体装置を示す断面図（図２７のXXVIII－XXVIII線断面図）。FIG. 28 is a sectional view showing a semiconductor device according to the fifth embodiment of the present invention (cross-sectional view taken along line XXVIII-XXVIII in FIG. 27). 図２９（ａ）－（ｆ）は、本発明の第５の実施の形態によるリードフレームの製造方法を示す断面図。29 (a)-(f) are cross-sectional views showing a method for manufacturing a lead frame according to a fifth embodiment of the present invention. 図３０（ａ）－（ｅ）は、本発明の第５の実施の形態による半導体装置の製造方法を示す断面図。30 (a) to 30 (e) are cross-sectional views showing a method of manufacturing a semiconductor device according to the fifth embodiment of the present invention. 図３１は、本発明の第６の実施の形態によるリードフレームを示す平面図。FIG. 31 is a plan view showing a lead frame according to a sixth embodiment of the present invention. 図３２（ａ）は、本発明の第６の実施の形態によるリードフレームを示す断面図（図３１のXXXIIA－XXXIIA線断面図）、図３２（ｂ）は、本発明の第６の実施の形態によるリードフレームを示す断面図（図３１のXXXIIB－XXXIIB線断面図）。FIG. 32A is a cross-sectional view (cross-sectional view taken along the line XXXIIA-XXXIIA in FIG. 31) showing a lead frame according to the sixth embodiment of the present invention, and FIG. 32B is a cross-sectional view of the sixth embodiment of the present invention. Sectional drawing which shows the lead frame by form (XXXIIB-XXXIIB sectional view taken on the line of FIG. 31). 図３３は、本発明の第６の実施の形態による半導体装置を示す平面図。FIG. 33 is a plan view showing a semiconductor device according to a sixth embodiment of the present invention. 図３４は、本発明の第６の実施の形態の変形例による半導体装置を示す平面図。FIG. 34 is a plan view showing a semiconductor device according to a modification of the sixth embodiment of the present invention.
　（第１の実施の形態）
　以下、本発明の第１の実施の形態について、図１乃至図７を参照して説明する。なお、以下の各図において、同一部分には同一の符号を付しており、一部詳細な説明を省略する場合がある。 (First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. Note that, in the following drawings, the same portions are denoted by the same reference numerals, and some detailed description may be omitted.
　リードフレームの構成
　まず、図１乃至図３により、本実施の形態によるリードフレームの概略について説明する。図１は、本実施の形態によるリードフレームを示す平面図であり、図２は、本実施の形態によるリードフレームを示す底面図である。図３（ａ）（ｂ）は、それぞれ本実施の形態によるリードフレームを示す断面図である。 Construction of the lead frame initially, to FIG. 1 to FIG. 3, the outline of the lead frame according to the present embodiment. FIG. 1 is a plan view showing a lead frame according to this embodiment, and FIG. 2 is a bottom view showing the lead frame according to this embodiment. 3A and 3B are cross-sectional views showing the lead frame according to the present embodiment, respectively.
　図１乃至図３に示すように、リードフレーム１０は、半導体素子２１（後述）を搭載するダイパッド１１と、ダイパッド１１周囲に設けられ、半導体素子２１と外部回路（図示せず）とを接続する複数の細長い外周リード部１２Ａ、１２Ｂと、ダイパッド１１と外周リード部１２Ａ、１２Ｂとの間に設けられた接続リング１４とを備えている。また、接続リング１４によって、それぞれ第２端子部１８を有する複数の内側リード部２６Ａ～２６Ｄが支持されている。 As shown in FIGS. 1 to 3, the lead frame 10 is provided around a die pad 11 on which a semiconductor element 21 (described later) is mounted, and connects the semiconductor element 21 and an external circuit (not shown). A plurality of elongated outer peripheral lead portions 12A and 12B and a connection ring 14 provided between the die pad 11 and the outer peripheral lead portions 12A and 12B are provided. A plurality of inner lead portions 26A to 26D each having the second terminal portion 18 are supported by the connection ring 14.
　このリードフレーム１０は、それぞれ半導体装置２０（後述）に対応する領域である、複数の単位リードフレーム１０ａを含んでいる。単位リードフレーム１０ａは、図１において仮想線の内側に位置する領域である。これら複数の単位リードフレーム１０ａは、支持リード（支持部材）１３を介して互いに連結されている。この支持リード１３は、ダイパッド１１と外周リード部１２Ａ、１２Ｂと接続リング１４とを支持するものであり、Ｘ方向、およびＸ方向に垂直なＹ方向に沿ってそれぞれ延びている。 The lead frame 10 includes a plurality of unit lead frames 10a, each of which corresponds to a semiconductor device 20 (described later). The unit lead frame 10a is an area located inside the virtual line in FIG. The plurality of unit lead frames 10 a are connected to each other via support leads (support members) 13. The support leads 13 support the die pad 11, the outer peripheral lead portions 12A and 12B, and the connection ring 14, and extend in the X direction and the Y direction perpendicular to the X direction.
　ダイパッド１１は、平面略矩形状であり、その４辺はＸ方向又はＹ方向のいずれかに沿って延びている。また、ダイパッド１１の四隅には、吊りリード１６が連結されている。そしてダイパッド１１は、この４本の吊りリード１６を介して支持リード１３に連結支持されている。 The die pad 11 has a substantially rectangular plane shape, and its four sides extend along either the X direction or the Y direction. Further, suspension leads 16 are connected to the four corners of the die pad 11. The die pad 11 is connected and supported to the support lead 13 through the four suspension leads 16.
　また、複数の外周リード部１２Ａ、１２Ｂは、各単位リードフレーム１０ａの外周に沿って設けられており、相対的に長い長外周リード部１２Ａと、相対的に短い短外周リード部１２Ｂとを含んでいる。本明細書において、長外周リード部１２Ａと短外周リード部１２Ｂとを合わせて外周リード部１２Ａ、１２Ｂともいう。以下、このような外周リード部１２Ａ、１２Ｂの構成について更に説明する。 The plurality of outer peripheral lead portions 12A and 12B are provided along the outer periphery of each unit lead frame 10a, and include a relatively long long outer peripheral lead portion 12A and a relatively short short outer peripheral lead portion 12B. It is out. In this specification, the long outer periphery lead portion 12A and the short outer periphery lead portion 12B are collectively referred to as outer periphery lead portions 12A and 12B. Hereinafter, the configuration of the outer peripheral lead portions 12A and 12B will be further described.
　図１乃至図３に示すように、各外周リード部１２Ａ、１２Ｂは、それぞれ接続リード５２と、第１端子部５３とを有している。このうち第１端子部５３は、その表面に内部端子１５Ａを有している。この内部端子１５Ａは、後述するようにボンディングワイヤ２２を介して半導体素子２１に電気的に接続される領域となっている。このため、内部端子１５Ａ上には、ボンディングワイヤ２２との密着性を向上させるめっき部２５が設けられている。また、接続リード５２は、第１端子部５３よりも外側（支持リード１３側）に位置しており、その基端部は支持リード１３に連結されている。この接続リード５２は、当該接続リード５２が連結される支持リード１３に対して垂直に延びている。 As shown in FIGS. 1 to 3, each of the outer peripheral lead portions 12A and 12B has a connection lead 52 and a first terminal portion 53, respectively. Among these, the 1st terminal part 53 has the internal terminal 15A on the surface. The internal terminal 15A is a region that is electrically connected to the semiconductor element 21 via a bonding wire 22 as will be described later. For this reason, the plating part 25 which improves adhesiveness with the bonding wire 22 is provided on the internal terminal 15A. Further, the connection lead 52 is located on the outer side (support lead 13 side) than the first terminal portion 53, and the base end portion thereof is coupled to the support lead 13. The connection lead 52 extends perpendicular to the support lead 13 to which the connection lead 52 is coupled.
　また、図３（ａ）（ｂ）に示すように、外周リード部１２Ａ、１２Ｂの接続リード５２は、それぞれ裏面側（半導体素子２１を搭載する面の反対側）からハーフエッチングにより薄肉に形成されている。他方、第１端子部５３は、ハーフエッチングされることなく、ダイパッド１１および支持リード１３と同一の厚みを有している。このように、接続リード５２の厚さが第１端子部５３の厚さよりも薄いことにより、幅の狭い外周リード部１２Ａ、１２Ｂを精度良く形成することができ、小型でピン数の多い半導体装置２０を得ることができる。なお、ハーフエッチングとは、被エッチング材料をその厚み方向に途中までエッチングすることをいう。 Further, as shown in FIGS. 3A and 3B, the connection leads 52 of the outer peripheral lead portions 12A and 12B are formed thin by half etching from the back surface side (opposite the surface on which the semiconductor element 21 is mounted). ing. On the other hand, the first terminal portion 53 has the same thickness as the die pad 11 and the support lead 13 without being half-etched. As described above, since the thickness of the connection lead 52 is smaller than the thickness of the first terminal portion 53, the narrow outer peripheral lead portions 12A and 12B can be formed with high accuracy, and the semiconductor device is small and has a large number of pins. 20 can be obtained. Half-etching means that the material to be etched is etched halfway in the thickness direction.
　各外周リード部１２Ａ、１２Ｂの第１端子部５３の裏面には、それぞれ外部の実装基板（図示せず）に電気的に接続される外部端子１７Ａ、１７Ｂが形成されている。各外部端子１７Ａ、１７Ｂは、半導体装置２０（後述）の製造後に、それぞれ半導体装置２０から外方に露出するようになっている。 External terminals 17A and 17B that are electrically connected to external mounting boards (not shown) are formed on the back surfaces of the first terminal portions 53 of the outer peripheral lead portions 12A and 12B, respectively. The external terminals 17A and 17B are exposed outward from the semiconductor device 20 after the semiconductor device 20 (described later) is manufactured.
　これら第１端子部５３のうち、長外周リード部１２Ａの第１端子部５３は、相対的に内側（ダイパッド１１側）に位置しており、短外周リード部１２Ｂの第１端子部５３は、相対的に外側（支持リード１３側）に位置している。 Among these first terminal portions 53, the first terminal portion 53 of the long outer periphery lead portion 12A is located relatively inside (on the die pad 11 side), and the first terminal portion 53 of the short outer periphery lead portion 12B is It is located relatively outside (support lead 13 side).
　また、外周リード部１２Ａ、１２Ｂの外部端子１７Ａ、１７Ｂは、隣り合う外周リード部１２Ａ、１２Ｂ間で内側および外側に位置するよう、平面から見て交互に千鳥状に配置されている。すなわち、ダイパッド１１の周囲において、相対的に内側（ダイパッド１１側）に位置する外部端子（内側外部端子）１７Ａをもつ長外周リード部１２Ａと、相対的に外側（支持リード１３側）に位置する外部端子（外側外部端子）１７Ｂをもつ短外周リード部１２Ｂとが、支持リード１３の各辺に沿って交互に配置されている。これにより、外周リード部１２Ａと１２Ｂを近接して設けた場合でも、外部端子１７Ａと１７Ｂが接触する不具合が防止される。この場合、外部端子１７Ａおよび外部端子１７Ｂは、全て同一の平面形状を有している。 Further, the external terminals 17A and 17B of the outer peripheral lead portions 12A and 12B are alternately arranged in a staggered manner when viewed from the plane so as to be located inside and outside between the adjacent outer peripheral lead portions 12A and 12B. That is, in the periphery of the die pad 11, the outer peripheral lead portion 12 </ b> A having the external terminal (inner external terminal) 17 </ b> A positioned relatively inside (die pad 11 side) and relatively outside (support lead 13 side). Short outer peripheral lead portions 12B having external terminals (outside external terminals) 17B are alternately arranged along each side of the support lead 13. Thereby, even when the outer peripheral lead portions 12A and 12B are provided close to each other, a problem that the external terminals 17A and 17B come into contact with each other is prevented. In this case, the external terminal 17A and the external terminal 17B all have the same planar shape.
　さらに、図２に示すように、複数の外部端子１７Ａは、平面から見ていずれもダイパッド１１の一辺に対して平行な直線に沿って配列されている。同様に、複数の外部端子１７Ｂは、平面から見ていずれもダイパッド１１の一辺に対して平行な直線に沿って配列されている。すなわち、複数の外部端子１７Ａ、１７Ｂは、Ｘ方向又はＹ方向のいずれかに対して平行な直線に沿って、２列に配列されている。 Further, as shown in FIG. 2, the plurality of external terminals 17A are all arranged along a straight line parallel to one side of the die pad 11 when viewed from above. Similarly, the plurality of external terminals 17B are all arranged along a straight line parallel to one side of the die pad 11 when viewed from the plane. That is, the plurality of external terminals 17A and 17B are arranged in two rows along a straight line parallel to either the X direction or the Y direction.
　この場合、互いに隣接する外周リード部１２Ａ、１２Ｂ間の間隔は、９０μｍ～１５０μｍとすることが好ましい。このように、外周リード部１２Ａ、１２Ｂ間の間隔を９０μｍ以上とすることにより、互いに隣接する外周リード部１２Ａ、１２Ｂ間の貫通部分をエッチングにより確実に形成することができる。また、上記間隔を１５０μｍ以下とすることにより、各半導体装置２０の外部端子１７Ａ、１７Ｂの数（ピン数）を一定数以上確保することができる。 In this case, the interval between the outer peripheral lead portions 12A and 12B adjacent to each other is preferably 90 μm to 150 μm. As described above, by setting the distance between the outer peripheral lead portions 12A and 12B to 90 μm or more, the through portion between the adjacent outer peripheral lead portions 12A and 12B can be reliably formed by etching. Further, by setting the interval to 150 μm or less, the number of external terminals 17A and 17B (number of pins) of each semiconductor device 20 can be secured at a certain number or more.
　次に、接続リング１４および内側リード部２６Ａ～２６Ｄの構成について説明する。 Next, the configuration of the connection ring 14 and the inner lead portions 26A to 26D will be described.
　図１および図２に示すように、接続リング１４は、外周リード部１２Ａ、１２Ｂの先端側において、ダイパッド１１を取り囲むように配置されている。この接続リング１４は、全体として略矩形形状を有しており、その各辺はＸ方向又はＹ方向に沿って延びている。接続リング１４の四隅にはそれぞれ吊りリード１６が連結されており、接続リング１４は、４本の吊りリード１６を介して支持リード１３に支持されている。 As shown in FIGS. 1 and 2, the connection ring 14 is disposed so as to surround the die pad 11 on the distal end side of the outer peripheral lead portions 12A and 12B. The connection ring 14 has a substantially rectangular shape as a whole, and each side thereof extends along the X direction or the Y direction. Suspension leads 16 are coupled to the four corners of the connection ring 14, and the connection ring 14 is supported by the support leads 13 via the four suspension leads 16.
　接続リング１４の表面には、接続リング１４の長手方向に沿って凹溝１４ａが形成されている。この凹溝１４ａは、ハーフエッチングにより形成されたものであり、厚み方向に貫通することなく一定の深さを持っている。また、凹溝１４ａは、接続リング１４の幅方向略中央部に形成されており、凹溝１４ａの幅方向両側には、ハーフエッチングされていない土手部１４ｂが形成されている。この場合、接続リング１４の長手方向に垂直な断面は、略凹字形状又は略Ｕ字形状となっている。なお、本実施の形態において、凹溝１４ａは、接続リング１４の四隅を除く全周に設けられているが、これに限らず、例えば接続リング１４の四隅を含む全周にわたって設けられていても良い。また、接続リング１４に凹溝１４が設けられておらず、接続リング１４の全体が金属基板の板厚のままの状態であってもよい。 A concave groove 14 a is formed on the surface of the connection ring 14 along the longitudinal direction of the connection ring 14. The concave groove 14a is formed by half etching, and has a certain depth without penetrating in the thickness direction. Further, the concave groove 14a is formed at a substantially central portion in the width direction of the connection ring 14, and bank portions 14b that are not half-etched are formed on both sides in the width direction of the concave groove 14a. In this case, the cross section perpendicular to the longitudinal direction of the connection ring 14 is substantially concave or U-shaped. In the present embodiment, the concave grooves 14a are provided on the entire circumference except for the four corners of the connection ring 14. However, the present invention is not limited thereto, and may be provided on the entire circumference including the four corners of the connection ring 14, for example. good. Moreover, the concave groove 14 is not provided in the connection ring 14, and the whole connection ring 14 may be in the state with the plate | board thickness of a metal board | substrate.
　このように凹溝１４ａを設けたことにより、接続リング１４の体積が減らされるので、後述するように、複数の第２端子部１８を個別に分離する際、接続リング１４をエッチングにより除去しやすくなっている。 Since the volume of the connection ring 14 is reduced by providing the concave groove 14a in this manner, the connection ring 14 can be easily removed by etching when the plurality of second terminal portions 18 are individually separated, as will be described later. It has become.
　一方、接続リング１４からは、複数の内側リード部２６Ａ～２６Ｄがそれぞれ延出している。これら複数の内側リード部２６Ａ～２６Ｄは、相対的に長い長内側リード部２６Ａ、２６Ｃと、相対的に短い短内側リード部２６Ｂ、２６Ｄとを含んでいる。本明細書において、長内側リード部２６Ａ、２６Ｃと短内側リード部２６Ｂ、２６Ｄとを合わせて内側リード部２６Ａ～２６Ｄともいう。 On the other hand, a plurality of inner lead portions 26A to 26D extend from the connection ring 14, respectively. The plurality of inner lead portions 26A to 26D include relatively long long inner lead portions 26A and 26C and relatively short short inner lead portions 26B and 26D. In this specification, the long inner lead portions 26A and 26C and the short inner lead portions 26B and 26D are collectively referred to as inner lead portions 26A to 26D.
　各内側リード部２６Ａ～２６Ｄは、それぞれその先端に第２端子部１８を有している。第２端子部１８は、後述するように、ボンディングワイヤ２２を介して半導体素子２１に接続されるものである。 Each inner lead portion 26A to 26D has a second terminal portion 18 at the tip thereof. The second terminal portion 18 is connected to the semiconductor element 21 via a bonding wire 22 as will be described later.
　また、複数の第２端子部１８は、接続リング１４に沿って互いに間隔を空けて配列されており、それぞれ接続リング１４に連結支持されている。この第２端子部１８は、後述するように半導体装置２０を作製する際、接続リング１４を除去した後、互いに個別に分離される。すなわち、各第２端子部１８は、接続リング１４を除去した後、ダイパッド１１、接続リング１４および他の第２端子部１８のいずれからも分離されるようになっている。 Further, the plurality of second terminal portions 18 are arranged along the connection ring 14 at intervals, and are connected and supported by the connection ring 14 respectively. As will be described later, the second terminal portions 18 are separated from each other after the connection ring 14 is removed when the semiconductor device 20 is manufactured. That is, each second terminal portion 18 is separated from any of the die pad 11, the connection ring 14, and the other second terminal portions 18 after removing the connection ring 14.
　これら複数の第２端子部１８のうち、長内側リード部２６Ａ、２６Ｃの第２端子部１８は、相対的に接続リング１４から離間した部分に位置しており、短内側リード部２６Ｂ、２６Ｄの第２端子部１８は、相対的に接続リング１４に近接した部分に位置している。 Among the plurality of second terminal portions 18, the second terminal portions 18 of the long inner lead portions 26A and 26C are located in a portion relatively separated from the connection ring 14, and the short inner lead portions 26B and 26D. The second terminal portion 18 is located in a portion relatively close to the connection ring 14.
　また、複数の内側リード部２６Ａ～２６Ｄのうち、長内側リード部２６Ａと短内側リード部２６Ｂとは、それぞれ接続リング１４の外側（支持リード１３側）から延びている。これら長内側リード部２６Ａと短内側リード部２６Ｂとは、接続リング１４の外側において交互に配置されている。 Of the plurality of inner lead portions 26A to 26D, the longer inner lead portion 26A and the shorter inner lead portion 26B each extend from the outer side of the connection ring 14 (the support lead 13 side). The long inner lead portions 26 </ b> A and the short inner lead portions 26 </ b> B are alternately arranged outside the connection ring 14.
　一方、長内側リード部２６Ｃと短内側リード部２６Ｄとは、それぞれ接続リング１４の内側（ダイパッド１１側）から延びている。これら長内側リード部２６Ｃと短内側リード部２６Ｄとは、接続リング１４の内側において交互に配置されている。 On the other hand, the long inner lead portion 26C and the short inner lead portion 26D extend from the inner side (die pad 11 side) of the connection ring 14, respectively. These long inner lead portions 26 </ b> C and short inner lead portions 26 </ b> D are alternately arranged inside the connection ring 14.
　図３（ａ）に示すように、各内側リード部２６Ａ～２６Ｄは、それぞれ接続リング１４に連結される接続リード５７を有しており、各接続リード５７は、裏面側から薄肉化されている。このように、各内側リード部２６Ａ～２６Ｄの接続リード５７を薄肉化したことにより、封止樹脂２３により樹脂封止した後、裏面側から接続リード５７に向けて封止樹脂２３が進入する（図５参照）。これにより、接続リング１４をエッチングにより除去した後、第２端子部１８が裏面側に脱落する不具合を防止することができる。 As shown in FIG. 3A, each of the inner lead portions 26A to 26D has a connection lead 57 coupled to the connection ring 14, and each connection lead 57 is thinned from the back side. . Thus, by thinning the connection leads 57 of the inner lead portions 26A to 26D, the sealing resin 23 enters from the back side toward the connection leads 57 after sealing with the sealing resin 23 ( (See FIG. 5). Thereby, after removing the connection ring 14 by etching, it is possible to prevent the second terminal portion 18 from dropping off to the back surface side.
　また、各第２端子部１８は、表面側に設けられた内部端子１５Ｂと、裏面側に設けられた外部端子１７Ｃ～１７Ｆとを有している。このうち内部端子１５Ｂは、ボンディングワイヤ２２を介して半導体素子２１に電気的に接続されるものである。なお、内部端子１５Ｂ上には、内部端子１５Ａと同様、ボンディングワイヤ２２との密着性を向上させるためのめっき部２５が設けられている。また外部端子１７Ｃ～１７Ｆは、外部の実装基板（図示せず）に電気的に接続されるものであり、それぞれ内側リード部２６Ａ～２６Ｄの先端に設けられている。 Each second terminal portion 18 has an internal terminal 15B provided on the front surface side and external terminals 17C to 17F provided on the back surface side. Among these, the internal terminal 15 </ b> B is electrically connected to the semiconductor element 21 through the bonding wire 22. In addition, the plating part 25 for improving adhesiveness with the bonding wire 22 is provided on the internal terminal 15B like the internal terminal 15A. The external terminals 17C to 17F are electrically connected to an external mounting board (not shown), and are provided at the tips of the inner lead portions 26A to 26D, respectively.
　図２に示すように、接続リング１４の外側（支持リード１３側）に位置する内側リード部２６Ａ、２６Ｂの外部端子１７Ｃ、１７Ｄは、隣り合う内側リード部２６Ａ、２６Ｂ間で内側および外側に位置するよう、平面から見て交互に千鳥状に配置されている。すなわち、ダイパッド１１の周囲において、相対的に内側（ダイパッド１１側）に位置する外部端子１７Ｄと、相対的に外側（支持リード１３側）に位置する外部端子１７Ｃとが、接続リング１４の各辺に沿って交互に配置されている。これにより、内側リード部２６Ａと２６Ｂを近接して設けた場合でも、外部端子１７Ｃと１７Ｄが接触する不具合が防止される。 As shown in FIG. 2, the external terminals 17C and 17D of the inner lead portions 26A and 26B located on the outer side (support lead 13 side) of the connection ring 14 are located on the inner and outer sides between the adjacent inner lead portions 26A and 26B. Thus, they are alternately arranged in a staggered manner when viewed from above. That is, in the periphery of the die pad 11, the external terminal 17 </ b> D positioned relatively on the inner side (die pad 11 side) and the external terminal 17 </ b> C positioned relatively on the outer side (support lead 13 side) are connected to each side of the connection ring 14. Are arranged alternately. Thereby, even when the inner lead portions 26A and 26B are provided close to each other, a problem that the external terminals 17C and 17D come into contact with each other is prevented.
　同様に、接続リング１４の内側（ダイパッド１１側）に位置する内側リード部２６Ｃ、２６Ｄの外部端子１７Ｅ、１７Ｆは、隣り合う内側リード部２６Ｃ、２６Ｄ間で内側および外側に位置するよう、平面から見て交互に千鳥状に配置されている。すなわち、ダイパッド１１の周囲において、相対的に内側（ダイパッド１１側）に位置する外部端子１７Ｅと、相対的に外側（支持リード１３側）に位置する外部端子１７Ｆとが、接続リング１４の各辺に沿って交互に配置されている。これにより、内側リード部２６Ｃと２６Ｄを近接して設けた場合でも、外部端子１７Ｅと１７Ｆが接触する不具合が防止される。 Similarly, the external terminals 17E and 17F of the inner lead portions 26C and 26D located on the inner side (die pad 11 side) of the connection ring 14 are arranged so as to be located on the inner side and the outer side between the adjacent inner lead portions 26C and 26D. It is arranged in a staggered pattern alternately. That is, around the die pad 11, the external terminals 17 </ b> E positioned relatively on the inner side (die pad 11 side) and the external terminals 17 </ b> F positioned relatively on the outer side (support lead 13 side) are connected to each side of the connection ring 14. Are arranged alternately. Thereby, even when the inner lead portions 26C and 26D are provided close to each other, a problem that the external terminals 17E and 17F come into contact with each other is prevented.
　上述した複数の外部端子１７Ｃ～１７Ｆは、平面から見ていずれもダイパッド１１の一辺に対して平行な直線に沿って配列されている。すなわち、複数の外部端子１７Ｃ～１７Ｆは、Ｘ方向又はＹ方向のいずれかに対して平行な直線に沿って、４列に配列されている。 The plurality of external terminals 17C to 17F described above are all arranged along a straight line parallel to one side of the die pad 11 when viewed from above. That is, the plurality of external terminals 17C to 17F are arranged in four rows along a straight line parallel to either the X direction or the Y direction.
　また、接続リング１４の外側から延びる短内側リード部２６Ｂと、長外周リード部１２Ａとが互いに向かい合い、接続リング１４の外側から延びる長内側リード部２６Ａと、短外周リード部１２Ｂとが互いに向かい合っている。これにより、外部端子１７Ａと外部端子１７Ｄとの間の端子間距離と、外部端子１７Ｂと外部端子１７Ｃとの間の端子間距離とを確保することができ、これらの端子同士が接触する不具合を防止することができる。 Further, the short inner lead portion 26B extending from the outside of the connection ring 14 and the long outer peripheral lead portion 12A face each other, and the long inner lead portion 26A extending from the outer side of the connection ring 14 and the short outer peripheral lead portion 12B face each other. Yes. Thereby, the inter-terminal distance between the external terminal 17A and the external terminal 17D and the inter-terminal distance between the external terminal 17B and the external terminal 17C can be ensured, and there is a problem that these terminals are in contact with each other. Can be prevented.
　以上説明したリードフレーム１０は、全体として銅、銅合金、４２合金（Ｎｉ４２％のＦｅ合金）等の金属から構成されている。また、リードフレーム１０の厚みは、製造する半導体装置２０の構成にもよるが、８０μｍ～２５０μｍとすることができる。またリードフレーム１０は、７５０Ｍｐａ～１１００Ｍｐａの引っ張り強度をもつ金属材料から構成されていることが好ましい。本実施の形態のような多ピン構造のリードフレーム１０においては、リード部１２Ａ、１２Ｂ、２６Ａ～２６Ｄを従来のものよりも細くする必要があるが、上記のような金属からこれを作成することで、細くても変形しにくいリード部１２Ａ、１２Ｂ、２６Ａ～２６Ｄを有するリードフレーム１０を得ることができる。 The lead frame 10 described above is made of a metal such as copper, copper alloy, 42 alloy (Ni 42% Fe alloy) as a whole. The lead frame 10 may have a thickness of 80 μm to 250 μm, although it depends on the configuration of the semiconductor device 20 to be manufactured. The lead frame 10 is preferably made of a metal material having a tensile strength of 750 Mpa to 1100 Mpa. In the lead frame 10 having a multi-pin structure as in the present embodiment, the lead portions 12A, 12B, and 26A to 26D need to be made thinner than the conventional one, but this should be made from the metal as described above. Thus, it is possible to obtain the lead frame 10 having the lead portions 12A, 12B, and 26A to 26D that are thin and hardly deformed.
　なお、図１において、外周リード部１２Ａ、１２Ｂおよび内側リード部２６Ａ～２６Ｄは、それぞれダイパッド１１の４辺全てに沿って配置されているが、これに限られるものではなく、例えばダイパッド１１の対向する２辺のみに沿って配置されていても良い。また、内側リード部２６Ａ～２６Ｄは、接続リング１４の外側（支持リード１３側）および内側（ダイパッド１１側）の両方から延びているが、これに限られるものではなく、接続リング１４の外側又は内側の一方のみから延びていても良い。 In FIG. 1, the outer peripheral lead portions 12A and 12B and the inner lead portions 26A to 26D are arranged along all four sides of the die pad 11, but the present invention is not limited to this. It may be arranged along only two sides. The inner lead portions 26A to 26D extend from both the outer side (support lead 13 side) and the inner side (die pad 11 side) of the connection ring 14. However, the present invention is not limited to this. You may extend only from one side inside.
　半導体装置の構成
　次に、図４および図５により、本実施の形態による半導体装置について説明する。図４および図５は、本実施の形態による半導体装置（ＤＲ－ＱＦＮ（Dual Row QFN）タイプ）を示す図である。 Configuration of Semiconductor Device Next, the semiconductor device according to the present embodiment will be described with reference to FIGS. 4 and 5 are diagrams showing a semiconductor device (DR-QFN (Dual Row QFN) type) according to the present embodiment.
　図４および図５に示すように、半導体装置（半導体パッケージ）２０は、ダイパッド１１と、ダイパッド１１の周囲に配置された複数の外周リード部１２Ａ、１２Ｂと、ダイパッド１１と外周リード部１２Ａ、１２Ｂとの間に配置された複数の第２端子部１８とを備えている。このうちダイパッド１１上に半導体素子２１が搭載され、半導体素子２１と各外周リード部１２Ａ、１２Ｂの第１端子部５３および各内側リード部２６Ａ～２６Ｄの第２端子部１８とは、それぞれボンディングワイヤ（接続部材）２２によって電気的に接続されている。また、ダイパッド１１、外周リード部１２Ａ、１２Ｂ、第２端子部１８、半導体素子２１およびボンディングワイヤ２２は、封止樹脂２３によって樹脂封止されている。 As shown in FIGS. 4 and 5, the semiconductor device (semiconductor package) 20 includes a die pad 11, a plurality of outer peripheral lead portions 12A and 12B arranged around the die pad 11, and the die pad 11 and the outer peripheral lead portions 12A and 12B. And a plurality of second terminal portions 18 disposed between them. Among these, the semiconductor element 21 is mounted on the die pad 11, and the semiconductor element 21, the first terminal portion 53 of each of the outer peripheral lead portions 12A and 12B, and the second terminal portion 18 of each of the inner lead portions 26A to 26D are each bonded to a bonding wire. (Connecting member) 22 is electrically connected. Further, the die pad 11, the outer peripheral lead portions 12 </ b> A and 12 </ b> B, the second terminal portion 18, the semiconductor element 21, and the bonding wire 22 are resin-sealed with a sealing resin 23.
　このうちダイパッド１１、外周リード部１２Ａ、１２Ｂおよび内側リード部２６Ａ～２６Ｄは、上述したリードフレーム１０から作製されたものである。このダイパッド１１、外周リード部１２Ａ、１２Ｂおよび内側リード部２６Ａ～２６Ｄの構成は、単位リードフレーム１０ａに含まれない領域を除き、上述した図１乃至図３に示すものと略同様であり、ここでは詳細な説明を省略する。 Among these, the die pad 11, the outer peripheral lead portions 12A and 12B, and the inner lead portions 26A to 26D are manufactured from the lead frame 10 described above. The configurations of the die pad 11, the outer periphery lead portions 12A and 12B, and the inner lead portions 26A to 26D are substantially the same as those shown in FIGS. 1 to 3 except for the region not included in the unit lead frame 10a. Then, detailed description is abbreviate | omitted.
　一方、上述した接続リング１４は、封止樹脂２３によって樹脂封止された後、裏面側からエッチングにより除去されている。このため、図４および図５に示すように、各内側リード部２６Ａ～２６Ｄの第２端子部１８は、ダイパッド１１、外周リード部１２Ａ、１２Ｂおよび他の第２端子部１８から分離されており、これらの部材から電気的に独立している。 On the other hand, the connection ring 14 described above is resin-sealed with a sealing resin 23 and then removed from the back side by etching. Therefore, as shown in FIGS. 4 and 5, the second terminal portions 18 of the inner lead portions 26A to 26D are separated from the die pad 11, the outer peripheral lead portions 12A and 12B, and the other second terminal portions 18. Electrically independent of these members.
　このように、接続リング１４が除去されたことに伴い、封止樹脂２３の裏面のうち、外周リード部１２Ａ、１２Ｂとダイパッド１１との間であって、内側リード部２６Ａ、２６Ｂと内側リード部２６Ｃ、２６Ｄとの間の領域に、凹部２７が形成されている。この凹部２７は、接続リング１４の形状に概ね対応しており、ダイパッド１１を取り囲むように平面矩形形状を有している。なお、凹部２７内において、封止樹脂２３の一部からなる突起部２７ａが突出している（図５参照）。この突起部２７ａは、上述した接続リング１４の凹溝１４ａに対応する形状を有している。なお、凹部２７には、封止樹脂２３と同じあるいは別の種類の絶縁性樹脂が充填されていても良い。 As described above, with the removal of the connection ring 14, the inner lead portions 26 </ b> A and 26 </ b> B and the inner lead portion between the outer peripheral lead portions 12 </ b> A and 12 </ b> B and the die pad 11 on the back surface of the sealing resin 23. A recess 27 is formed in a region between 26C and 26D. The recess 27 substantially corresponds to the shape of the connection ring 14 and has a planar rectangular shape so as to surround the die pad 11. In addition, in the recessed part 27, the protrusion part 27a which consists of a part of sealing resin 23 protrudes (refer FIG. 5). The protrusion 27a has a shape corresponding to the concave groove 14a of the connection ring 14 described above. The recess 27 may be filled with the same or different type of insulating resin as the sealing resin 23.
　一方、半導体素子２１としては、従来一般に用いられている各種半導体素子を使用することが可能であり、特に限定されないが、例えば集積回路、大規模集積回路、トランジスタ、サイリスタ、ダイオード等を用いることができる。この半導体素子２１は、各々ボンディングワイヤ２２が取り付けられる複数の電極２１ａを有している。また、半導体素子２１は、例えばダイボンディングペースト等の接着剤２４により、ダイパッド１１の表面に固定されている。 On the other hand, as the semiconductor element 21, various semiconductor elements generally used in the past can be used, and are not particularly limited. For example, an integrated circuit, a large-scale integrated circuit, a transistor, a thyristor, a diode, or the like is used. it can. The semiconductor element 21 has a plurality of electrodes 21a to which bonding wires 22 are attached. The semiconductor element 21 is fixed to the surface of the die pad 11 with an adhesive 24 such as a die bonding paste.
　各ボンディングワイヤ２２は、例えば金、銅等の導電性の良い材料からなっている。各ボンディングワイヤ２２は、それぞれその一端が半導体素子２１の電極２１ａに接続されるとともに、その他端が各外周リード部１２Ａ、１２Ｂの内部端子１５Ａ又は第２端子部１８の内部端子１５Ｂにそれぞれ接続されている。なお、内部端子１５Ａ、１５Ｂには、ボンディングワイヤ２２と密着性を向上させるめっき部２５がそれぞれ設けられている。 Each bonding wire 22 is made of a material having good conductivity such as gold or copper. Each bonding wire 22 has one end connected to the electrode 21a of the semiconductor element 21 and the other end connected to the internal terminal 15A of each of the outer peripheral lead portions 12A and 12B or the internal terminal 15B of the second terminal portion 18. ing. The internal terminals 15 </ b> A and 15 </ b> B are each provided with a plating portion 25 that improves the adhesion with the bonding wire 22.
　封止樹脂２３としては、シリコーン樹脂やエポキシ樹脂等の熱硬化性樹脂、あるいはＰＰＳ樹脂等の熱可塑性樹脂を用いることができる。封止樹脂２３全体の厚みは、５００μｍ～１０００μｍ程度とすることができる。なお、図４において、ダイパッド１１、外周リード部１２Ａ、１２Ｂおよび内側リード部２６Ａ～２６Ｄよりも表面側に位置する封止樹脂２３の表示を省略している。 As the sealing resin 23, a thermosetting resin such as a silicone resin or an epoxy resin, or a thermoplastic resin such as a PPS resin can be used. The total thickness of the sealing resin 23 can be about 500 μm to 1000 μm. In FIG. 4, the display of the sealing resin 23 located on the surface side of the die pad 11, the outer peripheral lead portions 12A and 12B, and the inner lead portions 26A to 26D is omitted.
　なお、半導体装置２０の一辺は、例えば８ｍｍ～１６ｍｍとしても良い。 Note that one side of the semiconductor device 20 may be, for example, 8 mm to 16 mm.
　リードフレームの製造方法
　次に、図１乃至図３に示すリードフレーム１０の製造方法について、図６（ａ）－（ｆ）を用いて説明する。なお、図６（ａ）－（ｆ）は、リードフレーム１０の製造方法を示す断面図（図３（ｂ）に対応する図）である。 Method for Manufacturing Lead Frame Next, a method for manufacturing the lead frame 10 shown in FIGS. 1 to 3 will be described with reference to FIGS. 6A to 6F are cross-sectional views (a diagram corresponding to FIG. 3B) showing a method for manufacturing the lead frame 10. FIG.
　まず図６（ａ）に示すように、平板状の金属基板３１を準備する。この金属基板３１としては、銅、銅合金、４２合金（Ｎｉ４２％のＦｅ合金）等の金属からなる基板を使用することができる。なお金属基板３１は、その両面に対して脱脂等を行い、洗浄処理を施したものを使用することが好ましい。 First, as shown in FIG. 6A, a flat metal substrate 31 is prepared. As the metal substrate 31, a substrate made of a metal such as copper, a copper alloy, or a 42 alloy (Ni 42% Fe alloy) can be used. In addition, it is preferable to use what the metal substrate 31 performed the degreasing | defatting etc. to the both surfaces, and performed the washing process.
　次に、金属基板３１の表裏全体にそれぞれ感光性レジスト３２ａ、３３ａを塗布し、これを乾燥する（図６（ｂ））。なお感光性レジスト３２ａ、３３ａとしては、従来公知のものを使用することができる。 Next, photosensitive resists 32a and 33a are applied to the entire front and back surfaces of the metal substrate 31, respectively, and dried (FIG. 6B). As the photosensitive resists 32a and 33a, conventionally known resists can be used.
　続いて、この金属基板３１に対してフォトマスクを介して露光し、現像することにより、所望の開口部３２ｂ、３３ｂを有するエッチング用レジスト層３２、３３を形成する（図６（ｃ））。 Subsequently, the metal substrate 31 is exposed through a photomask and developed to form etching resist layers 32 and 33 having desired openings 32b and 33b (FIG. 6C).
　次に、エッチング用レジスト層３２、３３を耐腐蝕膜として金属基板３１に腐蝕液でエッチングを施す（図６（ｄ））。これにより、ダイパッド１１、複数の外周リード部１２Ａ、１２Ｂ、接続リング１４、および複数の内側リード部２６Ａ～２６Ｄの外形が形成される。腐蝕液は、使用する金属基板３１の材質に応じて適宜選択することができ、例えば、金属基板３１として銅合金を用いる場合、通常、塩化第二鉄水溶液を使用し、金属基板３１の両面からスプレーエッチングにて行うことができる。 Next, etching is performed on the metal substrate 31 with a corrosive solution using the etching resist layers 32 and 33 as corrosion resistant films (FIG. 6D). Thereby, the outer shape of the die pad 11, the plurality of outer peripheral lead portions 12A and 12B, the connection ring 14, and the plurality of inner lead portions 26A to 26D is formed. The corrosive liquid can be appropriately selected according to the material of the metal substrate 31 to be used. For example, when a copper alloy is used as the metal substrate 31, a ferric chloride aqueous solution is usually used from both sides of the metal substrate 31. It can be performed by spray etching.
　その後、エッチング用レジスト層３２、３３を剥離して除去する（図６（ｅ））。 Thereafter, the etching resist layers 32 and 33 are peeled off and removed (FIG. 6E).
　なお、上記においては、金属基板３１の両面側からスプレーエッチングを行う場合を例にとって説明したが、これに限られるものではない。例えば、金属基板３１の片面ずつ２段階のスプレーエッチングを行っても良い。具体的には、まず所定のパターンをもつエッチング用レジスト層３２、３３を形成し（図６（ｃ）参照）、その後、金属基板３１の裏面側に耐エッチング性のある封止層（図示せず）を設け、この状態で金属基板３１の表面側のみエッチングを実施する。次いで、当該裏面側の封止層を剥離し、金属基板３１の表面側に封止層（図示せず）を設ける。このとき、表面側の封止層は、エッチング加工された金属基板３１の表面側の凹部内にも進入する。続いて、金属基板３１の露出した裏面のみをエッチングし、その後表面側の封止層を剥離することにより、ダイパッド１１、複数の外周リード部１２Ａ、１２Ｂ、接続リング１４、および複数の内側リード部２６Ａ～２６Ｄの外形が形成される。このように金属基板３１の片面ずつスプレーエッチングを行うことにより、外周リード部１２Ａ、１２Ｂおよび内側リード部２６Ａ～２６Ｄの変形を回避しやすいという効果が得られる。 In the above description, the case where the spray etching is performed from both sides of the metal substrate 31 has been described as an example. However, the present invention is not limited to this. For example, two stages of spray etching may be performed for each side of the metal substrate 31. Specifically, first, resist layers 32 and 33 for etching having a predetermined pattern are formed (see FIG. 6C), and then an etching-resistant sealing layer (not shown) is formed on the back side of the metal substrate 31. In this state, only the surface side of the metal substrate 31 is etched. Next, the sealing layer on the back side is peeled off, and a sealing layer (not shown) is provided on the front side of the metal substrate 31. At this time, the sealing layer on the surface side also enters the recess on the surface side of the etched metal substrate 31. Subsequently, by etching only the exposed back surface of the metal substrate 31, and then peeling off the sealing layer on the front surface side, the die pad 11, the plurality of outer peripheral lead portions 12A and 12B, the connection ring 14, and the plurality of inner lead portions. 26A to 26D are formed. By performing spray etching on each side of the metal substrate 31 in this way, it is possible to easily avoid the deformation of the outer peripheral lead portions 12A and 12B and the inner lead portions 26A to 26D.
　次に、ボンディングワイヤ２２と各内部端子１５Ａ、１５Ｂとの密着性を向上させるため、各内部端子１５Ａ、１５Ｂにそれぞれメッキ処理を施し、めっき部２５を形成する（図６（ｆ））。この場合、選択されるメッキ種は、ボンディングワイヤ２２との密着性を確保できればその種類は問わないが、たとえばＡｇやＡｕなどの単層めっきでもよいし、Ｎｉ／ＰｄやＮｉ／Ｐｄ／Ａｕがこの順に積層される複層めっきでもよい。また、めっき部２５は、外周リード部１２Ａ、１２Ｂおよび内側リード部２６Ａ～２６Ｄのうちボンディングワイヤ２２との接続部のみに施してもよいし、リードフレーム１０の全面に施してもよい。 Next, in order to improve the adhesion between the bonding wire 22 and the internal terminals 15A and 15B, the internal terminals 15A and 15B are respectively plated to form the plated portions 25 (FIG. 6F). In this case, the type of plating selected is not limited as long as the adhesion to the bonding wire 22 can be ensured. For example, single-layer plating such as Ag or Au may be used, or Ni / Pd or Ni / Pd / Au may be used. Multi-layer plating laminated in this order may be used. Further, the plating portion 25 may be provided only on the connection portion with the bonding wire 22 among the outer peripheral lead portions 12A and 12B and the inner lead portions 26A to 26D, or may be provided on the entire surface of the lead frame 10.
　このようにして、図１乃至図３に示すリードフレーム１０が得られる。 In this way, the lead frame 10 shown in FIGS. 1 to 3 is obtained.
　半導体装置の製造方法
　次に、図４および図５に示す半導体装置２０の製造方法について、図７（ａ）－（ｆ）を用いて説明する。図７（ａ）－（ｆ）は、半導体装置２０の製造方法を示す断面図（図５に対応する図）である。 Manufacturing Method of Semiconductor Device Next, a manufacturing method of the semiconductor device 20 shown in FIGS. 4 and 5 will be described with reference to FIGS. 7A to 7F are cross-sectional views (corresponding to FIG. 5) showing the method for manufacturing the semiconductor device 20.
　まず、例えば図６（ａ）－（ｆ）に示す方法（上述）により、リードフレーム１０を作製する。 First, for example, the lead frame 10 is manufactured by the method shown in FIGS. 6A to 6F (described above).
　次に、リードフレーム１０のダイパッド１１上に、半導体素子２１を搭載する。この場合、例えばダイボンディングペースト等の接着剤２４を用いて、半導体素子２１をダイパッド１１上に載置して固定する（ダイアタッチ工程）（図７（ａ））。 Next, the semiconductor element 21 is mounted on the die pad 11 of the lead frame 10. In this case, for example, the semiconductor element 21 is mounted on the die pad 11 and fixed using an adhesive 24 such as a die bonding paste (FIG. 7A).
　次に、半導体素子２１の各電極２１ａと、各外周リード部１２Ａ、１２Ｂのめっき部２５（内部端子１５Ａ）とを、それぞれボンディングワイヤ（接続部材）２２によって互いに電気的に接続する。同様に、半導体素子２１の各電極２１ａと、各内側リード部２６Ａ～２６Ｄのめっき部２５（内部端子１５Ｂ）とを、それぞれボンディングワイヤ（接続部材）２２によって互いに電気的に接続する（ワイヤボンディング工程）（図７（ｂ））。 Next, the electrodes 21a of the semiconductor element 21 and the plating portions 25 (internal terminals 15A) of the outer peripheral lead portions 12A and 12B are electrically connected to each other by bonding wires (connection members) 22, respectively. Similarly, the electrodes 21a of the semiconductor element 21 and the plating portions 25 (internal terminals 15B) of the inner lead portions 26A to 26D are electrically connected to each other by bonding wires (connection members) 22 (wire bonding step). (FIG. 7B).
　このとき、リードフレーム１０をワイヤボンディング装置のヒートブロック３６上に載置する。次いで、ヒートブロック３６により、各外周リード部１２Ａ、１２Ｂおよび各内側リード部２６Ａ～２６Ｄをその裏面側から加熱する。これとともに、ワイヤボンディング装置のキャピラリー（図示せず）を介して超音波を印加しながら、半導体素子２１の各電極２１ａと、各外周リード部１２Ａ、１２Ｂおよび各内側リード部２６Ａ～２６Ｄのめっき部２５とを、それぞれボンディングワイヤ２２を用いて電気的に接続する。 At this time, the lead frame 10 is placed on the heat block 36 of the wire bonding apparatus. Next, the outer circumferential lead portions 12A and 12B and the inner lead portions 26A to 26D are heated from the back side thereof by the heat block 36. At the same time, while applying ultrasonic waves through the capillaries (not shown) of the wire bonding apparatus, the electrodes 21a of the semiconductor element 21 and the plating portions of the outer peripheral lead portions 12A and 12B and the inner lead portions 26A to 26D. 25 are electrically connected to each other using bonding wires 22.
　次に、リードフレーム１０に対して熱硬化性樹脂または熱可塑性樹脂を射出成形またはトランスファ成形することにより、封止樹脂２３を形成する（図７（ｃ））。このようにして、ダイパッド１１、複数の外周リード部１２Ａ、１２Ｂ、複数の内側リード部２６Ａ～２６Ｄ、半導体素子２１、およびボンディングワイヤ２２を樹脂封止する。 Next, a sealing resin 23 is formed by injection molding or transfer molding of a thermosetting resin or a thermoplastic resin to the lead frame 10 (FIG. 7C). In this manner, the die pad 11, the plurality of outer peripheral lead portions 12A and 12B, the plurality of inner lead portions 26A to 26D, the semiconductor element 21, and the bonding wire 22 are sealed with resin.
　続いて、リードフレーム１０および封止樹脂２３の裏面に、所定の開口部３４ａを有するエッチング用レジスト層３４を設ける（図７（ｄ））。 Subsequently, an etching resist layer 34 having a predetermined opening 34a is provided on the back surface of the lead frame 10 and the sealing resin 23 (FIG. 7D).
　この間、まずリードフレーム１０および封止樹脂２３の裏面全体にそれぞれ感光性レジストを塗布する。続いて、当該感光性レジストをフォトマスクを介して露光し、現像することにより、所望の開口部３４ａを有するエッチング用レジスト層３４が形成される。 During this time, first, a photosensitive resist is applied to the entire back surface of the lead frame 10 and the sealing resin 23, respectively. Subsequently, the photosensitive resist is exposed through a photomask and developed to form an etching resist layer 34 having a desired opening 34a.
　この場合、エッチング用レジスト層３４は、開口部３４ａを除くリードフレーム１０および封止樹脂２３の裏面全体を覆っている。また、開口部３４ａは、接続リング１４の位置にほぼ対応する平面略矩形の帯形状を有しており、開口部３４ａからは接続リング１４の裏面（金属部分）が露出している。なお、エッチング用レジスト層３４としては、例えば公知のドライフィルムレジストを用いることができる。 In this case, the etching resist layer 34 covers the entire back surface of the lead frame 10 and the sealing resin 23 except for the opening 34a. The opening 34a has a substantially rectangular band shape substantially corresponding to the position of the connection ring 14, and the back surface (metal part) of the connection ring 14 is exposed from the opening 34a. As the etching resist layer 34, for example, a known dry film resist can be used.
　次に、エッチング用レジスト層３４を耐腐蝕膜としてリードフレーム１０に腐蝕液でエッチングを施す（図７（ｅ））。このとき、開口部３４ａから進入した腐蝕液が、接続リング１４の全体を溶解して除去する。この際、内側リード部２６Ａ～２６Ｄの接続リード５７の一部が、接続リング１４とともに除去されても良い。この場合、接続リング１４の表面に凹溝１４ａが設けられているので、開口部３４ａから進入した腐蝕液が、第２端子部１８や外周リード部１２Ａ、１２Ｂを必要以上に溶解することがなく、接続リング１４を適切に除去することができる。 Next, the lead frame 10 is etched with a corrosive solution using the etching resist layer 34 as a corrosion-resistant film (FIG. 7E). At this time, the corrosive liquid entering from the opening 34 a dissolves and removes the entire connection ring 14. At this time, a part of the connection lead 57 of the inner lead portions 26A to 26D may be removed together with the connection ring 14. In this case, since the concave groove 14a is provided on the surface of the connection ring 14, the corrosive liquid entering from the opening 34a does not dissolve the second terminal portion 18 and the outer circumferential lead portions 12A and 12B more than necessary. The connection ring 14 can be removed appropriately.
　このようにして、接続リング１４が取り除かれ、内側リード部２６Ａ～２６Ｄが互いに分離される。この結果、各第２端子部１８は個別に分離され、ダイパッド１１、外周リード部１２Ａ、１２Ｂおよび他の第２端子部１８から電気的に独立する。なお、腐蝕液は、上記と同様（図６（ｄ）参照）、例えば塩化第二鉄水溶液を使用することができる。 In this way, the connection ring 14 is removed, and the inner lead portions 26A to 26D are separated from each other. As a result, the second terminal portions 18 are individually separated and are electrically independent from the die pad 11, the outer peripheral lead portions 12 </ b> A and 12 </ b> B, and the other second terminal portions 18. In addition, the corrosion liquid can use the ferric chloride aqueous solution, for example similarly to the above (refer FIG.6 (d)).
　次いで、エッチング用レジスト層３４を剥離して除去する。その後、各半導体素子２１間のリードフレーム１０および封止樹脂２３をダイシングすることにより、リードフレーム１０を各単位リードフレーム１０ａ（図１参照）毎に分離する。この際、例えばダイヤモンド砥石からなるブレード（図示せず）を回転させながら、各単位リードフレーム１０ａ間のリードフレーム１０および封止樹脂２３を切断しても良い。なお、エッチング用レジスト層３４を除去した後、凹部２７に封止樹脂２３と同じあるいは別の種類の絶縁性樹脂を充填する工程が設けられていても良い。 Next, the etching resist layer 34 is peeled off and removed. Thereafter, the lead frame 10 and the sealing resin 23 between the semiconductor elements 21 are diced to separate the lead frame 10 for each unit lead frame 10a (see FIG. 1). At this time, the lead frame 10 and the sealing resin 23 between the unit lead frames 10a may be cut while rotating a blade (not shown) made of, for example, a diamond grindstone. Note that after removing the etching resist layer 34, a step of filling the recess 27 with the same or different type of insulating resin as the sealing resin 23 may be provided.
　このようにして、図４および図５に示す半導体装置２０が得られる（図７（ｆ））。 Thus, the semiconductor device 20 shown in FIGS. 4 and 5 is obtained (FIG. 7 (f)).
　このように本実施の形態によれば、第１端子部５３が相対的に内側に位置する長外周リード部１２Ａと、第１端子部５３が相対的に外側に位置する短外周リード部１２Ｂとが交互に配置されている。これにより、外周リード部１２Ａ、１２Ｂの間隔を狭くするとともにその本数を増やすことができるので、第１端子部５３の数を増やすことができる。 As described above, according to the present embodiment, the long outer periphery lead portion 12A in which the first terminal portion 53 is positioned relatively inside, and the short outer periphery lead portion 12B in which the first terminal portion 53 is positioned relatively outside, Are arranged alternately. Thereby, since the space | interval of outer periphery lead part 12A, 12B can be narrowed and the number can be increased, the number of the 1st terminal parts 53 can be increased.
　また、本実施の形態によれば、半導体装置２０を作製する際、接続リング１４を除去することにより、複数の第２端子部１８がそれぞれ個別に分離されるようになっている。このため、外周リード部１２Ａ、１２Ｂの第１端子部５３に加え、内側リード部２６Ａ～２６Ｄの第２端子部１８を用いることもでき、外部の実装基板と接続される端子部の数（ピン数）を更に増やすことができる。これにより、半導体装置２０の高密度化を実現することができる。 Further, according to the present embodiment, when the semiconductor device 20 is manufactured, the plurality of second terminal portions 18 are individually separated by removing the connection ring 14. Therefore, in addition to the first terminal portion 53 of the outer peripheral lead portions 12A and 12B, the second terminal portion 18 of the inner lead portions 26A to 26D can be used, and the number of terminal portions (pins) connected to an external mounting board Number) can be further increased. Thereby, high density of the semiconductor device 20 can be realized.
　とりわけ、本実施の形態によれば、第２端子部１８が相対的に接続リング１４から離間した部分に位置する長内側リード部２６Ａ、２６Ｃと、第２端子部１８が相対的に接続リング１４に近接した部分に位置する短内側リード部２６Ｂ、２６Ｄとが接続リング１４に沿って交互に配置されている。さらに、複数の内側リード部２６Ａ～２６Ｄは、接続リング１４の内側および外側の両方から延びている。これにより、内側リード部２６Ａ～２６Ｄの間隔を狭くするとともにその本数を増やすことができるので、第２端子部１８の数を増やすことができる。 In particular, according to the present embodiment, the long inner lead portions 26A and 26C that are positioned in a portion where the second terminal portion 18 is relatively separated from the connection ring 14 and the second terminal portion 18 are relatively connected to the connection ring 14. The short inner lead portions 26B and 26D located in the vicinity of the connection ring 14 are alternately arranged along the connection ring 14. Further, the plurality of inner lead portions 26A to 26D extend from both the inner side and the outer side of the connection ring 14. As a result, the interval between the inner lead portions 26A to 26D can be reduced and the number of the inner lead portions 26A to 26D can be increased, so that the number of second terminal portions 18 can be increased.
　なお、本実施の形態においては、接続リング１４の全体がエッチングにより除去される場合を例にとって説明したが、これに限られるものではない。例えば、接続リング１４の一部のみをエッチングにより除去し、接続リング１４のうち除去されなかった部分を半導体装置２０内に残すようにしても良い。 In the present embodiment, the case where the entire connection ring 14 is removed by etching has been described as an example. However, the present invention is not limited to this. For example, only a part of the connection ring 14 may be removed by etching, and a part of the connection ring 14 that has not been removed may be left in the semiconductor device 20.
　また、上記実施の形態では、内側リード部２６Ａ、２６Ｂの外部端子１７Ｃ、１７Ｄ（内側リード部２６Ｃ、２６Ｄの外部端子１７Ｅ、１７Ｆ）が、隣り合う内側リード部２６Ａ、２６Ｂ（内側リード部２６Ｃ、２６Ｄ）間で内側および外側に位置するよう平面から見て交互に千鳥状に２列に配置されている場合を例にとって説明した。しかしながら、これに限らず、内側リード部２６Ａ、２６Ｂの外部端子１７Ｃ、１７Ｄ（内側リード部２６Ｃ、２６Ｄの外部端子１７Ｅ、１７Ｆ）が、接続リング１４の各辺に沿って一直線上に並んでいても良い。 In the above embodiment, the external terminals 17C and 17D of the inner lead portions 26A and 26B (the external terminals 17E and 17F of the inner lead portions 26C and 26D) are adjacent to the inner lead portions 26A and 26B (the inner lead portions 26C and 26C). 26D), an example has been described in which they are alternately arranged in two rows in a staggered manner as viewed from the plane so as to be located inside and outside. However, the present invention is not limited thereto, and the external terminals 17C and 17D of the inner lead portions 26A and 26B (the external terminals 17E and 17F of the inner lead portions 26C and 26D) are aligned along each side of the connection ring 14. Also good.
　（第２の実施の形態）
　次に、図８乃至図１１を参照して本発明の第２の実施の形態について説明する。図８乃至図１１は本発明の第２の実施の形態を示す図である。図８乃至図１１に示す第２の実施の形態は、接続リング１４に第２端子部を有する内側リード部２６Ａ～２６Ｄを設ける代わりに、接続リング１４の一部が個別に分離されて第２端子部２８となる点が異なるものであり、他の構成は上述した第１の実施の形態と略同一である。図８乃至図１１において、第１の実施の形態と同一部分には同一の符号を付して詳細な説明は省略する。 (Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. 8 to 11 are views showing a second embodiment of the present invention. In the second embodiment shown in FIGS. 8 to 11, instead of providing the inner leads 26 </ b> A to 26 </ b> D having the second terminal portions in the connection ring 14, a part of the connection ring 14 is separately separated and the second embodiment is provided. The point which becomes the terminal part 28 is different, and the other structure is substantially the same as the first embodiment described above. 8 to 11, the same parts as those of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
　図８乃至図１０に示すリードフレーム１０Ａにおいて、接続リング１４の表面に間隔を空けて複数の凹部１４ｃが形成されている。各凹部１４ｃは、ハーフエッチングにより形成されたものであり、厚み方向に貫通することなく一定の深さを持っている。なお、各凹部１４ｃは、接続リング１４の幅方向略中央部に形成されている。 In the lead frame 10A shown in FIGS. 8 to 10, a plurality of recesses 14c are formed on the surface of the connection ring 14 at intervals. Each recess 14c is formed by half etching, and has a certain depth without penetrating in the thickness direction. Each concave portion 14 c is formed at a substantially central portion in the width direction of the connection ring 14.
　また、互いに隣接する凹部１４ｃの間には、第２端子部２８が形成されている。すなわち凹部１４ｃと第２端子部２８とは、接続リング１４の長さ方向に沿って交互に配置されている。この場合、第２端子部２８は、ハーフエッチングされておらず、ダイパッド１１および支持リード１３と同一の厚みを有している。なお、各第２端子部２８の表面には、ボンディングワイヤ２２と密着性を向上させるめっき部２５が設けられている。 Also, a second terminal portion 28 is formed between the recesses 14c adjacent to each other. That is, the recesses 14 c and the second terminal portions 28 are alternately arranged along the length direction of the connection ring 14. In this case, the second terminal portion 28 is not half-etched and has the same thickness as the die pad 11 and the support lead 13. In addition, the plating part 25 which improves the adhesiveness with the bonding wire 22 is provided on the surface of each second terminal part 28.
　本実施の形態において、半導体装置２０Ａ（図１１参照）を作製する際、接続リング１４の一部のみがエッチングにより除去される。具体的には、接続リング１４のうち各凹部１４ｃの周辺領域がそれぞれ除去される。一方、接続リング１４のうち、各凹部１４ｃ間に位置する部分は、除去されることなく、それぞれ個別に分離されて第２端子部２８を構成する。 In this embodiment, when the semiconductor device 20A (see FIG. 11) is manufactured, only a part of the connection ring 14 is removed by etching. Specifically, the peripheral area of each recess 14c in the connection ring 14 is removed. On the other hand, the part located between each recessed part 14c among the connection rings 14 is isolate | separated separately, and comprises the 2nd terminal part 28, without removing.
　すなわち、リードフレーム１０Ａの裏面側から接続リング１４の一部をエッチング除去する際（図７（ｆ）参照）、各凹部１４ｃおよびその周囲に対応する領域にエッチング用レジスト層３４の開口部３４ａを設けておく。そして当該開口部３４ａから進入した腐蝕液により、接続リング１４のうち各凹部１４ｃの周辺領域を選択的に溶解して除去する。この場合、接続リング１４の表面に凹部１４ｃが設けられているので、開口部３４ａから進入した腐蝕液が、第２端子部２８や外周リード部１２Ａ、１２Ｂを必要以上に溶解することなく、接続リング１４のうち各凹部１４ｃの周辺領域のみを適切に除去することができる。このようにして、接続リング１４のうち、互いに隣接する２つの凹部１４ｃ同士の間に、それぞれ第２端子部２８が残存する。 That is, when a part of the connection ring 14 is etched away from the back surface side of the lead frame 10A (see FIG. 7F), the openings 34a of the etching resist layer 34 are formed in the regions corresponding to the respective recesses 14c and the periphery thereof. Keep it. And the surrounding area | region of each recessed part 14c among the connection rings 14 is selectively melt | dissolved and removed with the corrosive liquid which approached from the said opening part 34a. In this case, since the concave portion 14c is provided on the surface of the connection ring 14, the corrosive liquid entering from the opening 34a can be connected without dissolving the second terminal portion 28 and the outer peripheral lead portions 12A and 12B more than necessary. Only the peripheral region of each recess 14c in the ring 14 can be appropriately removed. In this way, the second terminal portions 28 remain between the two recesses 14c adjacent to each other in the connection ring 14.
　なお、本実施の形態において、凹部１４ｃは、それぞれ長外周リード部１２Ａの先端に対応する位置に形成されているが、これに限らず、短外周リード部１２Ｂの先端に対応する位置に形成されていても良い。また、複数の凹部１４ｃは、接続リング１４の周方向全域にわたって設けられているが、これに限らず、接続リング１４の一部分のみに設けられていても良い。 In the present embodiment, the recess 14c is formed at a position corresponding to the tip of the long outer periphery lead portion 12A, but is not limited thereto, and is formed at a position corresponding to the tip of the short outer periphery lead portion 12B. May be. Moreover, although the several recessed part 14c is provided over the circumferential direction whole region of the connection ring 14, it is not restricted to this, You may provide in only one part of the connection ring 14. FIG.
　図１１に示す半導体装置２０Ａは、図８乃至図１０に示すリードフレーム１０Ａから作製されたものである。この半導体装置２０Ａにおいて、第２端子部２８は、ダイパッド１１の周囲４辺（図１１においてはＸ方向又はＹ方向に平行な４辺）の全てに沿って、互いに間隔を空けて配列されている。 A semiconductor device 20A shown in FIG. 11 is manufactured from the lead frame 10A shown in FIGS. In the semiconductor device 20A, the second terminal portions 28 are arranged at intervals from each other along all four sides (four sides parallel to the X direction or the Y direction in FIG. 11) around the die pad 11. .
　上述したように、リードフレーム１０Ａの接続リング１４のうち、各凹部１４ｃの周辺領域は、封止樹脂２３によって樹脂封止された後、裏面側からエッチングにより除去されている。このため、図１１に示すように、各第２端子部２８は、ダイパッド１１、外周リード部１２Ａ、１２Ｂおよび他の第２端子部２８から分離されており、これらの部材から電気的に独立している。また、第２端子部２８は、ハーフエッチングされておらず、ダイパッド１１と同一の厚みを有している。さらに第２端子部２８の裏面には、外部の実装基板（図示せず）に電気的に接続される外部端子１７Ｃが形成されている。 As described above, in the connection ring 14 of the lead frame 10A, the peripheral region of each recess 14c is resin-sealed with the sealing resin 23 and then removed from the back side by etching. Therefore, as shown in FIG. 11, each second terminal portion 28 is separated from the die pad 11, the outer peripheral lead portions 12 </ b> A and 12 </ b> B, and the other second terminal portions 28, and is electrically independent from these members. ing. Further, the second terminal portion 28 is not half-etched and has the same thickness as the die pad 11. Furthermore, an external terminal 17 </ b> C that is electrically connected to an external mounting substrate (not shown) is formed on the back surface of the second terminal portion 28.
　また、接続リング１４のうち第２端子部２８を除く部分が除去されたことに伴い、封止樹脂２３の裏面のうち、外周リード部１２Ａ、１２Ｂとダイパッド１１との間の領域に、ダイパッド１１を取り囲むように凹部２７が形成される。 In addition, as the portion excluding the second terminal portion 28 of the connection ring 14 is removed, the die pad 11 is formed in the region between the outer peripheral lead portions 12A and 12B and the die pad 11 on the back surface of the sealing resin 23. A recess 27 is formed so as to surround.
　本実施の形態によれば、半導体装置２０Ａを作製する際、接続リング１４の一部が除去され、接続リング１４のうち除去されない部分がそれぞれ個別に分離されて第２端子部２８となる。このように、多数の第２端子部２８が形成されていることにより、外部の実装基板と接続される端子部の数（ピン数）を増やすことができ、半導体装置２０の更なる高密度化を実現することができる。 According to the present embodiment, when the semiconductor device 20A is manufactured, a part of the connection ring 14 is removed, and the part of the connection ring 14 that is not removed is individually separated to become the second terminal portion 28. As described above, since a large number of second terminal portions 28 are formed, the number of terminal portions (number of pins) connected to an external mounting substrate can be increased, and the density of the semiconductor device 20 can be further increased. Can be realized.
　本実施の形態において、一部の第２端子部２８を他の第２端子部２８よりも大きく形成し、この第２端子部２８に複数のボンディングワイヤ２２を接続することにより、電気信号の調節のためのバスバーやグランド（ＧＮＤ）端子として用いても良い。これにより、端子数の増加に伴う発熱を低減し、より信頼性の高い半導体装置２０Ａとすることができる。 In the present embodiment, some of the second terminal portions 28 are formed larger than the other second terminal portions 28, and a plurality of bonding wires 22 are connected to the second terminal portions 28, thereby adjusting the electric signal. It may be used as a bus bar or ground (GND) terminal for the purpose. Thereby, the heat generation accompanying the increase in the number of terminals can be reduced, and the semiconductor device 20A with higher reliability can be obtained.
　なお、本実施の形態によるリードフレーム１０Ａの製造方法および半導体装置２０Ａの製造方法は、第１の実施の形態によるリードフレーム１０の製造方法（図６（ａ）－（ｆ））および半導体装置２０の製造方法（図７（ａ）－（ｆ））と略同様である。 Note that the manufacturing method of the lead frame 10A and the manufacturing method of the semiconductor device 20A according to the present embodiment are the same as the manufacturing method of the lead frame 10 (FIGS. 6A to 6F) according to the first embodiment and the semiconductor device 20. This is substantially the same as the manufacturing method (FIGS. 7A to 7F).
　（第３の実施の形態）
　次に、図１２乃至図１７を参照して本発明の第３の実施の形態について説明する。図１２乃至図１７は本発明の第３の実施の形態を示す図である。図１２乃至図１７に示す第３の実施の形態は、主として、内側リード部２６Ａ～２６Ｄの配置、および接続リード５７が表面側から薄肉化されている点が異なるものであり、他の構成は上述した第１の実施の形態と略同一である。図１２乃至図１７において、第１の実施の形態と同一部分には同一の符号を付して詳細な説明は省略する。 (Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIGS. 12 to 17 are views showing a third embodiment of the present invention. The third embodiment shown in FIGS. 12 to 17 mainly differs in the arrangement of the inner lead portions 26A to 26D and the point that the connection lead 57 is thinned from the surface side. This is substantially the same as the first embodiment described above. 12 to 17, the same parts as those in the first embodiment are denoted by the same reference numerals and detailed description thereof is omitted.
　図１２乃至図１４に示すリードフレーム１０Ｂおよび図１５および図１６に示す半導体装置２０Ｂにおいて、複数の内側リード部２６Ａ～２６Ｄのうち、接続リング１４の内側から延びる長内側リード部２６Ｃと、接続リング１４の外側から延びる短内側リード部２６Ｂとが、接続リング１４を介して互いに反対側の位置に配置されている。すなわち、長内側リード部２６Ｃと、対応する短内側リード部２６Ｂとが、接続リング１４を挟んで一直線上に位置している。 In the lead frame 10B shown in FIGS. 12 to 14 and the semiconductor device 20B shown in FIGS. 15 and 16, the long inner lead portion 26C extending from the inner side of the connection ring 14 among the plurality of inner lead portions 26A to 26D, and the connection ring Short inner lead portions 26 </ b> B extending from the outer side of 14 are arranged at positions opposite to each other via the connection ring 14. That is, the long inner lead portion 26 </ b> C and the corresponding short inner lead portion 26 </ b> B are positioned on a straight line across the connection ring 14.
　また、接続リング１４の内側から延びる短内側リード部２６Ｄと、接続リング１４の外側から延びる長内側リード部２６Ａとが、接続リング１４を介して互いに反対側の位置に配置されている。すなわち、短内側リード部２６Ｄと、対応する長内側リード部２６Ａとが、接続リング１４を挟んで一直線上に位置している。これにより、外部端子１７Ｄと外部端子１７Ｆとの間の端子間距離を確保することができ、これらの端子同士が接触する不具合を防止することができる。 Further, a short inner lead portion 26D extending from the inside of the connection ring 14 and a long inner lead portion 26A extending from the outside of the connection ring 14 are arranged at positions opposite to each other via the connection ring 14. That is, the short inner lead portion 26 </ b> D and the corresponding long inner lead portion 26 </ b> A are positioned on a straight line across the connection ring 14. Thereby, the inter-terminal distance between the external terminal 17D and the external terminal 17F can be ensured, and the problem of contact between these terminals can be prevented.
　さらに、接続リング１４の外側から延びる短内側リード部２６Ｂと、長外周リード部１２Ａとが互いに向かい合い、接続リング１４の外側から延びる長内側リード部２６Ａと、短外周リード部１２Ｂとが互いに向かい合っている。 Further, the short inner lead portion 26B extending from the outside of the connection ring 14 and the long outer peripheral lead portion 12A face each other, and the long inner lead portion 26A extending from the outer side of the connection ring 14 and the short outer peripheral lead portion 12B face each other. Yes.
　また、本実施の形態において、内側リード部２６Ａ～２６Ｄの各接続リード５７は、表面側から薄肉化されている。この場合、接続リード５７が裏面側に露出するので、接続リング１４とともに接続リード５７を除去する作業を容易に行うことができる。また、接続リング１４をエッチングにより除去する際（図７（ｅ）参照）、接続リング１４および接続リード５７が確実に除去されたか否かを裏面側から容易に確認することができる。これにより、外部端子１７Ｃ～１７Ｆを独立させる作業が容易となる。なお、第１の実施の形態においても、接続リード５７を表面側から薄肉化しても良い。 In the present embodiment, the connection leads 57 of the inner lead portions 26A to 26D are thinned from the surface side. In this case, since the connection lead 57 is exposed on the back side, the operation of removing the connection lead 57 together with the connection ring 14 can be easily performed. Further, when the connection ring 14 is removed by etching (see FIG. 7E), it can be easily confirmed from the back side whether or not the connection ring 14 and the connection lead 57 have been reliably removed. This facilitates the work of making the external terminals 17C to 17F independent. Also in the first embodiment, the connection lead 57 may be thinned from the surface side.
　図１５および図１６に示す半導体装置２０Ｂにおいて、接続リング１４とともに接続リード５７が除去されているが、これに限らず、半導体装置２０Ｂに接続リード５７の一部を残しても良く、あるいは接続リード５７の全体を残しても良い。 In the semiconductor device 20B shown in FIG. 15 and FIG. 16, the connection lead 57 is removed together with the connection ring 14. However, the present invention is not limited to this, and a part of the connection lead 57 may be left in the semiconductor device 20B. The entire 57 may be left.
　図１７は、本実施の形態の変形例によるリードフレーム１０Ｃを示している。図１７において、接続リング１４の内側からは、短内側リード部２６Ｄのみが延びており、長内側リード部２６Ｃは延びていない。したがって、外部端子１７Ａ～１７Ｄ、１７Ｆは、ダイパッド１１の周囲に５列に配置されている。この場合、半導体装置２０Ｂの大きさに対してダイパッド１１の面積を広く確保することができる。なお、第１の実施の形態においても、接続リング１４の内側に長内側リード部２６Ｃを設けなくても良い。 FIG. 17 shows a lead frame 10C according to a modification of the present embodiment. In FIG. 17, only the short inner lead portion 26 </ b> D extends from the inside of the connection ring 14, and the long inner lead portion 26 </ b> C does not extend. Accordingly, the external terminals 17A to 17D and 17F are arranged in five rows around the die pad 11. In this case, a large area of the die pad 11 can be ensured with respect to the size of the semiconductor device 20B. Also in the first embodiment, the long inner lead portion 26 </ b> C need not be provided inside the connection ring 14.
　なお、本実施の形態によるリードフレーム１０Ｂ、１０Ｃの製造方法および半導体装置２０Ｂの製造方法は、第１の実施の形態によるリードフレーム１０の製造方法（図６（ａ）－（ｆ））および半導体装置２０の製造方法（図７（ａ）－（ｆ））と略同様である。 Note that the manufacturing method of the lead frames 10B and 10C and the manufacturing method of the semiconductor device 20B according to the present embodiment are the same as those of the manufacturing method of the lead frame 10 according to the first embodiment (FIGS. 6A to 6F) and the semiconductor. This is substantially the same as the method for manufacturing the device 20 (FIGS. 7A to 7F).
　本実施の形態において、図１２（外部端子１７Ａ～１７Ｆが６列）に示すリードフレーム１０Ｂおよび図１７（外部端子１７Ａ～１７Ｄ、１７Ｆが５列）に示すリードフレーム１０Ｃのいずれにおいても、すべての外部端子１７Ａ～１７Ｆを、外部端子１７Ａ～１７Ｆ同士の間隔の等しい千鳥状に配置することができる。これにより、基板実装時における半田ブリッジの発生を抑制することができるため、実装信頼性を向上させることが可能となる。 In the present embodiment, all of the lead frame 10B shown in FIG. 12 (external terminals 17A to 17F have 6 rows) and the lead frame 10C shown in FIG. 17 (external terminals 17A to 17D, 17F have 5 rows) The external terminals 17A to 17F can be arranged in a zigzag manner in which the intervals between the external terminals 17A to 17F are equal. As a result, it is possible to suppress the occurrence of solder bridges when the board is mounted, and it is possible to improve the mounting reliability.
　本実施の形態によれば、例えば１２ｍｍ□のパッケージの場合、図１２に示すリードフレーム１０Ｂ（外部端子１７Ａ～１７Ｆが６列）を用いると、端子部の数（ピン数）を３０８ピンまで増やすことができる。また、例えば１２ｍｍ□のパッケージの場合、図１７に示すリードフレーム１０Ｂ（外部端子１７Ａ～１７Ｄ、１７Ｆが５列）を用いると、端子部の数（ピン数）を２８０ピンまで増やすことができる。このように、本実施の形態によれば、高機能のＬＳＩを搭載可能な半導体装置を安価に作製することが可能になる。さらに、例えば１０ｍｍ□のパッケージの場合、図１７に示すリードフレーム１０Ｂ（外部端子１７Ａ～１７Ｄ、１７Ｆが５列）を用いると、端子部の数（ピン数）を２０８ピン～２１６ピンまで増やすことが可能となる。このピン数（２０８ピン～２１６ピン）は、従来の２８ｍｍ□のＱＦＰ（Quad Flat Package）と同等のピン数に相当する。 According to the present embodiment, for example, in the case of a 12 mm square package, using the lead frame 10B shown in FIG. 12 (six external terminals 17A to 17F) increases the number of terminal portions (number of pins) to 308 pins. be able to. For example, in the case of a 12 mm square package, if the lead frame 10B shown in FIG. 17 (five rows of external terminals 17A to 17D, 17F) is used, the number of terminal portions (number of pins) can be increased to 280 pins. As described above, according to this embodiment, a semiconductor device on which a high-performance LSI can be mounted can be manufactured at low cost. Further, for example, in the case of a package of 10 mm □, if the lead frame 10B shown in FIG. 17 (external terminals 17A to 17D and 17F are in five rows) is used, the number of terminals (number of pins) is increased from 208 pins to 216 pins. Is possible. The number of pins (208 to 216 pins) corresponds to the number of pins equivalent to the conventional 28 mm □ QFP (Quad Flat Package).
　（第４の実施の形態）
　次に、図１８乃至図２１を参照して本発明の第４の実施の形態について説明する。図１８乃至図２１は本発明の第４の実施の形態を示す図である。図１８乃至図２１に示す第４の実施の形態は、主として、接続リング１４に代えてリード接続部（接続バー）６４を設けた点が異なるものであり、他の構成は上述した第１の実施の形態と略同一である。図１８乃至図２１において、第１の実施の形態と同一部分には同一の符号を付して詳細な説明は省略する。 (Fourth embodiment)
Next, a fourth embodiment of the present invention will be described with reference to FIGS. 18 to 21 are views showing a fourth embodiment of the present invention. The fourth embodiment shown in FIGS. 18 to 21 is mainly different from the first embodiment in that a lead connection portion (connection bar) 64 is provided in place of the connection ring 14, and the other configuration is the first embodiment described above. This is substantially the same as the embodiment. 18 to 21, the same parts as those of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
　図１８および図１９に示すリードフレーム１０Ｄにおいて、ダイパッド１１と外周リード部１２Ａ、１２Ｂとの間に、リード接続部６４が配置されている。このリード接続部６４によって、それぞれ第２端子部１８を有する複数の内側リード部２６Ａ～２６Ｄが支持されている。リード接続部６４は、ハーフエッチングされておらず、ダイパッド１１と同一の厚みを有している。しかしながら、これに限らず、リード接続部６４の表面側からハーフエッチングにより薄肉化されていても良い。また、リード接続部６４は、直線状に延びており、その両端はそれぞれ吊りリード１６に連結されている。吊りリード１６は、裏面側からハーフエッチングにより薄肉化されている。なお、リード接続部６４は、必ずしも吊りリード１６に連結されていなくても良く、例えばダイパッド１１に連結されていても良い。 In the lead frame 10D shown in FIGS. 18 and 19, a lead connection portion 64 is disposed between the die pad 11 and the outer peripheral lead portions 12A and 12B. The lead connecting portions 64 support a plurality of inner lead portions 26A to 26D each having the second terminal portion 18. The lead connection portion 64 is not half-etched and has the same thickness as the die pad 11. However, the present invention is not limited to this, and the thickness may be reduced by half etching from the surface side of the lead connection portion 64. The lead connection portion 64 extends linearly, and both ends thereof are coupled to the suspension lead 16. The suspension lead 16 is thinned by half etching from the back side. Note that the lead connecting portion 64 does not necessarily have to be connected to the suspension lead 16, and may be connected to the die pad 11, for example.
　この場合、ダイパッド１１は平面略長方形状であり、その長辺がＸ方向に平行であり、その短辺がＹ方向に平行である。本実施の形態において、リード接続部６４は、１つの単位リードフレーム１０ａあたり２本設けられており、それぞれダイパッド１１の長辺に平行に延びている。しかしながら、これに限らず、リード接続部６４は、１つの単位リードフレーム１０ａあたり１本又は３本以上設けられていても良い。また、リード接続部６４の形状は、直線状に限らず、略円弧等の曲線状、略Ｖ字形状、略Ｌ字形状、略Ｕ字形状等としても良い。 In this case, the die pad 11 has a substantially rectangular plane shape, its long side is parallel to the X direction, and its short side is parallel to the Y direction. In the present embodiment, two lead connection portions 64 are provided for each unit lead frame 10 a, and each extend parallel to the long side of the die pad 11. However, the present invention is not limited to this, and one or three or more lead connection portions 64 may be provided per unit lead frame 10a. Further, the shape of the lead connecting portion 64 is not limited to a linear shape, and may be a curved shape such as a substantially arc, a substantially V shape, a substantially L shape, a substantially U shape, or the like.
　また、本実施の形態において、連続する一部（例えば４個）の外部端子１７Ａが連結部６５によって連結され、連続する一部（例えば３個）の外部端子１７Ｅが連結部６６によって連結されている。連結部６５、６６は、それぞれ例えばバスバーやグランド（ＧＮＤ）端子として用いられても良い。 Further, in the present embodiment, a continuous part (for example, four) external terminals 17A are connected by the connecting part 65, and a continuous part (for example, three) external terminals 17E are connected by the connecting part 66. Yes. The connecting portions 65 and 66 may be used as, for example, a bus bar or a ground (GND) terminal.
　図２０に示す半導体装置２０Ｄは、図１８および図１９に示すリードフレーム１０Ｄから作製されたものである。この半導体装置２０Ｄにおいて、リード接続部６４が除去されており、これに伴い、封止樹脂２３の裏面のうち、外周リード部１２Ａ、１２Ｂとダイパッド１１との間であって、内側リード部２６Ａ、２６Ｂと内側リード部２６Ｃ、２６Ｄとの間の領域に、凹部６７が形成されている。この凹部６７は１つの半導体装置２０Ｄあたり２本設けられており、それぞれリード接続部６４の形状に概ね対応してダイパッド１１の長辺に対して平行に一直線状に延びている。 A semiconductor device 20D shown in FIG. 20 is manufactured from the lead frame 10D shown in FIGS. In the semiconductor device 20D, the lead connection portion 64 is removed, and accordingly, the inner lead portion 26A, between the outer peripheral lead portions 12A and 12B and the die pad 11 on the back surface of the sealing resin 23. A recess 67 is formed in a region between 26B and the inner lead portions 26C and 26D. Two recesses 67 are provided for each semiconductor device 20D, and each of the recesses 67 extends in a straight line parallel to the long side of the die pad 11 substantially corresponding to the shape of the lead connection portion 64.
　本実施の形態によれば、リード接続部６４がダイパッド１１の２辺のみに沿って延びているので、リード接続部６４が設けられていない方向にダイパッド１１を延ばすことによりその面積を広げることができる。これにより、ダイパッド１１に大型の半導体素子２１や複数の半導体素子２１を搭載することが容易となる。 According to the present embodiment, since the lead connection portion 64 extends along only two sides of the die pad 11, the area can be expanded by extending the die pad 11 in a direction where the lead connection portion 64 is not provided. it can. Thereby, it becomes easy to mount a large semiconductor element 21 or a plurality of semiconductor elements 21 on the die pad 11.
　図２１は、本実施の形態の変形例によるリードフレーム１０Ｅを示している。図２１において、各リード接続部６４の内側からは、短内側リード部２６Ｄのみが延びており、長内側リード部２６Ｃは延びていない。この場合、ダイパッド１１の面積を各リード接続部６４側に広げることができる。 FIG. 21 shows a lead frame 10E according to a modification of the present embodiment. In FIG. 21, only the short inner lead portion 26D extends from the inside of each lead connection portion 64, and the long inner lead portion 26C does not extend. In this case, the area of the die pad 11 can be expanded to each lead connection part 64 side.
　なお、本実施の形態によるリードフレーム１０Ｄ、１０Ｅの製造方法および半導体装置２０Ｄの製造方法は、第１の実施の形態によるリードフレーム１０の製造方法（図６（ａ）－（ｆ））および半導体装置２０の製造方法（図７（ａ）－（ｆ））と略同様である。 Note that the manufacturing method of the lead frames 10D and 10E and the manufacturing method of the semiconductor device 20D according to the present embodiment are the same as those of the manufacturing method of the lead frame 10 according to the first embodiment (FIGS. 6A to 6F) and the semiconductor. This is substantially the same as the method for manufacturing the device 20 (FIGS. 7A to 7F).
　（第５の実施の形態）
　次に、図２２乃至図３０を参照して本発明の第５の実施の形態について説明する。図２２乃至図３０は本発明の第５の実施の形態を示す図である。図２２乃至図３０において、同一部分には同一の符号を付しており、一部詳細な説明を省略する場合がある。 (Fifth embodiment)
Next, a fifth embodiment of the present invention will be described with reference to FIGS. 22 to 30 are views showing a fifth embodiment of the present invention. 22 to 30, the same reference numerals are given to the same parts, and a part of the detailed description may be omitted.
　リードフレームの構成
　まず、図２２乃至図２６により、本実施の形態によるリードフレームの概略について説明する。図２２乃至図２６は、本実施の形態によるリードフレームを示す図である。 Construction of the lead frame initially, by 22 to 26, will be described briefly in the lead frame according to the present embodiment. 22 to 26 are views showing a lead frame according to the present embodiment.
　図２２および図２３に示すように、リードフレーム１０Ｆは、複数の単位リードフレーム１０ａを含んでいる。各単位リードフレーム１０ａは、半導体素子２１（後述）を搭載する平面矩形状のダイパッド１１と、ダイパッド１１周囲に設けられ、半導体素子２１と外部回路（図示せず）とを接続する複数の細長いリード部１２Ａ、１２Ｂとを備えている。なお、単位リードフレーム１０ａは、それぞれ半導体装置２０Ｆ（後述）に対応する領域であり、図２２において仮想線の内側に位置する領域である。 22 and 23, the lead frame 10F includes a plurality of unit lead frames 10a. Each unit lead frame 10a is provided with a planar rectangular die pad 11 on which a semiconductor element 21 (described later) is mounted, and a plurality of elongated leads that are provided around the die pad 11 and connect the semiconductor element 21 and an external circuit (not shown). Parts 12A and 12B. Each unit lead frame 10a is a region corresponding to a semiconductor device 20F (described later), and is a region located inside a virtual line in FIG.
　複数の単位リードフレーム１０ａは、支持リード（支持部材）１３を介して互いに連結されている。この支持リード１３は、ダイパッド１１とリード部１２Ａ、１２Ｂとを支持するものであり、Ｘ方向、およびＸ方向に垂直なＹ方向に沿ってそれぞれ延びている。また、ダイパッド１１の四隅には吊りリード１６が連結されており、ダイパッド１１は、この４本の吊りリード１６を介して支持リード１３に連結支持されている。 The plurality of unit lead frames 10 a are connected to each other via support leads (support members) 13. The support leads 13 support the die pad 11 and the lead portions 12A and 12B, and extend along the X direction and the Y direction perpendicular to the X direction. In addition, suspension leads 16 are coupled to the four corners of the die pad 11, and the die pad 11 is coupled and supported to the support leads 13 through the four suspension leads 16.
　隣接するリード部１２Ａ、１２Ｂ同士は、半導体装置２０Ｆ（後述）の製造後に互いに電気的に絶縁される形状となっている。また、各リード部１２Ａ、１２Ｂは、半導体装置２０Ｆの製造後にダイパッド１１と電気的に絶縁される形状となっている。このリード部１２Ａ、１２Ｂの裏面には、それぞれ外部の実装基板（図示せず）に電気的に接続される外部端子１７Ａ、１７Ｂが形成されている。各外部端子１７Ａ、１７Ｂは、半導体装置２０Ｆ（後述）の製造後に、それぞれ半導体装置２０Ｆから外方に露出するようになっている。 Adjacent lead portions 12A and 12B are shaped to be electrically insulated from each other after manufacturing a semiconductor device 20F (described later). Each lead portion 12A, 12B is shaped to be electrically insulated from the die pad 11 after the semiconductor device 20F is manufactured. External terminals 17A and 17B that are electrically connected to external mounting boards (not shown) are formed on the back surfaces of the lead portions 12A and 12B, respectively. The external terminals 17A and 17B are exposed outward from the semiconductor device 20F after the manufacture of the semiconductor device 20F (described later).
　この場合、複数のリード部１２Ａ、１２Ｂの外部端子１７Ａ、１７Ｂは、隣り合うリード部１２Ａ、１２Ｂ間で内側および外側に位置するよう、平面から見て交互に千鳥状に配置されている。すなわち、ダイパッド１１の周囲において、相対的に内側（ダイパッド１１側）に位置する外部端子１７Ａをもつリード部１２Ａと、相対的に外側（支持リード１３側）に位置する外部端子１７Ｂをもつリード部１２Ｂとが、全周にわたり交互に配置されている。これにより、リード部１２Ａ、１２Ｂの外部端子１７Ａ、１７Ｂが、隣接するリード部１２Ｂ、１２Ａに接触する不具合が防止される。なお、本実施の形態において、内側に位置する外部端子１７Ａを内側外部端子１７Ａともいい、外側に位置する外部端子１７Ｂを外側外部端子１７Ｂともいう。この場合、内側外部端子１７Ａおよび外側外部端子１７Ｂは、全て同一の平面形状を有している。 In this case, the external terminals 17A and 17B of the plurality of lead portions 12A and 12B are alternately arranged in a staggered manner when viewed from the plane so as to be located inside and outside between the adjacent lead portions 12A and 12B. That is, around the die pad 11, a lead portion 12A having an external terminal 17A located relatively inside (die pad 11 side) and a lead portion having an external terminal 17B located relatively outside (support lead 13 side). 12B are alternately arranged over the entire circumference. Thereby, the malfunction that the external terminals 17A and 17B of the lead portions 12A and 12B come into contact with the adjacent lead portions 12B and 12A is prevented. In the present embodiment, the external terminal 17A located on the inner side is also referred to as the inner external terminal 17A, and the external terminal 17B located on the outer side is also referred to as the outer external terminal 17B. In this case, the inner external terminal 17A and the outer external terminal 17B all have the same planar shape.
　図２２に示すように、複数の内側外部端子１７Ａは、平面から見ていずれもダイパッド１１の一辺に対して平行な直線に沿って配列されている。また、複数の外側外部端子１７Ｂは、平面から見ていずれもダイパッド１１の一辺に対して平行な直線上に配列されている。すなわち、複数の内側外部端子１７Ａおよび複数の外側外部端子１７Ｂは、Ｘ方向又はＹ方向のいずれかに対して平行な直線に沿って、２列に配列されている。しかしながら、これに限られるものではなく、例えば、複数の内側外部端子１７Ａおよび／または複数の外側外部端子１７Ｂが、それぞれ平面から見て円弧上に配列されても良い。 As shown in FIG. 22, the plurality of inner external terminals 17A are all arranged along a straight line parallel to one side of the die pad 11 when viewed from the plane. The plurality of outer external terminals 17 </ b> B are all arranged on a straight line parallel to one side of the die pad 11 when viewed from the plane. That is, the plurality of inner external terminals 17A and the plurality of outer external terminals 17B are arranged in two rows along a straight line parallel to either the X direction or the Y direction. However, the present invention is not limited to this. For example, the plurality of inner external terminals 17A and / or the plurality of outer external terminals 17B may be arranged on an arc as viewed from the plane.
　次に、図２４および図２５（ａ）－（ｂ）を参照して、各リード部１２Ａ、１２Ｂの構成について更に説明する。 Next, the configuration of each of the lead portions 12A and 12B will be further described with reference to FIGS. 24 and 25 (a)-(b).
　図２４に示すように、リード部１２Ａ、１２Ｂのうち、内側外部端子１７Ａを有するリード部１２Ａは、インナーリード５１と、接続リード５２と、端子部（第１端子部）５３とを有している。このうちインナーリード５１は、端子部５３よりも内側（ダイパッド１１側）に延びており、その内側端部表面には内部端子１５が形成されている。この内部端子１５は、後述するようにボンディングワイヤ２２を介して半導体素子２１に電気的に接続される領域となっている。このため、内部端子１５上には、ボンディングワイヤ２２との密着性を向上させるめっき部２５が設けられている。この場合、インナーリード５１は、支持リード１３に対して傾斜して延びている。 As shown in FIG. 24, among the lead portions 12A and 12B, the lead portion 12A having the inner external terminal 17A has an inner lead 51, a connection lead 52, and a terminal portion (first terminal portion) 53. Yes. Among these, the inner lead 51 extends inward (on the die pad 11 side) from the terminal portion 53, and the internal terminal 15 is formed on the inner end surface thereof. The internal terminal 15 is a region that is electrically connected to the semiconductor element 21 via a bonding wire 22 as will be described later. For this reason, on the internal terminal 15, the plating part 25 which improves adhesiveness with the bonding wire 22 is provided. In this case, the inner lead 51 extends obliquely with respect to the support lead 13.
　接続リード５２は、端子部５３よりも外側（支持リード１３側）に位置しており、その外端部は支持リード１３に連結されている。接続リード５２は、当該接続リード５２が連結される支持リード１３に対して垂直に延びている。さらに、端子部５３の裏面には、内側外部端子１７Ａが形成されている。 The connection lead 52 is located outside the terminal portion 53 (on the support lead 13 side), and its outer end is connected to the support lead 13. The connection lead 52 extends perpendicularly to the support lead 13 to which the connection lead 52 is coupled. Further, an inner external terminal 17 </ b> A is formed on the back surface of the terminal portion 53.
　図２５（ａ）に示すように、リード部１２Ａのインナーリード５１および接続リード５２は、それぞれ裏面側（半導体素子２１を搭載する面の反対側）からハーフエッチングにより薄肉に形成されている。他方、端子部５３は、ハーフエッチングされることなく、ダイパッド１１および支持リード１３と同一の厚みを有している。このように、インナーリード５１および接続リード５２の厚さが端子部５３の厚さよりも薄いことにより、幅の狭いリード部１２Ａを精度良く形成することができ、小型でピン数の多い半導体装置２０Ｆを得ることができる。なお、ハーフエッチングとは、被エッチング材料をその厚み方向に途中までエッチングすることをいう。 As shown in FIG. 25 (a), the inner lead 51 and the connection lead 52 of the lead portion 12A are formed thin by half-etching from the back side (the side opposite to the surface on which the semiconductor element 21 is mounted). On the other hand, the terminal portion 53 has the same thickness as the die pad 11 and the support lead 13 without being half-etched. Thus, since the thickness of the inner lead 51 and the connection lead 52 is thinner than the thickness of the terminal portion 53, the narrow lead portion 12A can be accurately formed, and the semiconductor device 20F is small and has a large number of pins. Can be obtained. Half-etching means that the material to be etched is etched halfway in the thickness direction.
　一方、図２４に示すように、リード部１２Ａ、１２Ｂのうち、外側外部端子１７Ｂを有するリード部１２Ｂは、インナーリード６１と、接続リード６２と、端子部６３とを有している。このうちインナーリード６１は、端子部６３よりも内側（ダイパッド１１側）に位置しており、その内側端部表面には内部端子１５が形成されている。この場合、インナーリード６１は、支持リード１３に対して垂直に延びる直線部分６１ｂと、当該直線部分６１ｂから傾斜して延びる傾斜部分６１ａとを有している。 On the other hand, as shown in FIG. 24, the lead part 12B having the outer external terminal 17B among the lead parts 12A and 12B has an inner lead 61, a connection lead 62, and a terminal part 63. Among these, the inner lead 61 is located on the inner side (on the die pad 11 side) than the terminal portion 63, and the inner terminal 15 is formed on the inner end surface thereof. In this case, the inner lead 61 has a straight part 61b extending perpendicularly to the support lead 13 and a sloped part 61a extending inclined from the straight part 61b.
　また、接続リード６２は、端子部６３よりも外側（支持リード１３側）に位置しており、その外側端部は支持リード１３に連結されている。接続リード６２は、当該接続リード６２が連結される支持リード１３に対して垂直に延びている。さらに、端子部６３の裏面には、外側外部端子１７Ｂが形成されている。 Further, the connection lead 62 is positioned on the outer side (support lead 13 side) than the terminal portion 63, and the outer end portion thereof is coupled to the support lead 13. The connection lead 62 extends perpendicular to the support lead 13 to which the connection lead 62 is coupled. Further, an outer external terminal 17B is formed on the back surface of the terminal portion 63.
　図２５（ｂ）に示すように、リード部１２Ｂのインナーリード６１および接続リード６２は、それぞれ裏面側（半導体素子２１を搭載する面の反対側）からハーフエッチングにより薄肉に形成されている。また、端子部６３は、ハーフエッチングされることなく、ダイパッド１１および支持リード１３と同一の厚みを有している。このように、インナーリード６１および接続リード６２の厚さが端子部６３の厚さよりも薄いことにより、幅の狭いリード部１２Ｂを精度良く形成することができ、小型でピン数の多い半導体装置２０Ｆを得ることができる。 As shown in FIG. 25 (b), the inner lead 61 and the connection lead 62 of the lead portion 12B are formed thin by half-etching from the back surface side (the side opposite to the surface on which the semiconductor element 21 is mounted). Moreover, the terminal part 63 has the same thickness as the die pad 11 and the support lead 13 without being half-etched. As described above, since the inner lead 61 and the connecting lead 62 are thinner than the terminal portion 63, the narrow lead portion 12B can be formed with high accuracy, and the semiconductor device 20F is small and has a large number of pins. Can be obtained.
　次に、図２６（ａ）－（ｃ）を参照して、各リード部１２Ａ、１２Ｂの断面形状（各リード部１２Ａ、１２Ｂを支持する支持リード１３に平行な方向に沿った断面形状）について更に説明する。 Next, referring to FIGS. 26A to 26C, the cross-sectional shape of each lead portion 12A, 12B (the cross-sectional shape along the direction parallel to the support lead 13 supporting each lead portion 12A, 12B). Further explanation will be given.
　図２６（ａ）－（ｃ）に示すように、リード部１２Ａのインナーリード５１および接続リード５２は、裏面側からハーフエッチングが施されることにより、それぞれ、略四角形状、略台形状、又は略かまぼこ形状の断面を有している。また、リード部１２Ｂのインナーリード６１および接続リード６２についても同様に、裏面側からハーフエッチングが施されることにより、それぞれ、略四角形状、略台形状、又は略かまぼこ形状の断面を有している。 As shown in FIGS. 26 (a)-(c), the inner lead 51 and the connection lead 52 of the lead portion 12A are each subjected to half-etching from the back surface side, so that each has a substantially rectangular shape, a substantially trapezoidal shape, or It has a cross-section that is substantially kamaboko. Similarly, the inner lead 61 and the connecting lead 62 of the lead portion 12B are also half-etched from the back surface side, so that each has a substantially quadrangular, trapezoidal, or substantially semi-cylindrical cross section. Yes.
　また、図２６（ａ）に示すように、リード部１２Ａの端子部５３は、その両側面が内方に向けて湾曲した形状を有している。この場合、内側外部端子１７Ａ（端子部５３の裏面）の幅ｗＡ２は、端子部５３の表面の幅ｗＡ１よりも広くなっている。これにより、互いに隣接するリード部１２Ａとリード部１２Ｂとの間隔を狭めた場合であっても、内側外部端子１７Ａの面積を広く確保することができ、内側外部端子１７Ａと外部の実装基板（図示せず）とを確実に接続することができる。なお、図２６（ｃ）に示すように、リード部１２Ｂの端子部６３についても同様に、その両側面が内方に向けて湾曲した形状を有しており、かつ外側外部端子１７Ｂ（端子部６３の裏面）の幅ｗＢ２が端子部６３の表面の幅ｗＢ１よりも広くなっている。 Further, as shown in FIG. 26A, the terminal portion 53 of the lead portion 12A has a shape in which both side surfaces are curved inward. In this case, the width w A2 of the inner external terminal 17A (the back surface of the terminal portion 53) is wider than the width w A1 of the surface of the terminal portion 53. As a result, even when the interval between the lead portion 12A and the lead portion 12B adjacent to each other is narrowed, the area of the inner external terminal 17A can be secured widely, and the inner external terminal 17A and the external mounting board (see FIG. (Not shown) can be securely connected. As shown in FIG. 26 (c), the terminal portion 63 of the lead portion 12B similarly has a shape in which both side surfaces are curved inward, and the outer external terminal 17B (terminal portion). width w B2 of the back surface) of 63 is wider than the width w B1 of the surface of the terminal portion 63.
　ところで、図２４に示すように、リード部１２Ａ、１２Ｂの接続リード５２、６２のうち、支持リード１３の近傍部分５５は、その幅ｗｃが６０μｍ～９０μｍ又は７５μｍ～９０μｍとなっている。また、図２５（ａ）－（ｂ）において、当該近傍部分５５の厚みｔｃは、５０μｍ～７５μｍ又は６０μｍ～７５μｍとなっている。 Meanwhile, as shown in FIG. 24, of the lead portion 12A, 12B of the connecting leads 52 and 62, the portion near 55 of the support leads 13, the width w c is in the 60 [mu] m ~ 90 [mu] m or 75 [mu] m ~ 90 [mu] m. In FIGS. 25A and 25B, the thickness t c of the neighboring portion 55 is 50 μm to 75 μm or 60 μm to 75 μm.
　このように、近傍部分５５の幅ｗｃを６０μｍ又は７５μｍ以上とし、厚みｔｃを５０μｍ又は６０μｍ以上としたことにより、リード部１２Ａ、１２Ｂのつけ根にあたる部分（近傍部分５５）の強度を保持している。このため、リード部１２Ａ、１２Ｂ間の間隔を狭くした場合であっても、リード部１２Ａ、１２Ｂの強度が低下することが抑えられ、リード部１２Ａ、１２Ｂに変形が生じることを防止することができる。また、上記近傍部分５５の幅ｗｃを９０μｍ以下とし、厚みｔｃを７５μｍ以下としたことにより、リード部１２Ａ、１２Ｂ間の間隔を狭くすることができ、各半導体装置２０Ｆの外部端子１７Ａ、１７Ｂの数（ピン数）を増やすことができる。 As described above, the width w c of the vicinity portion 55 is set to 60 μm or 75 μm or more, and the thickness t c is set to 50 μm or 60 μm or more, thereby maintaining the strength of the portion corresponding to the root of the lead portions 12A and 12B (the vicinity portion 55). ing. For this reason, even if it is a case where the space | interval between lead part 12A, 12B is narrowed, it can suppress that the intensity | strength of lead part 12A, 12B falls, and prevents that lead part 12A, 12B deform | transforms. it can. Further, by setting the width w c of the neighboring portion 55 to 90 μm or less and the thickness t c to 75 μm or less, the interval between the lead portions 12A and 12B can be narrowed, and the external terminals 17A and 16A of each semiconductor device 20F can be reduced. The number of 17B (number of pins) can be increased.
　また、図２４において、リード部１２Ａ、１２Ｂのインナーリード５１、６１のうち、端子部５３、６３の近傍部分５６は、その幅ｗｄが６０μｍ～９０μｍ又は７５μｍ～９０μｍとなっている。さらに、図２５（ａ）－（ｂ）において、当該近傍部分５６の厚みｔｄは、５０μｍ～７５μｍ又は６０μｍ～７５μｍとなっている。 Further, in FIG. 24, of the lead portion 12A, 12B of the inner leads 51 and 61, near portion 56 of the terminal portions 53 and 63 has a width w d is in the 60 [mu] m ~ 90 [mu] m or 75 [mu] m ~ 90 [mu] m. Further, in FIGS. 25A and 25B, the thickness t d of the neighboring portion 56 is 50 μm to 75 μm or 60 μm to 75 μm.
　このように、近傍部分５６の幅ｗｄを６０μｍ又は７５μｍ以上とし、厚みｔｄを５０μｍ又は６０μｍ以上としたことにより、インナーリード５１、６１のつけ根にあたる部分（近傍部分５６）の強度を保持し、インナーリード５１、６１の強度が低下することが抑えられ、インナーリード５１、６１に変形が生じることを防止することができる。また、上記近傍部分５６の幅ｗｄを９０μｍ以下とし、厚みｔｄを７５μｍ以下としたことにより、リード部１２Ａ、１２Ｂ間の間隔を狭くすることができるので、各半導体装置２０Ｆの外部端子１７Ａ、１７Ｂの数（ピン数）を増やすことができる。 Thus, the width w d of the portion near 56 and 60μm or 75μm or more, by the thickness t d was 50μm or 60μm or more, maintains the strength of the portion (portion near 56) corresponding to the base of the inner leads 51 and 61 It is possible to suppress the strength of the inner leads 51 and 61 from being lowered, and to prevent the inner leads 51 and 61 from being deformed. Further, by setting the width w d of the neighboring portion 56 to 90 μm or less and the thickness t d to 75 μm or less, the interval between the lead portions 12A and 12B can be narrowed, so that the external terminal 17A of each semiconductor device 20F can be reduced. , 17B (number of pins) can be increased.
　なお、図２４において、互いに隣接するリード部１２Ａ、１２Ｂ間の間隔ｄは、９０μｍ～１５０μｍとすることが好ましい。このように、間隔ｄを９０μｍ以上とすることにより、互いに隣接するリード部１２Ａ、１２Ｂ間の貫通部分をエッチングにより確実に形成することができる。また、上記間隔ｄを１５０μｍ以下とすることにより、各半導体装置２０Ｆの外部端子１７Ａ、１７Ｂの数（ピン数）を一定数以上確保することができる。具体的には、外部端子１７Ａ、１７Ｂの数（ピン数）は、例えば８０ピン～２５０ピンとすることができる。 In FIG. 24, the distance d between the adjacent lead portions 12A and 12B is preferably 90 μm to 150 μm. As described above, by setting the distance d to 90 μm or more, it is possible to reliably form through portions between the adjacent lead portions 12A and 12B by etching. Further, by setting the distance d to 150 μm or less, the number of external terminals 17A and 17B (number of pins) of each semiconductor device 20F can be secured at a certain number or more. Specifically, the number of external terminals 17A and 17B (number of pins) can be set to 80 to 250 pins, for example.
　以上説明したリードフレーム１０Ｆは、７５０ＭＰａ～１１００ＭＰａ又は８５０ＭＰａ～１１００ＭＰａの引張強度、好ましくは９２０ＭＰａ～１０１０ＭＰａの引張強度をもつ金属材料から構成されている。リードフレーム１０Ｆが７５０ＭＰａ又は８５０ＭＰａ以上の引張強度をもつ金属材料から構成されることにより、リード部１２Ａ、１２Ｂの強度が低下して変形が生じることが抑えられるので、リード部１２Ａ、１２Ｂ間の間隔を狭くすることができる。また、一般に、引張強度の高い金属材料は、導電性が低くなる傾向にある。このため、リードフレーム１０Ｆを１１００ＭＰａ以下の引張強度をもつ金属材料から構成することにより、リード部１２Ａ、１２Ｂの導電性が低下することを防止することができる。 The lead frame 10F described above is made of a metal material having a tensile strength of 750 MPa to 1100 MPa or 850 MPa to 1100 MPa, preferably a tensile strength of 920 MPa to 1010 MPa. Since the lead frame 10F is made of a metal material having a tensile strength of 750 MPa or 850 MPa or more, the strength of the lead portions 12A and 12B is prevented from being reduced and deformation is prevented, so the distance between the lead portions 12A and 12B Can be narrowed. In general, a metal material having high tensile strength tends to have low conductivity. For this reason, it can prevent that the electroconductivity of lead part 12A, 12B falls by comprising the lead frame 10F from the metal material which has a tensile strength of 1100 Mpa or less.
　このような金属材料としては、銅合金等が挙げられ、具体的には、例えばコルソン系合金（Ｃｕ－Ｎｉ－Ｓｉ）、ニッケル錫銅合金（Ｃｕ－Ｎｉ－Ｓｎ）、チタニウム銅合金（Ｃｕ－Ｔｉ）などを挙げることができる。 Examples of such a metal material include a copper alloy, and specifically, for example, a Corson alloy (Cu—Ni—Si), a nickel tin copper alloy (Cu—Ni—Sn), a titanium copper alloy (Cu—). Ti).
　また、リードフレーム１０Ｆの厚みは、製造する半導体装置２０Ｆの構成にもよるが、８０μｍ～２５０μｍとすることができる。 Further, the thickness of the lead frame 10F can be set to 80 μm to 250 μm depending on the configuration of the semiconductor device 20F to be manufactured.
　なお、図２２において、リード部１２Ａ、１２Ｂは、ダイパッド１１の４辺全てに沿って配置されているが、これに限られるものではなく、例えばダイパッド１１の対向する２辺のみに沿って配置されていても良い。 In FIG. 22, the lead portions 12A and 12B are arranged along all four sides of the die pad 11, but the present invention is not limited to this. For example, the lead portions 12A and 12B are arranged along only two opposite sides of the die pad 11. May be.
　半導体装置の構成
　次に、図２７および図２８により、本実施の形態による半導体装置について説明する。図２７および図２８は、本実施の形態による半導体装置（ＤＲ－ＱＦＮ（Dual Row QFN）タイプ）を示す図である。 Configuration of Semiconductor Device Next, the semiconductor device according to the present embodiment will be described with reference to FIGS. 27 and 28 are diagrams showing a semiconductor device (DR-QFN (Dual Row QFN) type) according to the present embodiment.
　図２７および図２８に示すように、半導体装置（半導体パッケージ）２０Ｆは、ダイパッド１１と、ダイパッド１１の周囲に配置された複数のリード部１２Ａ、１２Ｂと、ダイパッド１１上に搭載された半導体素子２１と、リード部１２Ａ、１２Ｂと半導体素子２１とを電気的に接続する複数のボンディングワイヤ（接続部材）２２とを備えている。また、ダイパッド１１、リード部１２Ａ、１２Ｂ、半導体素子２１およびボンディングワイヤ２２は、封止樹脂２３によって樹脂封止されている。 As shown in FIGS. 27 and 28, the semiconductor device (semiconductor package) 20F includes a die pad 11, a plurality of lead portions 12A and 12B arranged around the die pad 11, and a semiconductor element 21 mounted on the die pad 11. And a plurality of bonding wires (connection members) 22 for electrically connecting the lead portions 12A and 12B and the semiconductor element 21. The die pad 11, the lead portions 12 </ b> A and 12 </ b> B, the semiconductor element 21 and the bonding wire 22 are resin-sealed with a sealing resin 23.
　このうちダイパッド１１およびリード部１２Ａ、１２Ｂは、上述したリードフレーム１０Ｆから作製されたものである。このダイパッド１１およびリード部１２Ａ、１２Ｂの構成は、単位リードフレーム１０ａに含まれない領域を除き、上述した図２２乃至図２６に示すものと同様であり、ここでは詳細な説明を省略する。また、半導体素子２１、ボンディングワイヤ２２、封止樹脂２３、接着剤２４およびめっき部２５の構成については、第１の実施の形態と略同様であるので、詳細な説明を省略する。 Among these, the die pad 11 and the lead portions 12A and 12B are manufactured from the lead frame 10F described above. The configurations of the die pad 11 and the lead portions 12A and 12B are the same as those shown in FIGS. 22 to 26 described above except for the region not included in the unit lead frame 10a, and detailed description thereof will be omitted here. Further, the configurations of the semiconductor element 21, the bonding wire 22, the sealing resin 23, the adhesive 24, and the plating portion 25 are substantially the same as those in the first embodiment, and thus detailed description thereof is omitted.
　リードフレームの製造方法
　次に、図２２乃至図２６に示すリードフレーム１０Ｆの製造方法について、図２９（ａ）－（ｆ）を用いて説明する。なお、図２９（ａ）－（ｆ）は、リードフレーム１０Ｆの製造方法を示す断面図（図２３に対応する図）である。 Manufacturing Method of Lead Frame Next, a manufacturing method of the lead frame 10F shown in FIGS. 22 to 26 will be described with reference to FIGS. 29 (a) to 29 (f). 29A to 29F are cross-sectional views (corresponding to FIG. 23) showing the manufacturing method of the lead frame 10F.
　まず図２９（ａ）に示すように、平板状の金属基板３１を準備する。この金属基板３１としては、７５０ＭＰａ～１１００ＭＰａ又は８５０ＭＰａ～１１００ＭＰａの引張強度をもつものが用いられ、例えば例えばコルソン系合金（Ｃｕ－Ｎｉ－Ｓｉ）、ニッケル錫銅合金（Ｃｕ－Ｎｉ－Ｓｎ）、チタニウム銅合金（Ｃｕ－Ｔｉ）等の銅合金からなる基板を使用することができる。なお金属基板３１は、その両面に対して脱脂等を行い、洗浄処理を施したものを使用することが好ましい。 First, as shown in FIG. 29A, a flat metal substrate 31 is prepared. As the metal substrate 31, one having a tensile strength of 750 MPa to 1100 MPa or 850 MPa to 1100 MPa is used. For example, Corson alloy (Cu—Ni—Si), nickel tin copper alloy (Cu—Ni—Sn), titanium A substrate made of a copper alloy such as a copper alloy (Cu—Ti) can be used. In addition, it is preferable to use what the metal substrate 31 performed the degreasing | defatting etc. to the both surfaces, and performed the washing process.
　次に、金属基板３１の表裏全体にそれぞれ感光性レジスト３２ａ、３３ａを塗布し、これを乾燥する（図２９（ｂ））。なお感光性レジスト３２ａ、３３ａとしては、従来公知のものを使用することができる。 Next, photosensitive resists 32a and 33a are applied to the entire front and back surfaces of the metal substrate 31, respectively, and dried (FIG. 29B). As the photosensitive resists 32a and 33a, conventionally known resists can be used.
　続いて、この金属基板３１に対してフォトマスクを介して露光し、現像することにより、所望の開口部３２ｂ、３３ｂを有するエッチング用レジスト層３２、３３を形成する（図２９（ｃ））。 Subsequently, the metal substrate 31 is exposed through a photomask and developed to form etching resist layers 32 and 33 having desired openings 32b and 33b (FIG. 29C).
　次に、エッチング用レジスト層３２、３３を耐腐蝕膜として金属基板３１に腐蝕液でエッチングを施す（図２９（ｄ））。これにより、ダイパッド１１および複数のリード部１２Ａ、１２Ｂの外形が形成される。腐蝕液は、使用する金属基板３１の材質に応じて適宜選択することができ、例えば、金属基板３１として銅合金を用いる場合、通常、塩化第二鉄水溶液を使用し、金属基板３１の両面からスプレーエッチングにて行うことができる。なお、第１の実施の形態の場合と同様に、金属基板３１の片面ずつ２段階のスプレーエッチングを行っても良い。 Next, etching is performed on the metal substrate 31 with the etching solution using the etching resist layers 32 and 33 as corrosion resistant films (FIG. 29D). Thereby, the outer shape of the die pad 11 and the plurality of lead portions 12A and 12B is formed. The corrosive liquid can be appropriately selected according to the material of the metal substrate 31 to be used. For example, when a copper alloy is used as the metal substrate 31, a ferric chloride aqueous solution is usually used from both sides of the metal substrate 31. It can be performed by spray etching. As in the case of the first embodiment, two stages of spray etching may be performed for each side of the metal substrate 31.
　その後、エッチング用レジスト層３２、３３を剥離して除去する（図２９（ｅ））。 Thereafter, the etching resist layers 32 and 33 are peeled off and removed (FIG. 29E).
　次に、ボンディングワイヤ２２と内部端子１５との密着性を向上させるため、内部端子１５にメッキ処理を施し、めっき部２５を形成する（図２９（ｆ））。この場合、選択されるメッキ種は、ボンディングワイヤ２２との密着性を確保できればその種類は問わないが、たとえばＡｇやＡｕなどの単層めっきでもよいし、Ｎｉ／ＰｄやＮｉ／Ｐｄ／Ａｕがこの順に積層される複層めっきでもよい。また、めっき部２５は、リード部１２Ａ、１２Ｂのうちボンディングワイヤ２２との接続部のみに施してもよいし、リードフレーム１０Ｆの全面に施してもよい。 Next, in order to improve the adhesion between the bonding wire 22 and the internal terminal 15, the internal terminal 15 is plated to form a plated portion 25 (FIG. 29 (f)). In this case, the type of plating selected is not limited as long as the adhesion to the bonding wire 22 can be ensured. For example, single-layer plating such as Ag or Au may be used, or Ni / Pd or Ni / Pd / Au may be used. Multi-layer plating laminated in this order may be used. Moreover, the plating part 25 may be provided only on the connection part with the bonding wire 22 among the lead parts 12A and 12B, or may be provided on the entire surface of the lead frame 10F.
　このようにして、図２２乃至図２６に示すリードフレーム１０Ｆが得られる。 In this way, the lead frame 10F shown in FIGS. 22 to 26 is obtained.
　半導体装置の製造方法
　次に、図２７および図２８に示す半導体装置２０Ｆの製造方法について、図３０（ａ）－（ｅ）を用いて説明する。 Method for Manufacturing Semiconductor Device Next, a method for manufacturing the semiconductor device 20F shown in FIGS. 27 and 28 will be described with reference to FIGS. 30 (a) to 30 (e).
　まず上述したように、図２９（ａ）－（ｆ）に示す方法により、リードフレーム１０Ｆを作製する（図３０（ａ））。 First, as described above, the lead frame 10F is manufactured by the method shown in FIGS. 29A to 29F (FIG. 30A).
　次に、リードフレーム１０Ｆのダイパッド１１上に、半導体素子２１を搭載する。この場合、例えばダイボンディングペースト等の接着剤２４を用いて、半導体素子２１をダイパッド１１上に載置して固定する（ダイアタッチ工程）（図３０（ｂ））。 Next, the semiconductor element 21 is mounted on the die pad 11 of the lead frame 10F. In this case, for example, the semiconductor element 21 is mounted on the die pad 11 and fixed using an adhesive 24 such as a die bonding paste (die attachment step) (FIG. 30B).
　次に、半導体素子２１の各電極２１ａと、各リード部１２Ａ、１２Ｂのめっき部２５（内部端子１５）とを、それぞれボンディングワイヤ（接続部材）２２によって互いに電気的に接続する（ワイヤボンディング工程）（図３０（ｃ））。 Next, the electrodes 21a of the semiconductor element 21 and the plating portions 25 (internal terminals 15) of the lead portions 12A and 12B are electrically connected to each other by bonding wires (connection members) 22 (wire bonding step). (FIG. 30 (c)).
　このとき、リードフレーム１０Ｆをワイヤボンディング装置のヒートブロック３６上に載置する。次いで、ヒートブロック３６によりリード部１２Ａのインナーリード５１及びリード部１２Ｂのインナーリード６１の裏面側から加熱する。これとともに、ワイヤボンディング装置のキャピラリー（図示せず）を介して超音波を印加しながら、半導体素子２１の各電極２１ａと各リード部１２Ａ、１２Ｂのめっき部２５とをボンディングワイヤ２２を用いて電気的に接続する。 At this time, the lead frame 10F is placed on the heat block 36 of the wire bonding apparatus. Next, the heat block 36 heats from the back side of the inner lead 51 of the lead portion 12A and the inner lead 61 of the lead portion 12B. At the same time, while applying ultrasonic waves through a capillary (not shown) of the wire bonding apparatus, the electrodes 21a of the semiconductor element 21 and the plating portions 25 of the lead portions 12A and 12B are electrically connected using the bonding wires 22. Connect.
　この場合、リード部１２Ａのインナーリード５１及びリード部１２Ｂのインナーリード６１が、それぞれ平坦な裏面を有していることにより、リード部１２Ａ、１２Ｂをヒートブロック３６に対して安定して載置することができる。これにより、ボンディングワイヤ２２をめっき部２５に対して安定して接続することが可能となる。 In this case, since the inner lead 51 of the lead portion 12A and the inner lead 61 of the lead portion 12B have flat back surfaces, the lead portions 12A and 12B are stably placed on the heat block 36. be able to. Thereby, the bonding wire 22 can be stably connected to the plating portion 25.
　次に、リードフレーム１０Ｆに対して熱硬化性樹脂または熱可塑性樹脂を射出成形またはトランスファ成形することにより、封止樹脂２３を形成する（図３０（ｄ））。このようにして、リードフレーム１０Ｆ、半導体素子２１、リード部１２Ａ、１２Ｂおよびボンディングワイヤ２２を封止する。 Next, the sealing resin 23 is formed by injection molding or transfer molding of a thermosetting resin or a thermoplastic resin to the lead frame 10F (FIG. 30D). In this way, the lead frame 10F, the semiconductor element 21, the lead portions 12A and 12B, and the bonding wire 22 are sealed.
　次に、各半導体素子２１間の封止樹脂２３をダイシングすることにより、リードフレーム１０Ｆを各単位リードフレーム１０ａ（図２２参照）毎に分離する。この際、例えばダイヤモンド砥石からなるブレード（図示せず）を回転させながら、各単位リードフレーム１０ａ間のリードフレーム１０Ｆおよび封止樹脂２３を切断しても良い。 Next, the lead frame 10F is separated for each unit lead frame 10a (see FIG. 22) by dicing the sealing resin 23 between the semiconductor elements 21. At this time, the lead frames 10F and the sealing resin 23 between the unit lead frames 10a may be cut while rotating a blade (not shown) made of, for example, a diamond grindstone.
　このようにして、図２７および図２８に示す半導体装置２０Ｆが得られる（図３０（ｅ））。 Thus, the semiconductor device 20F shown in FIGS. 27 and 28 is obtained (FIG. 30 (e)).
　ところで、本実施の形態において、リードフレーム１０Ｆは、７５０ＭＰａ～１１００ＭＰａ又は８５０ＭＰａ～１１００ＭＰａの引張強度をもつ金属材料から構成され、各単位リードフレーム１０ａのリード部１２Ａ、１２Ｂのうち、支持リード１３の近傍部分５５の幅は、６０μｍ～９０μｍ又は７５μｍ～９０μｍとなり、かつ当該近傍部分５５の厚みは、５０μｍ～７５μｍ又は６０μｍ～７５μｍとなっている。これにより、リード部１２Ａ、１２Ｂの強度が低下することが抑えられるので、例えば上述した半導体装置２０Ｆの製造工程において、リード部１２Ａ、１２Ｂに歪みや曲り等の変形が生じることを防止することができる。この結果、隣接するリード部１２Ａとリード部１２Ｂとの間隔ｄ（ピッチ）を狭めることができ、半導体装置２０Ｆの外部端子１７Ａ、１７Ｂの数（ピン数）を増やすことができる。具体的には、従来の半導体装置と比べてリード部１２Ａ、１２Ｂのピッチを１０％以上狭めることが可能となる。例えば、半導体装置２０Ｆのサイズが１４ｍｍ×１４ｍｍである場合、外部端子１７Ａ、１７Ｂの数（ピン数）を２００ピン以上に増やすことができる。 By the way, in the present embodiment, the lead frame 10F is made of a metal material having a tensile strength of 750 MPa to 1100 MPa or 850 MPa to 1100 MPa, and in the vicinity of the support lead 13 among the lead portions 12A and 12B of each unit lead frame 10a. The width of the portion 55 is 60 μm to 90 μm or 75 μm to 90 μm, and the thickness of the neighboring portion 55 is 50 μm to 75 μm or 60 μm to 75 μm. As a result, the strength of the lead portions 12A and 12B can be prevented from lowering, and therefore, for example, in the manufacturing process of the semiconductor device 20F described above, it is possible to prevent the lead portions 12A and 12B from being deformed such as distortion or bending. it can. As a result, the distance d (pitch) between the adjacent lead portions 12A and 12B can be reduced, and the number of external terminals 17A and 17B (number of pins) of the semiconductor device 20F can be increased. Specifically, the pitch of the lead portions 12A and 12B can be narrowed by 10% or more as compared with the conventional semiconductor device. For example, when the size of the semiconductor device 20F is 14 mm × 14 mm, the number of external terminals 17A and 17B (number of pins) can be increased to 200 pins or more.
　また、隣接するリード部１２Ａ、１２Ｂ間の間隔を狭くした場合であっても、リード部１２Ａ、１２Ｂの強度が低下することが抑えられ、リード部１２Ａ、１２Ｂが変形して外部端子１７Ａ、１７Ｂに位置ずれが発生する不具合を防止することができる。これにより、リードフレーム１０Ｆの歩留まりを高めることができる。 In addition, even when the interval between the adjacent lead portions 12A and 12B is narrowed, the strength of the lead portions 12A and 12B is suppressed from decreasing, and the lead portions 12A and 12B are deformed to cause external terminals 17A and 17B. It is possible to prevent a problem that the position shift occurs. Thereby, the yield of the lead frame 10F can be increased.
　さらに、リード部１２Ａ、１２Ｂの強度を高めたことにより、リード部１２Ａ、１２Ｂの長さを長くすることできるので、内部端子１５をダイパッド１１に対して接近させることができる。これにより、高価なボンディングワイヤ２２の使用量を減らすことができ、リードフレーム１０Ｆの製造コストを低下させることができる。 Furthermore, since the length of the lead portions 12A and 12B can be increased by increasing the strength of the lead portions 12A and 12B, the internal terminal 15 can be brought closer to the die pad 11. Thereby, the usage-amount of the expensive bonding wire 22 can be reduced, and the manufacturing cost of the lead frame 10F can be reduced.
　なお、上記実施の形態では、リード部１２Ａとリード部１２Ｂとが交互に配置されている場合を例にとって説明した。しかしながら、これに限らず、リードフレーム１０Ｆは、互いに同一の長さをもつ複数のリード部を有していても良い（ＱＦＮタイプ）。 In the above embodiment, the case where the lead portions 12A and the lead portions 12B are alternately arranged has been described as an example. However, the present invention is not limited to this, and the lead frame 10F may have a plurality of lead portions having the same length (QFN type).
　さらに、上記実施の形態では、内側外部端子１７Ａおよび外側外部端子１７Ｂが千鳥状に２列に配置されている場合を例にとって説明したが、これに限らず、外部端子が３列以上に配置されていても良い。 Furthermore, in the above embodiment, the case where the inner external terminals 17A and the outer external terminals 17B are arranged in two rows in a staggered manner has been described as an example. However, the present invention is not limited to this, and the external terminals are arranged in three or more rows. May be.
　次に、本実施の形態における具体的実施例について説明する。 Next, specific examples in the present embodiment will be described.
　（実施例１）
　本実施の形態による構成からなるリードフレーム１０Ｆ（実施例１）を作製した。この場合、３．７５質量％のＮｉ、０．９質量％のＳｉ、０．５質量％のＺｎ、０．１５質量％のＳｎを含有し、残部が銅および不可避不純物からなる銅合金（古河電気工業株式会社製、商品名ＥＦＴＥＣ－９８Ｓ）の金属基板３１を準備した。この金属基板３１の厚みは２００μｍであり、金属基板３１の引張強度は８６０ＭＰａであった。なお、金属基板３１の引張強度は、金属基板３１を幅２０ｍｍに裁断し、ＪＩＳ　Ｚ２２０１に基づいて試験片を作製し、引張試験機を用いることにより測定した。この金属基板３１を３００ｍｍ×１００ｍｍの大きさに切断してエッチング加工することにより、２５０ｍｍ×７０ｍｍの大きさのリードフレーム１０Ｆ（実施例１）を得た。前記エッチング加工においては、金属基板の両面からスプレーエッチングを行い（エッチング工程）、その後、アルカリ水溶液によってレジストをスプレー方式で剥離し（レジスト剥離工程）、最終洗浄をスプレー方式で行った（最終水洗工程）。上記３つの工程におけるスプレー時間は合計で１０分とし、スプレー圧は０．２Ｍｐａとした。得られたリードフレームはチップを５６個配置できる形状（５６面付）とし、１面付当りのリード部の本数は１５６本とした。また、各リード部１２Ａ、１２Ｂのうち、支持リード１３の近傍部分５５の幅をそれぞれ７５μｍとし、近傍部分５５の厚みをそれぞれ６０μｍとした。 (Example 1)
A lead frame 10F (Example 1) having the configuration according to the present embodiment was manufactured. In this case, a copper alloy (Furukawa) containing 3.75% by mass of Ni, 0.9% by mass of Si, 0.5% by mass of Zn, 0.15% by mass of Sn, with the balance being copper and inevitable impurities. A metal substrate 31 manufactured by Denki Kogyo Co., Ltd. and trade name EFTEC-98S) was prepared. The thickness of the metal substrate 31 was 200 μm, and the tensile strength of the metal substrate 31 was 860 MPa. The tensile strength of the metal substrate 31 was measured by cutting the metal substrate 31 into a width of 20 mm, preparing a test piece based on JIS Z2201, and using a tensile tester. The metal substrate 31 was cut into a size of 300 mm × 100 mm and etched to obtain a lead frame 10F (Example 1) having a size of 250 mm × 70 mm. In the etching process, spray etching is performed from both surfaces of the metal substrate (etching process), and then the resist is stripped by an alkaline aqueous solution by a spray method (resist stripping process), and the final cleaning is performed by a spray method (final water washing step). ). The total spray time in the above three steps was 10 minutes, and the spray pressure was 0.2 MPa. The obtained lead frame had a shape (with 56 surfaces) in which 56 chips could be arranged, and the number of lead portions per surface was 156. Further, in each of the lead portions 12A and 12B, the width of the vicinity portion 55 of the support lead 13 is 75 μm, and the thickness of the vicinity portion 55 is 60 μm.
　（実施例２）
　金属基板３１の引張強度が７８０ＭＰａであり、各リード部１２Ａ、１２Ｂの支持リード１３の近傍部分５５の幅をそれぞれ６０μｍとし、近傍部分５５の厚みをそれぞれ５０μｍとしたこと、以外は、実施例１と同様にして、実施例１と同じ形状のリードフレームを作製した。 (Example 2)
Example 1 except that the tensile strength of the metal substrate 31 is 780 MPa, the width of the vicinity 55 of the support lead 13 of each lead portion 12A, 12B is 60 μm, and the thickness of the vicinity 55 is 50 μm. In the same manner, a lead frame having the same shape as in Example 1 was produced.
　（比較例１）
　金属基板の材料として、３．０質量％のＮｉ、０．６５質量％のＳｉ、０．１５質量％のＭｇを含有し、残部が銅および不可避不純物からなる銅合金（ＪＸ日鉱日石金属株式会社製、商品名Ｃ７０２５ １／２Ｈ）を用いたこと、以外は、実施例１と同様にして、実施例１と同じ形状のリードフレームを作製した。当該金属基板の引張強度を測定したところ、７２６ＭＰａであった。 (Comparative Example 1)
Copper alloy containing 3.0% by mass of Ni, 0.65% by mass of Si, 0.15% by mass of Mg as the material of the metal substrate, with the balance being copper and inevitable impurities (JX Nippon Mining & Metals Corporation) A lead frame having the same shape as in Example 1 was produced in the same manner as in Example 1 except that the product made by the company, trade name C7025 1 / 2H) was used. The tensile strength of the metal substrate was measured and found to be 726 MPa.
　上記３種類のリードフレーム（実施例１、実施例２および比較例１）について、それぞれリード部に変形が生じるか否かの試験を実施した。 The above-mentioned three types of lead frames (Example 1, Example 2 and Comparative Example 1) were each tested for whether or not the lead part was deformed.
　この試験の方法は、各リードフレームを作製する間にリード部に変形が生じたか否かを判定することによって実施した。すなわち、前記エッチング工程、レジスト剥離工程、最終水洗工程において、スプレーによる衝撃を受けることによって、衝撃を受けた部位に所望の強度があるかどうかを確認した。 This test method was carried out by determining whether or not the lead portion was deformed during the production of each lead frame. That is, in the etching step, resist stripping step, and final water washing step, it was confirmed whether or not the impacted portion had a desired strength by receiving an impact by spraying.
　各リードフレームについて、インナーリードに具備された外部端子近辺、および支持リードの変形を計測した。この計測方法としては、金属顕微鏡による焦点深度計測を用い、リードフレームの板厚方向に対して変形している高さを計測した。尚、前記変形している高さが外観を目視で検査しても判定にしくい３０μｍ以下である場合には、変形が生じていないと判断した。 For each lead frame, the deformation of the vicinity of the external terminal provided on the inner lead and the support lead was measured. As this measurement method, depth of focus measurement using a metal microscope was used, and the height of the lead frame deformed in the thickness direction was measured. When the deformed height is 30 μm or less, which is difficult to determine even by visual inspection of the appearance, it was determined that no deformation occurred.
　尚、実施例１、実施例２および比較例１のいずれも、１０枚のリードフレームを作製した。作製された各々のリードフレームについて、変形が発生したリード部の本数を測定し、リードフレーム１枚当たりでの変形した本数を算出した。さらに、算出されたリードフレーム１枚当たりでの変形したリード部の本数から、１チップ（１面付）当たりでの変形が発生したリード部の本数を算出した。この結果を表１に示す。 In all of Example 1, Example 2, and Comparative Example 1, 10 lead frames were produced. For each manufactured lead frame, the number of lead portions where deformation occurred was measured, and the number of deformed leads per lead frame was calculated. Further, the number of lead portions deformed per chip (with one surface) was calculated from the calculated number of deformed lead portions per lead frame. The results are shown in Table 1.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　この結果、実施例１および実施例２のリードフレーム１０Ｆについては、リード部１２Ａ、１２Ｂに変形が発生しなかった。これに対して比較例１のリードフレームについては、その一部に変形が発生した。 As a result, the lead frames 10F of Example 1 and Example 2 were not deformed in the lead portions 12A and 12B. On the other hand, the lead frame of Comparative Example 1 was partially deformed.
　（第６の実施の形態）
　次に、図３１乃至図３４を参照して本発明の第６の実施の形態について説明する。図３１乃至図３４は本発明の第６の実施の形態を示す図である。図３１乃至図３４において、接続リング１４のハーフエッチング部（凹部）が、接続リング１４の全周にわたって連続的に設けられるのでなく、接続リング１４に沿って規則的に設けられており、各ハーフエッチング部の間には厚肉部２８ａが形成されている。図３１乃至図３４において、第１の実施の形態乃至第５の実施の形態と同一部分には同一の符号を付して詳細な説明は省略する。 (Sixth embodiment)
Next, a sixth embodiment of the present invention will be described with reference to FIGS. 31 to 34 are views showing a sixth embodiment of the present invention. 31 to 34, the half-etched portion (recessed portion) of the connection ring 14 is not provided continuously over the entire circumference of the connection ring 14 but is provided regularly along the connection ring 14. A thick portion 28a is formed between the etched portions. In FIG. 31 to FIG. 34, the same parts as those in the first to fifth embodiments are denoted by the same reference numerals, and detailed description thereof is omitted.
　図３１および図３２（ａ）（ｂ）に示すリードフレーム１０Ｇにおいて、接続リング１４は、リード部１２Ａ、１２Ｂのインナーリード５１の先端側に設けられており、ダイパッド１１を取り囲むように配置されている。接続リング１４の外側周縁部（支持リード１３側周縁部）には、リード部１２Ａ、１２Ｂのインナーリード５１が連結されている。また、接続リング１４から内側（ダイパッド１１側）に向けて、連結バー１９が延出している。この場合、接続リング１４は、全てのインナーリード５１に連結されて支持されているが、これに限らず、接続リング１４は一部のインナーリード５１のみに連結されて支持されていても良い。 In the lead frame 10G shown in FIGS. 31 and 32A and 32B, the connection ring 14 is provided on the distal end side of the inner lead 51 of the lead portions 12A and 12B, and is disposed so as to surround the die pad 11. Yes. Inner leads 51 of the lead portions 12 </ b> A and 12 </ b> B are coupled to the outer peripheral edge (the support lead 13 side peripheral edge) of the connection ring 14. A connecting bar 19 extends from the connection ring 14 toward the inside (on the die pad 11 side). In this case, the connection ring 14 is connected to and supported by all the inner leads 51, but the present invention is not limited to this, and the connection ring 14 may be connected to and supported by only some of the inner leads 51.
　接続リング１４の表面であって各インナーリード５１の先端近傍に、それぞれ凹部１４ｃが形成されている。各凹部１４ｃは、ハーフエッチングにより形成されたものであり、厚み方向に貫通することなく一定の深さを持っている。なお、各凹部１４ｃは、接続リング１４の幅方向略中央部に形成されている。 A recess 14 c is formed on the surface of the connection ring 14 and in the vicinity of the tip of each inner lead 51. Each recess 14c is formed by half etching, and has a certain depth without penetrating in the thickness direction. Each concave portion 14 c is formed at a substantially central portion in the width direction of the connection ring 14.
　また、互いに隣接する凹部１４ｃの間には、厚肉部２８ａが形成されている。すなわち凹部１４ｃと厚肉部２８ａとは、接続リング１４の長さ方向に沿って交互に配置されている。この場合、厚肉部２８ａは、ハーフエッチングされておらず、ダイパッド１１および支持リード１３と同一の厚みを有している。また、連結バー１９は、ダイパッド１１の４辺全てにそれぞれ２本ずつ連結されている。ダイパッド１１は、接続リング１４および連結バー１９によって支持されている。一方、ダイパッド１１の四隅には吊りリードが設けられていないので、ダイパッド１１の四隅近傍にもリード部１２Ａ、１２Ｂを配置することができる。このため、ダイパッド１１が吊りリードを介して支持される場合と比較して、リード部１２Ａ、１２Ｂの本数を増やすことができる。 Further, a thick portion 28a is formed between the concave portions 14c adjacent to each other. That is, the concave portions 14 c and the thick portions 28 a are alternately arranged along the length direction of the connection ring 14. In this case, the thick portion 28 a is not half-etched and has the same thickness as the die pad 11 and the support lead 13. Two connecting bars 19 are connected to all four sides of the die pad 11. The die pad 11 is supported by a connection ring 14 and a connection bar 19. On the other hand, since the suspension leads are not provided at the four corners of the die pad 11, the lead portions 12 </ b> A and 12 </ b> B can be arranged near the four corners of the die pad 11. For this reason, compared with the case where the die pad 11 is supported via a suspension lead, the number of lead parts 12A and 12B can be increased.
　本実施の形態において、半導体装置２０Ｇ（図３３参照）を作製する際、接続リング１４のうち各凹部１４ｃの周辺の土手部と、接続リング１４のうち各凹部１４ｃの間に位置する厚肉部２８ａとは、同時にエッチングされはじめるが、厚肉部２８ａの除去には、各凹部１４ｃが設けられた領域よりも時間がかかり、これにより接続リング１４自体のエッチングの進行を調整することが可能である。 In the present embodiment, when manufacturing the semiconductor device 20G (see FIG. 33), a thick wall portion located between the bank portion around each recess 14c in the connection ring 14 and each recess portion 14c in the connection ring 14. 28a begins to be etched at the same time, but the removal of the thick portion 28a takes more time than the region in which the concave portions 14c are provided, and this allows the etching progress of the connection ring 14 itself to be adjusted. is there.
　すなわち、リードフレーム１０Ｇの裏面側から接続リング１４をエッチング除去する際（図７（ｅ）参照）、リードフレーム１０および封止樹脂２３の裏面のエッチング用レジスト層３４の接続リング１４に対応する位置に開口部３４ａを設けておく。そして当該開口部３４ａから進入した腐蝕液により、接続リング１４のうち各凹部１４ｃと厚肉部２８ａとを適度に溶解して除去する。この場合、接続リング１４の表面に凹部１４ｃが設けられているので、開口部３４ａから進入した腐蝕液が、リード部１２Ａ、１２Ｂを必要以上に溶解することなく、接続リング１４の全体を適切に除去することができる。 That is, when the connection ring 14 is etched away from the back surface side of the lead frame 10G (see FIG. 7E), the position corresponding to the connection ring 14 of the etching resist layer 34 on the back surface of the lead frame 10 and the sealing resin 23. An opening 34a is provided in the front. Then, the recesses 14c and the thick portions 28a in the connection ring 14 are appropriately dissolved and removed by the corrosive liquid entering from the openings 34a. In this case, since the concave portion 14c is provided on the surface of the connection ring 14, the corrosive liquid entering from the opening 34a properly dissolves the entire connection ring 14 without dissolving the lead portions 12A and 12B more than necessary. Can be removed.
　なお、本実施の形態において、凹部１４ｃは、全てのインナーリード５１の先端近傍に設けられているが、これに限らず、一部のインナーリード５１の先端近傍のみに設けられていても良い。 In the present embodiment, the recesses 14 c are provided in the vicinity of the tips of all the inner leads 51. However, the present invention is not limited to this, and the recesses 14 c may be provided only in the vicinity of the tips of some of the inner leads 51.
　このように、接続リング１４に沿って凹部１４ｃを一定間隔でドット状に設け、各凹部１４ｃの間に厚肉部２８ａを形成したことにより、接続リング１４をエッチングにより除去する際、腐蝕液の進入と溶解とを適宜調整することができる。 As described above, the concave portions 14c are provided in the form of dots at regular intervals along the connection ring 14, and the thick portions 28a are formed between the concave portions 14c. Ingress and dissolution can be adjusted as appropriate.
　図３４に示す半導体装置２０Ｈは、本実施の形態の変形例を示しており、厚肉部２８ａを完全に除去せず、半導体装置２０Ｈ内部に残した形態を示している。この半導体装置２０Ｈは、図３１および図３２（ａ）（ｂ）に示すリードフレーム１０Ｇから作製されたものであり、厚肉部２８ａは、完全に除去されることなく残されて、第２端子部を構成している。この厚肉部２８ａは、ダイパッド１１の周囲４辺（図３４においてＸ方向又はＹ方向に平行な４辺）の全てに沿って、互いに間隔を空けて配列されている。 A semiconductor device 20H shown in FIG. 34 shows a modification of the present embodiment, in which the thick portion 28a is not completely removed and is left inside the semiconductor device 20H. This semiconductor device 20H is manufactured from the lead frame 10G shown in FIGS. 31 and 32A and 32B, and the thick portion 28a is left without being completely removed, and the second terminal Part. The thick portions 28a are arranged at intervals from each other along all four sides (four sides parallel to the X direction or Y direction in FIG. 34) around the die pad 11.
　図３４において、厚肉部２８ａは、接続リング１４の一部から形成されるため、各インナーリード５１の先端近傍を結ぶ直線に沿って配置される。図３４においては、複数の厚肉部２８ａは、ダイパット１１とインナーリード５１の先端の間の領域に矩形状に配置されている。 34, since the thick portion 28a is formed from a part of the connection ring 14, it is arranged along a straight line connecting the vicinity of the tip of each inner lead 51. In FIG. 34, the plurality of thick portions 28 a are arranged in a rectangular shape in a region between the die pad 11 and the tip of the inner lead 51.
　この場合、リードフレーム１０Ｇの接続リング１４のうち、各凹部１４ｃの周辺領域は、封止樹脂２３によって樹脂封止された後、裏面側からエッチングにより除去されている。一方、各厚肉部２８ａは、ダイパッド１１、リード部１２Ａ、１２Ｂおよび他の厚肉部２８ａから分離されており、これらの部材から電気的に独立して第２端子部を構成している。この厚肉部２８ａは、ハーフエッチングされておらず、ダイパッド１１と同一の厚みを有している。さらに厚肉部２８ａの裏面には、外部の実装基板（図示せず）に電気的に接続される外部端子１７Ｃが形成されている。また、厚肉部２８ａの表面には、ボンディングワイヤ２２と密着性を向上させるめっき部２５が設けられており、それぞれボンディングワイヤ２２が接続されている。 In this case, in the connection ring 14 of the lead frame 10G, the peripheral region of each recess 14c is resin-sealed with the sealing resin 23 and then removed from the back side by etching. On the other hand, each thick part 28a is separated from the die pad 11, the lead parts 12A and 12B, and the other thick part 28a, and constitutes a second terminal part electrically independently from these members. The thick portion 28 a is not half-etched and has the same thickness as the die pad 11. Furthermore, an external terminal 17C that is electrically connected to an external mounting substrate (not shown) is formed on the back surface of the thick portion 28a. Moreover, the plating part 25 which improves adhesiveness with the bonding wire 22 is provided in the surface of the thick part 28a, and the bonding wire 22 is connected to each.
　また、接続リング１４のうち厚肉部２８ａを除く部分が除去されたことに伴い、封止樹脂２３の裏面のうち、リード部１２Ａ、１２Ｂとダイパッド１１との間の領域に、凹部２７が形成される。 Further, with the removal of the connection ring 14 excluding the thick portion 28a, a recess 27 is formed in the region between the lead portions 12A and 12B and the die pad 11 on the back surface of the sealing resin 23. Is done.
　図３４に示す形態によれば、半導体装置２０Ｈを作製する際、接続リング１４の一部が除去され、接続リング１４のうち除去されない部分がそれぞれ個別に分離されて第２端子部となる厚肉部２８ａが形成される。このように、多数の厚肉部２８ａが形成されていることにより、外部の実装基板と接続される端子部の数（ピン数）を増やすことができ、半導体装置２０の更なる高密度化を実現することができる。 According to the form shown in FIG. 34, when manufacturing the semiconductor device 20H, a part of the connection ring 14 is removed, and a part of the connection ring 14 that is not removed is individually separated to become the second terminal portion. A portion 28a is formed. As described above, since a large number of thick portions 28a are formed, the number of terminal portions (number of pins) connected to an external mounting substrate can be increased, and the density of the semiconductor device 20 can be further increased. Can be realized.
　図３４において、半導体装置２０Ｈ内に残された厚肉部２８ａは、必ずしも外部端子（第２端子部）として用いなくてもよい。例えば、半導体装置２０Ｈ内に残された厚肉部２８ａは、半導体装置２０Ｈに衝撃が加わった際にダイパッド１１周辺の変形を防止する役割を果たしても良い。あるいは、厚肉部２８ａは、半導体装置２０Ｈの裏面に露出する金属部分を増やすことにより、半導体装置２０Ｈの放熱性を向上させる役割を果たしても良い。 34, the thick part 28a left in the semiconductor device 20H is not necessarily used as an external terminal (second terminal part). For example, the thick portion 28a left in the semiconductor device 20H may serve to prevent deformation around the die pad 11 when an impact is applied to the semiconductor device 20H. Alternatively, the thick portion 28a may serve to improve the heat dissipation of the semiconductor device 20H by increasing the number of metal portions exposed on the back surface of the semiconductor device 20H.
　なお、本実施の形態によるリードフレーム１０Ｇの製造方法および半導体装置２０Ｇ、２０Ｃの製造方法は、第１の実施の形態によるリードフレーム１０の製造方法（図６（ａ）－（ｆ））および半導体装置２０の製造方法（図７（ａ）－（ｆ））と略同様である。 Note that the manufacturing method of the lead frame 10G and the manufacturing method of the semiconductor devices 20G and 20C according to the present embodiment are the same as the manufacturing method of the lead frame 10 according to the first embodiment (FIGS. 6A to 6F) and the semiconductor. This is substantially the same as the method for manufacturing the device 20 (FIGS. 7A to 7F).

Claims (27)

  1. 　半導体装置用のリードフレームであって、
    　半導体素子が搭載されるダイパッドと、
    　前記ダイパッド周囲に設けられ、それぞれ第１端子部を含む複数の外周リード部と、
    　前記ダイパッドと前記外周リード部との間に配置され、前記ダイパッドを取り囲む接続リングと、
    　前記接続リングによって支持され、それぞれ第２端子部を含む複数の内側リード部とを備え、
    　前記複数の内側リード部は、長内側リード部と、短内側リード部とを含み、前記長内側リード部と前記短内側リード部とが前記接続リングに沿って交互に配置されていることを特徴とするリードフレーム。     A lead frame for a semiconductor device,
    A die pad on which a semiconductor element is mounted;
    A plurality of outer peripheral lead portions provided around the die pad, each including a first terminal portion;
    A connection ring disposed between the die pad and the outer circumferential lead portion and surrounding the die pad;
    A plurality of inner lead portions each supported by the connection ring and including a second terminal portion;
    The plurality of inner lead portions include a long inner lead portion and a short inner lead portion, and the long inner lead portion and the shorter inner lead portion are alternately arranged along the connection ring. And lead frame.
  2. 　前記複数の内側リード部は、前記接続リングの内側および外側の両方から延びていることを特徴とする請求項１記載のリードフレーム。 The lead frame according to claim 1, wherein the plurality of inner lead portions extend from both the inside and the outside of the connection ring.
  3. 　前記複数の内側リード部のうち、前記接続リングの内側から延びる前記短内側リード部と、前記接続リングの外側から延びる前記長内側リード部とが、前記接続リングを介して互いに反対側の位置に配置されていることを特徴とする請求項２記載のリードフレーム。 Among the plurality of inner lead portions, the short inner lead portion extending from the inner side of the connection ring and the long inner lead portion extending from the outer side of the connection ring are located at positions opposite to each other via the connection ring. The lead frame according to claim 2, wherein the lead frame is arranged.
  4. 　前記接続リングの表面に、前記接続リングに沿って凹溝が形成されていることを特徴とする請求項１記載のリードフレーム。 The lead frame according to claim 1, wherein a concave groove is formed on the surface of the connection ring along the connection ring.
  5. 　前記内側リード部は、前記接続リングに連結される接続リードを有し、前記接続リードは、裏面側から薄肉化されていることを特徴とする請求項１記載のリードフレーム。 The lead frame according to claim 1, wherein the inner lead portion has a connection lead coupled to the connection ring, and the connection lead is thinned from the back surface side.
  6. 　前記内側リード部は、前記接続リングに連結される接続リードを有し、前記接続リードは、表面側から薄肉化されていることを特徴とする請求項１記載のリードフレーム。 The lead frame according to claim 1, wherein the inner lead portion has a connection lead coupled to the connection ring, and the connection lead is thinned from the surface side.
  7. 　前記複数の外周リード部は、長外周リード部と、短外周リード部とを含み、前記長外周リード部と前記短外周リード部とが交互に配置され、
    　前記複数の内側リード部は、前記接続リングの少なくとも外側から延びており、
    　前記長外周リード部と前記短内側リード部とが互いに向かい合い、
    　前記短外周リード部と前記長内側リード部とが互いに向かい合うことを特徴とする請求項１記載のリードフレーム。     The plurality of outer peripheral lead portions include a long outer peripheral lead portion and a short outer peripheral lead portion, and the long outer peripheral lead portion and the short outer peripheral lead portion are alternately arranged,
    The plurality of inner lead portions extend from at least the outer side of the connection ring,
    The long outer periphery lead portion and the short inner lead portion face each other,
    The lead frame according to claim 1, wherein the short outer periphery lead portion and the long inner lead portion face each other.
  8. 　７５０Ｍｐａ～１１００Ｍｐａの引っ張り強度をもつ金属材料から構成されていることを特徴とする請求項１記載のリードフレーム。 2. The lead frame according to claim 1, wherein the lead frame is made of a metal material having a tensile strength of 750 Mpa to 1100 Mpa.
  9. 　半導体装置用のリードフレームであって、
    　半導体素子が搭載されるダイパッドと、
    　前記ダイパッド周囲に設けられ、それぞれ第１端子部を含む複数の外周リード部と、
    　前記ダイパッドと前記外周リード部との間に配置されたリード接続部と、
    　前記リード接続部によって支持され、それぞれ第２端子部を含む複数の内側リード部とを備え、
    　前記複数の内側リード部は、長内側リード部と、短内側リード部とを含み、前記長内側リード部と前記短内側リード部とが前記リード接続部に沿って交互に配置されていることを特徴とするリードフレーム。     A lead frame for a semiconductor device,
    A die pad on which a semiconductor element is mounted;
    A plurality of outer peripheral lead portions provided around the die pad, each including a first terminal portion;
    A lead connection portion disposed between the die pad and the outer peripheral lead portion;
    A plurality of inner lead portions each supported by the lead connection portion and including a second terminal portion;
    The plurality of inner lead portions include a long inner lead portion and a short inner lead portion, and the long inner lead portion and the shorter inner lead portion are alternately arranged along the lead connecting portion. A featured lead frame.
  10. 　半導体装置であって、
    　ダイパッドと、
    　前記ダイパッド周囲に設けられ、それぞれ第１端子部を含む複数の外周リード部と、
    　前記ダイパッドと前記外周リード部との間に配置され、前記ダイパッドおよび前記外周リード部から分離された複数の第２端子部と、
    　前記ダイパッド上に搭載された半導体素子と、
    　前記半導体素子と各外周リード部とを電気的に接続するとともに、前記半導体素子と各第２端子部とを電気的に接続する接続部材と、
    　前記ダイパッドと、前記複数の外周リード部と、前記複数の第２端子部と、前記半導体素子と、前記接続部材とを封止する封止樹脂とを備え、
    　前記複数の外周リード部は、前記第１端子部が相対的に内側に位置する長外周リード部と、前記第１端子部が相対的に外側に位置する短外周リード部とを含み、前記長外周リード部と前記短外周リード部とが交互に配置され、
    　前記封止樹脂の裏面のうち、前記外周リード部と前記ダイパッドとの間の領域に、前記ダイパッドを取り囲むように凹部が形成されていることを特徴とする半導体装置。     A semiconductor device,
    Die pad,
    A plurality of outer peripheral lead portions provided around the die pad, each including a first terminal portion;
    A plurality of second terminal portions disposed between the die pad and the outer peripheral lead portion and separated from the die pad and the outer peripheral lead portion;
    A semiconductor element mounted on the die pad;
    A connection member for electrically connecting the semiconductor element and each outer peripheral lead portion, and for electrically connecting the semiconductor element and each second terminal portion,
    A sealing resin that seals the die pad, the plurality of outer peripheral lead portions, the plurality of second terminal portions, the semiconductor element, and the connection member;
    The plurality of outer peripheral lead portions include a long outer peripheral lead portion in which the first terminal portion is positioned relatively inside, and a short outer peripheral lead portion in which the first terminal portion is positioned relatively outward. The outer peripheral lead portions and the short outer peripheral lead portions are alternately arranged,
    A semiconductor device, wherein a recess is formed in a region between the outer peripheral lead portion and the die pad on the back surface of the sealing resin so as to surround the die pad.
  11. 　半導体装置であって、
    　ダイパッドと、
    　前記ダイパッド周囲に設けられ、それぞれ第１端子部を含む複数の外周リード部と、
    　前記ダイパッドと前記外周リード部との間に配置され、前記ダイパッドおよび前記外周リード部から分離された複数の第２端子部と、
    　前記ダイパッド上に搭載された半導体素子と、
    　前記半導体素子と各外周リード部とを電気的に接続するとともに、前記半導体素子と各第２端子部とを電気的に接続する接続部材と、
    　前記ダイパッドと、前記複数の外周リード部と、前記複数の第２端子部と、前記半導体素子と、前記接続部材とを封止する封止樹脂とを備え、
    　前記複数の外周リード部は、前記第１端子部が相対的に内側に位置する長外周リード部と、前記第１端子部が相対的に外側に位置する短外周リード部とを含み、前記長外周リード部と前記短外周リード部とが交互に配置され、
    　前記封止樹脂の裏面のうち、前記外周リード部と前記ダイパッドとの間の領域に凹部が形成されていることを特徴とする半導体装置。     A semiconductor device,
    Die pad,
    A plurality of outer peripheral lead portions provided around the die pad, each including a first terminal portion;
    A plurality of second terminal portions disposed between the die pad and the outer peripheral lead portion and separated from the die pad and the outer peripheral lead portion;
    A semiconductor element mounted on the die pad;
    A connection member for electrically connecting the semiconductor element and each outer peripheral lead portion, and for electrically connecting the semiconductor element and each second terminal portion,
    A sealing resin that seals the die pad, the plurality of outer peripheral lead portions, the plurality of second terminal portions, the semiconductor element, and the connection member;
    The plurality of outer peripheral lead portions include a long outer peripheral lead portion in which the first terminal portion is positioned relatively inside, and a short outer peripheral lead portion in which the first terminal portion is positioned relatively outward. The outer peripheral lead portions and the short outer peripheral lead portions are alternately arranged,
    A semiconductor device, wherein a recess is formed in a region between the outer peripheral lead portion and the die pad on the back surface of the sealing resin.
  12. 　請求項１記載のリードフレームの製造方法において、
    　金属基板を準備する工程と、
    　前記金属基板をエッチング加工することにより、前記金属基板に前記ダイパッド、前記外周リード部、前記接続リングおよび前記内側リード部を形成する工程とを備えたことを特徴とするリードフレームの製造方法。     In the manufacturing method of the lead frame according to claim 1,
    Preparing a metal substrate;
    And a step of forming the die pad, the outer peripheral lead portion, the connection ring and the inner lead portion on the metal substrate by etching the metal substrate.
  13. 　半導体装置の製造方法において、
    　請求項１記載のリードフレームを準備する工程と、
    　前記リードフレームの前記ダイパッド上に前記半導体素子を搭載する工程と、
    　前記半導体素子と各外周リード部とを接続部材により電気的に接続する工程と、
    　前記ダイパッドと、前記複数の外周リード部と、前記半導体素子と、前記接続部材とを封止樹脂により封止する工程と、
    　前記リードフレームの裏面側から前記接続リングの少なくとも一部を除去することにより、前記複数の第２端子部をそれぞれ個別に分離する工程とを備えたことを特徴とする半導体装置の製造方法。     In a method for manufacturing a semiconductor device,
    Preparing a lead frame according to claim 1;
    Mounting the semiconductor element on the die pad of the lead frame;
    Electrically connecting the semiconductor element and each outer lead portion by a connecting member;
    Sealing the die pad, the plurality of outer peripheral lead portions, the semiconductor element, and the connection member with a sealing resin;
    And a step of individually separating the plurality of second terminal portions by removing at least a part of the connection ring from the back surface side of the lead frame.
  14. 　請求項９記載のリードフレームの製造方法において、
    　金属基板を準備する工程と、
    　前記金属基板をエッチング加工することにより、前記金属基板に前記ダイパッド、前記外周リード部、前記リード接続部および前記内側リード部を形成する工程とを備えたことを特徴とするリードフレームの製造方法。     The lead frame manufacturing method according to claim 9, wherein
    Preparing a metal substrate;
    And a step of forming the die pad, the outer peripheral lead portion, the lead connecting portion and the inner lead portion on the metal substrate by etching the metal substrate.
  15. 　半導体装置の製造方法において、
    　請求項９記載のリードフレームを準備する工程と、
    　前記リードフレームの前記ダイパッド上に前記半導体素子を搭載する工程と、
    　前記半導体素子と各外周リード部とを接続部材により電気的に接続する工程と、
    　前記ダイパッドと、前記複数の外周リード部と、前記半導体素子と、前記接続部材とを封止樹脂により封止する工程と、
    　前記リードフレームの裏面側から前記リード接続部の少なくとも一部を除去することにより、前記複数の第２端子部をそれぞれ個別に分離する工程とを備えたことを特徴とする半導体装置の製造方法。     In a method for manufacturing a semiconductor device,
    Preparing a lead frame according to claim 9;
    Mounting the semiconductor element on the die pad of the lead frame;
    Electrically connecting the semiconductor element and each outer lead portion by a connecting member;
    Sealing the die pad, the plurality of outer peripheral lead portions, the semiconductor element, and the connection member with a sealing resin;
    And a step of individually separating the plurality of second terminal portions by removing at least a part of the lead connection portion from the back surface side of the lead frame.
  16. 　互いに支持部材を介して連結された複数の単位リードフレームを含むリードフレームであって、
    　各単位リードフレームは、
    　半導体素子が搭載されるダイパッドと、
    　前記ダイパッド周囲に設けられ、それぞれ端子部と前記端子部から内側に延びるインナーリードとを含む複数のリード部とを備え、
    　前記リード部は、隣り合う前記単位リードフレーム間に設けられた前記支持部材によって支持され、
    　前記リードフレームは、８５０ＭＰａ～１１００ＭＰａの引張強度をもつ金属材料から構成され、
    　各単位リードフレームの前記リード部のうち、前記支持部材の近傍部分は、幅が７５μｍ～９０μｍであり、厚みが６０μｍ～７５μｍであることを特徴とするリードフレーム。     A lead frame including a plurality of unit lead frames connected to each other via a support member,
    Each unit lead frame is
    A die pad on which a semiconductor element is mounted;
    A plurality of lead portions provided around the die pad, each including a terminal portion and an inner lead extending inward from the terminal portion;
    The lead portion is supported by the support member provided between the adjacent unit lead frames,
    The lead frame is made of a metal material having a tensile strength of 850 MPa to 1100 MPa,
    A lead frame characterized in that, in the lead portion of each unit lead frame, a portion near the support member has a width of 75 μm to 90 μm and a thickness of 60 μm to 75 μm.
  17. 　前記複数のリード部の前記端子部は、隣り合う前記リード部間で内側および外側に位置するよう平面から見て交互に千鳥状に配置されていることを特徴とする請求項１６記載のリードフレーム。 17. The lead frame according to claim 16, wherein the terminal portions of the plurality of lead portions are alternately arranged in a staggered manner as viewed from above so as to be located inside and outside between the adjacent lead portions. .
  18. 　前記インナーリードは前記端子部よりも厚さが薄いことを特徴とする請求項１６記載のリードフレーム。 The lead frame according to claim 16, wherein the inner lead is thinner than the terminal portion.
  19. 　前記リード部は、前記端子部から外側に延びる接続リードを含み、前記接続リードは前記端子部よりも厚さが薄いことを特徴とする請求項１６記載のリードフレーム。 The lead frame according to claim 16, wherein the lead portion includes a connection lead extending outward from the terminal portion, and the connection lead is thinner than the terminal portion.
  20. 　前記リード部の前記インナーリードのうち、前記端子部の近傍部分は、幅が７５μｍ～９０μｍであり、厚みが６０μｍ～７５μｍであることを特徴とする請求項１６記載のリードフレーム。 17. The lead frame according to claim 16, wherein, of the inner leads of the lead portion, a portion in the vicinity of the terminal portion has a width of 75 μm to 90 μm and a thickness of 60 μm to 75 μm.
  21. 　前記金属材料は、コルソン系合金（Ｃｕ－Ｎｉ－Ｓｉ）、ニッケル錫銅合金（Ｃｕ－Ｎｉ－Ｓｎ）、又はチタニウム銅合金（Ｃｕ－Ｔｉ）であることを特徴とする請求項１６記載のリードフレーム。 The lead according to claim 16, wherein the metal material is a Corson alloy (Cu-Ni-Si), a nickel tin copper alloy (Cu-Ni-Sn), or a titanium copper alloy (Cu-Ti). flame.
  22. 　互いに支持部材を介して連結された複数の単位リードフレームを含むリードフレームであって、
    　各単位リードフレームは、
    　半導体素子が搭載されるダイパッドと、
    　前記ダイパッド周囲に設けられ、それぞれ端子部と前記端子部から内側に延びるインナーリードとを含む複数のリード部とを備え、
    　前記リード部は、隣り合う前記単位リードフレーム間に設けられた前記支持部材によって支持され、
    　前記リードフレームは、７５０ＭＰａ～１１００ＭＰａの引張強度をもつ金属材料から構成され、
    　各単位リードフレームの前記リード部のうち、前記支持部材の近傍部分は、幅が６０μｍ～９０μｍであり、厚みが５０μｍ～７５μｍであることを特徴とするリードフレーム。     A lead frame including a plurality of unit lead frames connected to each other via a support member,
    Each unit lead frame is
    A die pad on which a semiconductor element is mounted;
    A plurality of lead portions provided around the die pad, each including a terminal portion and an inner lead extending inward from the terminal portion;
    The lead portion is supported by the support member provided between the adjacent unit lead frames,
    The lead frame is made of a metal material having a tensile strength of 750 MPa to 1100 MPa,
    2. A lead frame according to claim 1, wherein, of the lead portions of each unit lead frame, a portion near the support member has a width of 60 μm to 90 μm and a thickness of 50 μm to 75 μm.
  23. 　請求項１６記載のリードフレームを用いて作製された半導体装置であって、
    　前記ダイパッドと、
    　前記ダイパッド周囲に設けられ、それぞれ前記端子部と前記端子部から内側に延びる前記インナーリードとを含む複数の前記リード部と、
    　前記ダイパッド上に搭載された半導体素子と、
    　前記半導体素子と各リード部の前記インナーリードとを電気的に接続する接続部材と、
    　前記ダイパッドと、前記複数のリード部と、前記半導体素子と、前記接続部材とを封止する封止樹脂とを備えたことを特徴とする半導体装置。     A semiconductor device manufactured using the lead frame according to claim 16,
    The die pad;
    A plurality of the lead portions provided around the die pad, each including the terminal portion and the inner lead extending inward from the terminal portion;
    A semiconductor element mounted on the die pad;
    A connection member for electrically connecting the semiconductor element and the inner lead of each lead portion;
    A semiconductor device, comprising: a sealing resin that seals the die pad, the plurality of lead portions, the semiconductor element, and the connection member.
  24. 　互いに支持部材を介して連結された複数の単位リードフレームを含み、各単位リードフレームは、半導体素子が搭載されるダイパッドと、前記ダイパッド周囲に設けられ、それぞれ端子部と前記端子部から内側に延びるインナーリードとを含む複数のリード部とを備えた、リードフレームの製造方法において、
    　８５０ＭＰａ～１１００ＭＰａの引張強度をもつ金属材料から構成される金属基板を準備する工程と、
    　前記金属基板をエッチング加工することにより、前記金属基板に前記ダイパッドおよび前記リード部を形成する工程とを備え、
    　前記金属基板に前記ダイパッドおよび前記リード部を形成する際、各単位リードフレームの前記リード部のうち、前記支持部材の近傍部分は、幅が７５μｍ～９０μｍとなり、厚みが６０μｍ～７５μｍとなることを特徴とするリードフレームの製造方法。     Each unit lead frame includes a die pad on which a semiconductor element is mounted and a periphery of the die pad, and extends inward from the terminal portion and the terminal portion, respectively. In a lead frame manufacturing method comprising a plurality of lead portions including an inner lead,
    Preparing a metal substrate composed of a metal material having a tensile strength of 850 MPa to 1100 MPa;
    Forming the die pad and the lead portion on the metal substrate by etching the metal substrate; and
    When the die pad and the lead portion are formed on the metal substrate, a portion of the lead portion of each unit lead frame in the vicinity of the support member has a width of 75 μm to 90 μm and a thickness of 60 μm to 75 μm. A method for manufacturing a lead frame.
  25. 　互いに支持部材を介して連結された複数の単位リードフレームを含み、各単位リードフレームは、半導体素子が搭載されるダイパッドと、前記ダイパッド周囲に設けられ、それぞれ端子部と前記端子部から内側に延びるインナーリードとを含む複数のリード部とを備えた、リードフレームの製造方法において、
    　７５０ＭＰａ～１１００ＭＰａの引張強度をもつ金属材料から構成される金属基板を準備する工程と、
    　前記金属基板をエッチング加工することにより、前記金属基板に前記ダイパッドおよび前記リード部を形成する工程とを備え、
    　前記金属基板に前記ダイパッドおよび前記リード部を形成する際、各単位リードフレームの前記リード部のうち、前記支持部材の近傍部分は、幅が６０μｍ～９０μｍとなり、厚みが５０μｍ～７５μｍとなることを特徴とするリードフレームの製造方法。     Each unit lead frame includes a die pad on which a semiconductor element is mounted and a periphery of the die pad, and extends inward from the terminal portion and the terminal portion, respectively. In a lead frame manufacturing method comprising a plurality of lead portions including an inner lead,
    Preparing a metal substrate composed of a metal material having a tensile strength of 750 MPa to 1100 MPa;
    Forming the die pad and the lead portion on the metal substrate by etching the metal substrate; and
    When the die pad and the lead portion are formed on the metal substrate, a portion of the lead portion of each unit lead frame in the vicinity of the support member has a width of 60 μm to 90 μm and a thickness of 50 μm to 75 μm. A method for manufacturing a lead frame.
  26. 　半導体装置の製造方法において、
    　請求項２４記載のリードフレームの製造方法によりリードフレームを製造する工程と、
    　前記リードフレームの前記ダイパッド上に前記半導体素子を搭載する工程と、
    　前記半導体素子と各リード部の前記インナーリードとを接続部材により電気的に接続する工程と、
    　前記ダイパッドと、前記複数のリード部と、前記半導体素子と、前記接続部材とを封止樹脂により封止する工程とを備えたことを特徴とする半導体装置の製造方法。     In a method for manufacturing a semiconductor device,
    Producing a lead frame by the method for producing a lead frame according to claim 24;
    Mounting the semiconductor element on the die pad of the lead frame;
    Electrically connecting the semiconductor element and the inner lead of each lead portion by a connecting member;
    A method of manufacturing a semiconductor device, comprising: sealing the die pad, the plurality of lead portions, the semiconductor element, and the connection member with a sealing resin.
  27. 　半導体装置用のリードフレームであって、
    　半導体素子が搭載されるダイパッドと、
    　前記ダイパッド周囲に設けられ、それぞれ第１端子部と前記第１端子部から内側に延びるインナーリードとを含む複数のリード部と、
    　前記インナーリードの先端側に設けられ、前記ダイパッドを取り囲む接続リングとを備え、
    　前記接続リングは、少なくとも１つの前記インナーリードによって支持され、
    　前記接続リングに沿って凹部が規則的に設けられ、各凹部の間には厚肉部が形成されていることを特徴とするリードフレーム。     A lead frame for a semiconductor device,
    A die pad on which a semiconductor element is mounted;
    A plurality of lead portions provided around the die pad, each including a first terminal portion and an inner lead extending inward from the first terminal portion;
    A connection ring provided on the tip side of the inner lead and surrounding the die pad;
    The connection ring is supported by at least one of the inner leads;
    A lead frame, wherein concave portions are regularly provided along the connection ring, and a thick portion is formed between the concave portions.
PCT/JP2015/051545 2014-01-22 2015-01-21 Lead frame and method for manufacturing same, semiconductor device and method for manufacturing same WO2015111623A1 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP2014-009332 2014-01-22
JP2014009332 2014-01-22
JP2014031975 2014-02-21
JP2014-031975 2014-02-21
JP2014158121 2014-08-01
JP2014-158121 2014-08-01

Publications (1)

Publication Number Publication Date
WO2015111623A1 true WO2015111623A1 (en) 2015-07-30

Family

ID=53681424

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2015/051545 WO2015111623A1 (en) 2014-01-22 2015-01-21 Lead frame and method for manufacturing same, semiconductor device and method for manufacturing same

Country Status (2)

Country Link
TW (3) TWI662673B (en)
WO (1) WO2015111623A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10177081B2 (en) * 2017-01-13 2019-01-08 Littlefuse, Inc. Thyristor and thermal switch device and assembly techniques therefor

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07169895A (en) * 1993-09-20 1995-07-04 Sumitomo Electric Ind Ltd Lead frame and manufacture of the same
JP2000307045A (en) * 1999-04-23 2000-11-02 Matsushita Electronics Industry Corp Lead frame and manufacture of resin sealed semiconductor device using it
JP2002261193A (en) * 2001-03-06 2002-09-13 Hitachi Ltd Method for manufacturing semiconductor device
JP2003017645A (en) * 2001-07-03 2003-01-17 Shinko Electric Ind Co Ltd Lead frame and method of fabricating the same
JP2003204024A (en) * 2002-01-08 2003-07-18 Toppan Printing Co Ltd Method for producing lead frame
JP2003243600A (en) * 2001-12-14 2003-08-29 Hitachi Ltd Semiconductor device and method of manufacturing the same
US20090072364A1 (en) * 2007-09-13 2009-03-19 Punzalan Jeffrey D Integrated circuit package system with leads separated from a die paddle
US20090294935A1 (en) * 2008-05-30 2009-12-03 Lionel Chien Hui Tay Semiconductor package system with cut multiple lead pads
JP2010126777A (en) * 2008-11-28 2010-06-10 Dowa Metaltech Kk Copper alloy sheet, and method for producing the same
US8072050B1 (en) * 2008-11-18 2011-12-06 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including passive device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8404524B2 (en) * 2010-09-16 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system with paddle molding and method of manufacture thereof

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07169895A (en) * 1993-09-20 1995-07-04 Sumitomo Electric Ind Ltd Lead frame and manufacture of the same
JP2000307045A (en) * 1999-04-23 2000-11-02 Matsushita Electronics Industry Corp Lead frame and manufacture of resin sealed semiconductor device using it
JP2002261193A (en) * 2001-03-06 2002-09-13 Hitachi Ltd Method for manufacturing semiconductor device
JP2003017645A (en) * 2001-07-03 2003-01-17 Shinko Electric Ind Co Ltd Lead frame and method of fabricating the same
JP2003243600A (en) * 2001-12-14 2003-08-29 Hitachi Ltd Semiconductor device and method of manufacturing the same
JP2003204024A (en) * 2002-01-08 2003-07-18 Toppan Printing Co Ltd Method for producing lead frame
US20090072364A1 (en) * 2007-09-13 2009-03-19 Punzalan Jeffrey D Integrated circuit package system with leads separated from a die paddle
US20090294935A1 (en) * 2008-05-30 2009-12-03 Lionel Chien Hui Tay Semiconductor package system with cut multiple lead pads
US8072050B1 (en) * 2008-11-18 2011-12-06 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including passive device
JP2010126777A (en) * 2008-11-28 2010-06-10 Dowa Metaltech Kk Copper alloy sheet, and method for producing the same

Also Published As

Publication number Publication date
TWI712137B (en) 2020-12-01
TWI719905B (en) 2021-02-21
TW201929173A (en) 2019-07-16
TWI662673B (en) 2019-06-11
TW201535648A (en) 2015-09-16
TW202038408A (en) 2020-10-16

Similar Documents

Publication Publication Date Title
TWI587457B (en) Resin-encapsulated semiconductor device and method of manufacturing the same
JP2005057067A (en) Semiconductor device and manufacturing method thereof
JP6205816B2 (en) Lead frame and manufacturing method thereof, and semiconductor device and manufacturing method thereof
JP5278037B2 (en) Resin-sealed semiconductor device
JP6936963B2 (en) Lead frame
JP7174363B2 (en) Lead frames and semiconductor equipment
JP6379448B2 (en) Lead frame and manufacturing method thereof, and semiconductor device and manufacturing method thereof
JP6573157B2 (en) Lead frame and manufacturing method thereof, and semiconductor device and manufacturing method thereof
JP6607429B2 (en) Lead frame and manufacturing method thereof, and semiconductor device and manufacturing method thereof
WO2015111623A1 (en) Lead frame and method for manufacturing same, semiconductor device and method for manufacturing same
JP6465394B2 (en) Lead frame and manufacturing method thereof, and semiconductor device and manufacturing method thereof
JP6274553B2 (en) Lead frame and manufacturing method thereof, and semiconductor device and manufacturing method thereof
JP6807050B2 (en) Lead frames and semiconductor devices
JP6436202B2 (en) Lead frame and manufacturing method thereof, and semiconductor device and manufacturing method thereof
JP7081702B2 (en) Lead frames and semiconductor devices
JP7064721B2 (en) Lead frames and semiconductor devices
JP6807043B2 (en) Lead frames and semiconductor devices
JP6967190B2 (en) Lead frame
JP7073637B2 (en) Lead frames and semiconductor devices
JP2015154042A (en) Lead frame and manufacturing method therefor, and semiconductor device and manufacturing method therefor
JP6842649B2 (en) Lead frames and semiconductor devices
JP6788825B2 (en) Lead frames and semiconductor devices
JP6428013B2 (en) Lead frame member and manufacturing method thereof, and semiconductor device and manufacturing method thereof
JP5910950B2 (en) Resin-sealed semiconductor device, multi-surface resin-sealed semiconductor device, lead frame, and method for manufacturing resin-sealed semiconductor device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15740279

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15740279

Country of ref document: EP

Kind code of ref document: A1