WO2015096098A1 - Electronic board with anti-cracking performance - Google Patents

Electronic board with anti-cracking performance Download PDF

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Publication number
WO2015096098A1
WO2015096098A1 PCT/CN2013/090577 CN2013090577W WO2015096098A1 WO 2015096098 A1 WO2015096098 A1 WO 2015096098A1 CN 2013090577 W CN2013090577 W CN 2013090577W WO 2015096098 A1 WO2015096098 A1 WO 2015096098A1
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WO
WIPO (PCT)
Prior art keywords
lines
electronic board
cpu
substrate
vias
Prior art date
Application number
PCT/CN2013/090577
Other languages
French (fr)
Inventor
Guangzhi SHI
Hui Yang
Original Assignee
Thomson Licensing
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing filed Critical Thomson Licensing
Priority to PCT/CN2013/090577 priority Critical patent/WO2015096098A1/en
Publication of WO2015096098A1 publication Critical patent/WO2015096098A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0275—Security details, e.g. tampering prevention or detection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114—Pad being close to via, but not surrounding the via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09709—Staggered pads, lands or terminals; Parallel conductors in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10545—Related components mounted on both sides of the PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Definitions

  • the present inventions relate generally to an electronic board and, more particularly, a printed circuit board with anti-cracking performance. [BACKGROUND ART] [0002]
  • Conditional Accessing technology is widely used in content receivers such us set top boxes for cable TV and TV receivers as a main security and anti-cracking method.
  • providers for the set top boxes such as IC providers, hardware providers, software providers, and system providers.
  • the various requirements for hardware design are also imposed and thus it results in increasing difficulty of probing signals through lines in a printed circuit board (PCB) and decreasing possibility of cracking a system.
  • PCB printed circuit board
  • An object of the present inventions is to provide a useful electronic board with anti-cracking performance.
  • an electronic board including: a substrate; a CPU on a first side of the substrate; a memory chip on a second side of the other side of the first side of the substrate; and signal lines for connecting the CPU and the memory chip, wherein the signal lines are located in the region held between a package of the CPU and a package of the memory chip.
  • the signal lines for coupling the CPU and the memory chip are covered with the packages of the CPU and the memory chip, and thus the probing the signal lines may become more difficult and the anti-cracking performance may be improved.
  • FIG. 1 is an electronic board according to a first embodiment of the present invention
  • FIG. 2 is an exemplary variation of a line pattern of the electronic board according to the first embodiment of the present invention
  • FIG. 3 is an electronic board according to a second embodiment of the present invention.
  • FIG. 1 is an electronic board according to a first embodiment of the present invention.
  • FIG. 1 (a) is a cross sectional view of the electronic board.
  • FIG. 1 (b) is a plane view of the electronic board viewed from the CPU and describes a line pattern on the substrate and connections between the CPU and lines.
  • a substrate 110 for a CPU 120 on a surface 110a of a one side of the substrate 110, and a memory chip 130 on a surface 110b of the other side of the substrate 110.
  • the substrate 110 is provided with lines 112 (hereinafter, called the "first lines
  • the substrate 110 may be provided with more substrate layers and one or more line layers between adjacent substrate layers.
  • the CPU 120 is provided with circuits (not shown), a package 122, and terminals 124.
  • the terminals 124 are formed inside of outer edges of the package 122.
  • the terminals 124 of the CPU 120 are soldered to the first lines 112.
  • One end 112a of the first line 112 is connected to the terminal 124 of the CPU
  • the first line 112 is located in the region held between the surface 110a of the substrate 110 and the package 124 of the CPU 120. Thus, since all the terminals 124 and the first lines 112 are covered with the package 122 of the CPU 120, it may be difficult to probe the elements 124 and the first lines 112.
  • the memory chip 130 is provided with circuits (not shown), a package 132, and terminals 134.
  • the terminals 134 are formed inside of outer edges of the package 132.
  • the terminals 134 are soldered to the second lines 114.
  • the memory chip 130 may store a program for booting a system of an apparatus in which the electronic board 100 is implemented.
  • the memory chip 130 may transmit the program to the CPU 120 to boot the system.
  • One end of the second line 114 is connected to the terminal 134 of the memory chip 130 and the other end of the second line 114 is connected to the through- via 116.
  • the second line 114 is located in the region held between the surface 110b of the substrate 110 and the package 134 of the memory chip 130. Thus, since all the terminals 134 and the second lines 114 are covered with the package 132 of the memory chip 130, it may be difficult to probe the elements 134 and the second lines 114.
  • the first line 112 and the second lines 114 are connected via the through- vias 116 through the substrate 110.
  • the through- vias 116 are located in the region held between the package 122 of the CPU 120 and the package 132 of the memory chip 130. In FIG. 1 (a), the region is enclosed by the package 122 of the CPU 120, the package 132 of the memory chip 130, and the dotted lines connecting the outer edges of these packages 122, 132. Thus, it is difficult to probe the through-vias.
  • the signal lines connecting CPU 120 and the memory chip 130 include the first lines 112, the through-vias 116, and the second lines 114. These signal lines are located in the region held between the package 122 of the CPU 120 and the package 132 of the memory chip 130.
  • the electronic board 100 may have advantageous anti-cracking performance.
  • the electronic board 100 may be realized with advantageous anti-cracking performance and lower production cost.
  • only lines requiring anti-probing may be located in the region held with the package 122 of the CPU 120 and the package 132 of the memory chip 130. This may make the design of line patterns of the first and second lines 112 and 114 more flexible.
  • the invention of the first embodiments may apply to only the 4 signal lines for "Chip Select (CS)", “Master-Output, Slave-Input (MOSI)", “Master-Input, Slave-Output (MISO)", and “Clock (CLK)". That is, the signal lines for the 4 signals are located in the region held between the package 122 of the CPU 120 and the package 132 of the memory chip 130. This may make the probing of the signal lines for the 4 signals more difficult and may improve anti-cracking performance.
  • CS Chip Select
  • MOSI Master-Output
  • MISO Master-Input, Slave-Output
  • CLK Lock
  • FIG. 2 is an exemplary variation of a line pattern of the electronic board according to the first embodiment of the present invention.
  • FIG. 2 (a) and (b) are plane views of the electronic board viewed from the CPU and describes line patterns.
  • the elements in FIG. 2 which have the same reference indexes as the elements in FIG. 1, have the functions described above in FIG. 1 and the descriptions for such elements are not shown here.
  • the cross view of the electronic boards 200, 250 in FIG. 2 (a) and (b) is same as FIG. 1 (a).
  • an electronic board 200 of the exemplary variation is provided with first lines 212 on the surface 110a of the substrate 110.
  • One end 212a of the first line 212 is connected to the terminal 124 of the CPU 120 and the other end 212b of the first line 212 is connected to the though-via 116.
  • the first line 212 is extended more than one in FIG. 1 (b) and thus the terminal 124 of the CPU 120 and the through- via 116 may be connected by the first line 212 even if these are separated each other.
  • the first line 212 is located in the region held between the outer edges of the package 122 of the CPU and the surface 110b.
  • a line pattern of the second lines (not shown in FIG. 2 (a)) on the surface 110b at the side of the memory chip 130 may be same as the line pattern described in FIG. 2 (a) or FIG. 1 (a).
  • the electronic board 200 of the exemplary variation may connect the both terminals by the first lines 212 and the second lines via the through- vias 116.
  • the electronic board 200 may have advantageous anti-cracking performance.
  • the electronic board 200 of the exemplary variation may be adopted when the fan-outs of the CPU 120 and the memory chip 130 are different each other.
  • an electronic board 250 of another exemplary variation is provided with first lines 262 on the surface 110a of the substrate 110.
  • One end 262a of the first line 262 is connected to the terminal 124 of the CPU 120 and the other end 262b of the first line 262 is connected to the though-via 116.
  • the first lines 262 extend from the ends 262a to the other end 262b which is the inside of the package 124 of the CPU 120. Thus, the probing the first lines 262 becomes more difficult than the first lines 112 in FIG. 1 (a). Accordingly, the electronic board 250 may have advantageous anti-cracking performance.
  • a line pattern of the second lines (not shown in FIG. 2 (b)) on surface 110b at the side of the memory chip 130 may be same as the line pattern described in FIG. 2 (b), FIG. 2 (a) or FIG. 1 (a).
  • FIG. 3 is an electronic board according to a second embodiment of the present invention.
  • FIG. 3 is a cross sectional view of the electronic board.
  • the elements in FIG. 3 which have the same reference indexes as the elements in FIG. 1, have the functions described above in FIG. 1 and the descriptions for such elements are not shown here.
  • an electronic board 300 of the second embodiment is provided with a substrate 310, the CPU 120 on a surface 310a of a one side of the substrate 310, and the memory chip 130 on a surface 310b of the other side of the substrate 310.
  • the substrate 310 is provided with a first substrate layer 311, a second substrate layer, the first lines 112 on a surface 310a, the second lines 114 on a surface 310b, and third lines 315 between the first substrate layer 311 and the second substrate layer 313.
  • the substrate 310 is also provided with first vias 316 through the first substrate layer 311 and second vias 318 through the second substrate layer 313.
  • the substrate 310 may be provided with more substrate layers and one or more line layers between adjacent substrate layers.
  • the third lines 315 connect the first vias 316 and the second vias 318.
  • the third lines 315, the first vias 316, and the second vias 318 are located in the region held between the package 122 of the CPU 120 and the package 132 of the memory chip 130.
  • a line pattern of the first and second lines 112, 114 may be same as the line pattern described in FIG. 1 (a), FIG. 2 (a), or FIG. 2 (b).
  • the electronic board 300 since the electronic board 300 is provided with the third lines 315, the locations of the first vias 316 and the second vias may be selected more flexibly. This may make the design of line patterns of the first and second lines 112 and 114 more flexible.
  • the electronic board 300 has the same effects as those of the electronic boards 100, 200, 250 of the first embodiment and the exemplary variations as described above.

Abstract

There is provided an electronic board 100 with anti-cracking performance. The electronic board includes a substrate 110, a CPU 120 on a first side of the substrate, a memory chip 130 on a second side of the other side of the first side of the substrate, and signal lines 112, 114, 116 for connecting the CPU and the memory chip. The signal lines are located in the region held between a package of the CPU and a package of the memory chip.

Description

ELECTRONIC BOARD WITH ANTI-CRACKING PERFORMANCE
[TECHNICAL FIELD] [0001]
The present inventions relate generally to an electronic board and, more particularly, a printed circuit board with anti-cracking performance. [BACKGROUND ART] [0002]
Conditional Accessing technology is widely used in content receivers such us set top boxes for cable TV and TV receivers as a main security and anti-cracking method. Various restrictions for the conditional access technology are imposed on providers for the set top boxes such as IC providers, hardware providers, software providers, and system providers. The various requirements for hardware design are also imposed and thus it results in increasing difficulty of probing signals through lines in a printed circuit board (PCB) and decreasing possibility of cracking a system. In the requirements for a layout of the PCB, it is desired that all data and address lines in addition to chip select (CS) and write enable (WE) lines for signals to boot a system are protected.
[0003]
However, in order to meet the requirements, it is required that all the lines should be covered with epoxy coating or should be protected in other ways by using additional materials and processes. It could be a problem that such materials or processes increase clearly production cost of the PCB.
[SUMMARY OF INVENTION]
[0004]
An object of the present inventions is to provide a useful electronic board with anti-cracking performance. [0005]
According to an aspect of the present invention, there is provided an electronic board including: a substrate; a CPU on a first side of the substrate; a memory chip on a second side of the other side of the first side of the substrate; and signal lines for connecting the CPU and the memory chip, wherein the signal lines are located in the region held between a package of the CPU and a package of the memory chip.
[0006]
According to the present invention, the signal lines for coupling the CPU and the memory chip are covered with the packages of the CPU and the memory chip, and thus the probing the signal lines may become more difficult and the anti-cracking performance may be improved.
[BRIEF DESCRIPTION OF DRAWINGS]
[0007]
These and other aspects, features and advantages of the present invention will become apparent from the following description in connection with the accompanying drawings in which:
FIG. 1 is an electronic board according to a first embodiment of the present invention;
FIG. 2 is an exemplary variation of a line pattern of the electronic board according to the first embodiment of the present invention;
FIG. 3 is an electronic board according to a second embodiment of the present invention.
[DETAILED DESCRIPTION OF THE INVENTION] [0008]
Hereinafter, embodiments of the present invention will be described referring to the drawings.
[0009]
FIG. 1 is an electronic board according to a first embodiment of the present invention. FIG. 1 (a) is a cross sectional view of the electronic board. FIG. 1 (b) is a plane view of the electronic board viewed from the CPU and describes a line pattern on the substrate and connections between the CPU and lines.
[0010]
Referring to FIG. 1 (a) and (b), an electronic board 100 of the first
embodiment is provided with a substrate 110, a CPU 120 on a surface 110a of a one side of the substrate 110, and a memory chip 130 on a surface 110b of the other side of the substrate 110.
[0011]
The substrate 110 is provided with lines 112 (hereinafter, called the "first lines
112") on the surface 110a, lines 114 (hereinafter, called the "second lines 114"), and through- vias 116 connecting the first lines 112 and the second lines 114. The substrate 110 may be provided with more substrate layers and one or more line layers between adjacent substrate layers. [0012]
The CPU 120 is provided with circuits (not shown), a package 122, and terminals 124. The terminals 124 are formed inside of outer edges of the package 122. The terminals 124 of the CPU 120 are soldered to the first lines 112.
[0013]
One end 112a of the first line 112 is connected to the terminal 124 of the CPU
120 and the other end 112b of the first line 112 is connected to the though-via 116. The first line 112 is located in the region held between the surface 110a of the substrate 110 and the package 124 of the CPU 120. Thus, since all the terminals 124 and the first lines 112 are covered with the package 122 of the CPU 120, it may be difficult to probe the elements 124 and the first lines 112. [0014]
The memory chip 130 is provided with circuits (not shown), a package 132, and terminals 134. The terminals 134 are formed inside of outer edges of the package 132. The terminals 134 are soldered to the second lines 114. The memory chip 130 may store a program for booting a system of an apparatus in which the electronic board 100 is implemented. The memory chip 130 may transmit the program to the CPU 120 to boot the system.
[0015]
One end of the second line 114 is connected to the terminal 134 of the memory chip 130 and the other end of the second line 114 is connected to the through- via 116. The second line 114 is located in the region held between the surface 110b of the substrate 110 and the package 134 of the memory chip 130. Thus, since all the terminals 134 and the second lines 114 are covered with the package 132 of the memory chip 130, it may be difficult to probe the elements 134 and the second lines 114.
[0016]
The first line 112 and the second lines 114 are connected via the through- vias 116 through the substrate 110. The through- vias 116 are located in the region held between the package 122 of the CPU 120 and the package 132 of the memory chip 130. In FIG. 1 (a), the region is enclosed by the package 122 of the CPU 120, the package 132 of the memory chip 130, and the dotted lines connecting the outer edges of these packages 122, 132. Thus, it is difficult to probe the through-vias.
[0017]
In addition, it is described in FIG. 1 (a) and (b) that the sizes of the packages 122, 132 of the CPU 120 and the memory chip 130 are same. When the sizes of the packages 122, 132 are different, all of the terminals 124, 134, the first lines 112, the second lines 114, and the through-vias may be located in region of the smaller package among the packages 122, 132.
[0018]
As described above, the signal lines connecting CPU 120 and the memory chip 130 include the first lines 112, the through-vias 116, and the second lines 114. These signal lines are located in the region held between the package 122 of the CPU 120 and the package 132 of the memory chip 130.
[0019]
According to the first embodiment, since the lines between the CPU 120 and the memory chip 130 are located in the region held between the package 122 of the CPU 120 and the package 132 of the memory chip 130, it is difficult to probe the signals transmitted through the signal lines. Accordingly, the electronic board 100 may have advantageous anti-cracking performance. In addition, the electronic board 100 may be realized with advantageous anti-cracking performance and lower production cost.
[0020]
As a variant of the first embodiment, only lines requiring anti-probing may be located in the region held with the package 122 of the CPU 120 and the package 132 of the memory chip 130. This may make the design of line patterns of the first and second lines 112 and 114 more flexible.
[0021]
When the memory chip 130 is a serial NOR flash memory, the invention of the first embodiments may apply to only the 4 signal lines for "Chip Select (CS)", "Master-Output, Slave-Input (MOSI)", "Master-Input, Slave-Output (MISO)", and "Clock (CLK)". That is, the signal lines for the 4 signals are located in the region held between the package 122 of the CPU 120 and the package 132 of the memory chip 130. This may make the probing of the signal lines for the 4 signals more difficult and may improve anti-cracking performance.
[0022]
FIG. 2 is an exemplary variation of a line pattern of the electronic board according to the first embodiment of the present invention. FIG. 2 (a) and (b) are plane views of the electronic board viewed from the CPU and describes line patterns. The elements in FIG. 2 which have the same reference indexes as the elements in FIG. 1, have the functions described above in FIG. 1 and the descriptions for such elements are not shown here. The cross view of the electronic boards 200, 250 in FIG. 2 (a) and (b) is same as FIG. 1 (a).
[0023]
Referring to FIG. 2 (a), an electronic board 200 of the exemplary variation is provided with first lines 212 on the surface 110a of the substrate 110. One end 212a of the first line 212 is connected to the terminal 124 of the CPU 120 and the other end 212b of the first line 212 is connected to the though-via 116.
[0024]
The first line 212 is extended more than one in FIG. 1 (b) and thus the terminal 124 of the CPU 120 and the through- via 116 may be connected by the first line 212 even if these are separated each other. The first line 212 is located in the region held between the outer edges of the package 122 of the CPU and the surface 110b.
[0025]
In addition, a line pattern of the second lines (not shown in FIG. 2 (a)) on the surface 110b at the side of the memory chip 130 may be same as the line pattern described in FIG. 2 (a) or FIG. 1 (a). [0026]
Thus, even when there is no such relation that each of the terminals 124 of the CPU 120 faces each of the terminals 134 of the memory chip 130 to be coupled to the each of the terminals 124 of the CPU 120 such as the electronic board 100 described in FIG. 1, the electronic board 200 of the exemplary variation may connect the both terminals by the first lines 212 and the second lines via the through- vias 116.
Accordingly, the electronic board 200 may have advantageous anti-cracking performance. In addition, the electronic board 200 of the exemplary variation may be adopted when the fan-outs of the CPU 120 and the memory chip 130 are different each other.
[0027]
Referring to FIG. 2 (b), an electronic board 250 of another exemplary variation is provided with first lines 262 on the surface 110a of the substrate 110. One end 262a of the first line 262 is connected to the terminal 124 of the CPU 120 and the other end 262b of the first line 262 is connected to the though-via 116.
[0028]
The first lines 262 extend from the ends 262a to the other end 262b which is the inside of the package 124 of the CPU 120. Thus, the probing the first lines 262 becomes more difficult than the first lines 112 in FIG. 1 (a). Accordingly, the electronic board 250 may have advantageous anti-cracking performance.
[0029]
In addition, a line pattern of the second lines (not shown in FIG. 2 (b)) on surface 110b at the side of the memory chip 130 may be same as the line pattern described in FIG. 2 (b), FIG. 2 (a) or FIG. 1 (a). [0030]
FIG. 3 is an electronic board according to a second embodiment of the present invention. FIG. 3 is a cross sectional view of the electronic board. The elements in FIG. 3 which have the same reference indexes as the elements in FIG. 1, have the functions described above in FIG. 1 and the descriptions for such elements are not shown here.
[0031]
Referring to FIG. 3, an electronic board 300 of the second embodiment is provided with a substrate 310, the CPU 120 on a surface 310a of a one side of the substrate 310, and the memory chip 130 on a surface 310b of the other side of the substrate 310.
[0032]
The substrate 310 is provided with a first substrate layer 311, a second substrate layer, the first lines 112 on a surface 310a, the second lines 114 on a surface 310b, and third lines 315 between the first substrate layer 311 and the second substrate layer 313. The substrate 310 is also provided with first vias 316 through the first substrate layer 311 and second vias 318 through the second substrate layer 313. The substrate 310 may be provided with more substrate layers and one or more line layers between adjacent substrate layers. [0033]
The third lines 315 connect the first vias 316 and the second vias 318. The third lines 315, the first vias 316, and the second vias 318 are located in the region held between the package 122 of the CPU 120 and the package 132 of the memory chip 130. In addition, a line pattern of the first and second lines 112, 114 may be same as the line pattern described in FIG. 1 (a), FIG. 2 (a), or FIG. 2 (b). [0034]
According to the second embodiment, since the electronic board 300 is provided with the third lines 315, the locations of the first vias 316 and the second vias may be selected more flexibly. This may make the design of line patterns of the first and second lines 112 and 114 more flexible. In addition, the electronic board 300 has the same effects as those of the electronic boards 100, 200, 250 of the first embodiment and the exemplary variations as described above.
[0035]
It is to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised as defined by the appended claims.

Claims

1. An electronic board comprising:
a substrate (110);
a CPU (120) on a first side (110a) of the substrate;
a memory chip (130) on a second side (110b) of the other side of the first side of the substrate; and
signal lines (112, 114, 116) for connecting the CPU and the memory chip, wherein
the signal lines are located in the region held between a package of the CPU and a package of the memory chip.
2. The electronic board according to Claim 1, wherein signals which are required to prevent from cracking are transmitted through the signal lines.
3. The electronic board according to Claim 1 or 2, wherein the signal lines comprise first lines (112) on the first side, second lines (114) on the second side, and vias (116) for connecting the first lines and the second lines.
4. The electronic board according to Claim 3, wherein the vias are through-vias.
5. The electronic board according to Claim 3, wherein the vias are through-vias and a line pattern of at least one of the first line and the second line is formed so that the terminal and the through- via which are separated each other is connected.
6. The electronic board according to any of Claims 3 to 5, wherein
the substrate comprises a first and second layers, and third lines between the first and second layers and the vias comprises first vias through the first layer and the second vias through the second layer, and wherein the first vias are coupled to the second vias via the third lines.
PCT/CN2013/090577 2013-12-26 2013-12-26 Electronic board with anti-cracking performance WO2015096098A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2013/090577 WO2015096098A1 (en) 2013-12-26 2013-12-26 Electronic board with anti-cracking performance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2013/090577 WO2015096098A1 (en) 2013-12-26 2013-12-26 Electronic board with anti-cracking performance

Publications (1)

Publication Number Publication Date
WO2015096098A1 true WO2015096098A1 (en) 2015-07-02

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Country Status (1)

Country Link
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6388207B1 (en) * 2000-12-29 2002-05-14 Intel Corporation Electronic assembly with trench structures and methods of manufacture
US20020076919A1 (en) * 1998-11-13 2002-06-20 Peters Michael G. Composite interposer and method for producing a composite interposer
CN1925722B (en) * 2005-09-01 2010-04-07 日本特殊陶业株式会社 Wiring board construction including embedded ceramic capacitors
US20130277855A1 (en) * 2012-04-24 2013-10-24 Terry (Teckgyu) Kang High density 3d package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020076919A1 (en) * 1998-11-13 2002-06-20 Peters Michael G. Composite interposer and method for producing a composite interposer
US6388207B1 (en) * 2000-12-29 2002-05-14 Intel Corporation Electronic assembly with trench structures and methods of manufacture
CN1925722B (en) * 2005-09-01 2010-04-07 日本特殊陶业株式会社 Wiring board construction including embedded ceramic capacitors
US20130277855A1 (en) * 2012-04-24 2013-10-24 Terry (Teckgyu) Kang High density 3d package

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