WO2015084393A1

WO2015084393A1 - Semiconductor device having non-volatile memory with short-channeled transistors

Info

Publication number: WO2015084393A1
Application number: PCT/US2013/073571
Authority: WO
Inventors: Ning GE; Reynaldo V. VILLAVELEZ
Original assignee: Hewlett-Packard Development Company, L.P.
Priority date: 2013-12-06
Filing date: 2013-12-06
Publication date: 2015-06-11

Abstract

Semiconductor device having non-volatile memory with short-channeled transistors is described. In an example, a semiconductor device includes a non-volatile memory having a plurality of cells formed in rows and columns. A read/write line is coupled to each of the cells. Column select lines are coupled to columns of the cells. Row select lines are coupled to rows of the cells. Each of the cells includes a programmable transistor coupled to the read/write line. First and second select transistors are serially coupled between the programmable transistor and a reference voltage, such as electrical ground. Each of the first and second select transistors has a short-channeled gate (SCG) electrically coupled to one of the column select lines and one of the row select lines, respectively.

Description

SEMICONDUCTOR DEVICE HAVING NON-VOLATILE MEMORY WITH SHORT-CHANNELED TRANSISTORS

Background

[0001 ] Inkjet technology is widely used for precisely and rapidly dispensing small quantities of fluid. Inkjets eject droplets of fluid out of a nozzle by creating a short pulse of high pressure within a firing chamber. During printing, this ejection process can repeat thousands of times per second. Inkjet printing devices are implemented using semiconductor devices, such as thermal inkjet (TIJ) devices or piezoelectric inkjet (PIJ) devices. For example, a TIJ device is a semiconductor device including a heating element (e.g., resistor) in the firing chamber along with other integrated circuitry. To eject a droplet, an electrical current is passed through the heating element. As the heating element generates heat, a small portion of the fluid within the firing chamber is vaporized. The vapor rapidly expands, forcing a small droplet out of the firing chamber and nozzle. The electrical current is then turned off and the heating element cools. The vapor bubble rapidly collapses, drawing more fluid into the firing chamber.

Brief Description Of The Drawings

[0002] Some embodiments of the invention are described with respect to the following figures:

Fig. 1 is a block diagram of an ink jet printer according to an example implementation.

Fig. 2 is a block diagram showing the EPROM according to an example implementation. Fig. 3 is a block diagram showing a cell according to an example implementation.

Detailed Description

[0003] Semiconductor device having non-volatile memory with short- channeled transistors is described. In an example, a semiconductor device includes a non-volatile memory having a plurality of cells formed in rows and columns. A read/write line is coupled to each of the cells. Column select lines are coupled to columns of the cells. Row select lines are coupled to rows of the cells. Each of the cells includes a programmable transistor coupled to the read/write line. A "programmable transistor" can be, for example, a floating gate field effect transistor (FET), where the on-resistance (Ron) of the transistor is changeable by biasing the transistor to avalanche breakdown. Thus, the programmable transistor can have a Ron in one of two different states. First and second select transistors are serially coupled between the programmable transistor and a reference voltage, such as electrical ground. Each of the first and second select transistors has a short-channeled gate (SCG) electrically coupled to one of the column select lines and one of the row select lines, respectively.

[0004] The non-volatile memory can be programmed by changing the Ron of the programmable transistor in selected ones of the cells. Thereafter, a cell can be sensed to measure the Ron and decode the stored information (e.g., logic Ύ or logic '0' based on Ron). Thus, it becomes important that the change in Ron of the programmable transistor from one state to another be enough to be detectable. In addition, the total resistance of the cell is affected by the parasitic resistance of the select transistors. The inventors have found that the Ron of short-channeled select transistors is reduced as compared to long- channeled transistors, thereby reducing the parasitic resistance in the cell and increasing the program ratio (i.e., the ratio of total cell resistance after programming to total cell resistance before programming). Short-channeled transistors exhibit various secondary effects, such as drain-induced barrier lowering and punch through, surface scattering, velocity saturation, impact ionization, hot electron effect, and the like. Such secondary effects are often undesirable, leading designers to use long-channeled devices instead. The inventors have found that in the cells described herein, the configuration of the select transistors is such that the secondary effects do not affect the operation of the cell, while the reduction in Ron reduces parasitic resistance. Thus, short- channeled transistors can be used in the cell where such devices have heretofore been avoided.

[0005] Fig. 1 is a block diagram of an ink jet printer 102 according to an example implementation. The ink jet printer 102 includes a print controller 106 and a printhead 108. The print controller 106 is coupled to the printhead 108. The print controller 106 receives printing data representing an image to be printed to media (media not shown for clarity). The print controller 106 generates signals for activating drop ejectors on the printhead 108 to eject ink onto the media and produce the image. The print controller 106 provides the signals to the printhead 108 based on the printing data.

[0006] The print controller 106 includes a processor 120, a memory 122, input/output (IO) circuits 1 16, and various support circuits 1 18. The processor 120 can include any type of microprocessor known in the art. The support circuits 1 18 can include cache, power supplies, clock circuits, data registers, and the like. The memory 122 can include random access memory, read only memory, cache memory, magnetic read/write memory, or the like or any combination of such memory devices. The IO circuits 1 16 can by coupled to the printhead 108. The IO circuits 1 16 can also be coupled to external devices, such as a computer 104. For example, the IO circuits 1 16 can receive printing data from an external device (e.g., the computer 104), and provide signals to the printhead 108 using the IO circuits 1 16.

[0007] The printhead 108 includes a plurality of drop ejectors 1 10, a nonvolatile memory 1 1 1 , such as an erasable programmable read-only memory (EPROM) or the like, and associated integrated circuitry 130. For purposes of clarity by example, the non-volatile memory 1 1 1 is hereafter assumed to be an EPROM. The EPROM 1 1 1 includes a plurality of cells 1 12 each configured to store information (e.g., a "bit" of information). The EPROM 1 1 1 can be used to store various information, such as identification information for the printhead 108. The cells 1 12 can be mapped into banks addressable using a row and column select addressing scheme for reading and writing. The circuits 130 can include, for example, an address generator or the like for addressing the

EPROM 1 1 1 using row and column select signals, as discussed further below.

[0008] The drop ejectors 1 10 are in fluidic communication with an ink supply (not shown) for receiving ink. For example, ink can be provided from a container. In an example, the printhead 108 is a thermal ink jet (TIJ) device. The drop ejectors 1 10 generally include a heating element, a firing chamber, and a nozzle. Ink from the ink supply fills the firing chambers. To eject a droplet, an electrical current is passed through the heater element placed adjacent to the firing chamber. The heating element generated heat, which vaporizes a small portion of the fluid within the firing chamber. The vapor rapidly expands, forcing a small droplet out of the firing chamber and nozzle. The electrical current is then turned off and the resistor cools. The vapor bubble rapidly collapses, drawing more fluid into the firing chamber from the ink supply. In other examples, the printhead 108 can be a piezoelectric ink jet (PIJ) device or other type of device that ejects ink.

[0009] Fig. 2 is a block diagram showing the EPROM 1 1 1 according to an example implementation. The EPROM 1 1 1 includes the cells 1 12 formed into an array of rows and columns. Each of the cells 1 12 is configured to store a bit of information (e.g., a logic '1 ' or Ό'). An address generator 208 is configured to generate address signals. The address generator 208 couples the address signals to a row bus 204 and a column bus 206. Individual cells 1 12 can be selected using a row and column address signals. Individual cells 1 12 can be read from or written to using the read/write line 202. As discussed below, each of the cells 1 12 includes a short-channeled gate (SCG) design for row and column select transistors, which increases program ratio and tightens resistance distribution.

[0010] Fig. 3 is a block diagram showing a cell 1 12 according to an example implementation. The cell 1 12 includes a transistors 302, 306, and 308, and a resistor 304. The transistors 302, 306, and 308 are field effect transistors (FETs), such as N-type metal oxide semiconductor FETs (MOSFETs). A source of the transistor 302 is coupled to the read/write line through the resistor 304. A drain of the transistor 302 is coupled to a source of the transistor 306. A drain of the transistor 302 is coupled to a source of the transistor 308. A drain of the transistor 308 is coupled to a reference voltage, such as electrical ground. A floating gate of the transistor 302 is coupled to the read/write line as control gate. A gate of the transistor 306 is coupled to a column select line. A gate of the transistor 308 is coupled to a row select line.

[001 1 ] The transistor 302 has a "floating gate" (i.e., the gate is electrically isolated) and is configured as the EPROM transistor. Programming of the cell is achieved by biasing the drain junction of the transistor 302 to avalanche breakdown, where the electrons in the avalanche area were injected from the drain region into the floating gate through hot carrier injection and Folwer- Nordheim tuning as free electrons and retained when power is removed. With the electrons trapped into the floating gate, gate voltage of the transistor 302 becomes more negative. The on-resistance (Ron) is thus increased to a certain value when voltage is applied to the control gate connected to read/write line. If no voltage is applied to the read/write line, the Ron does not increase. By either programming or not programming the cell 1 12 (e.g., applying or not applying a voltage to the read/write line), two difference Ron resistances can be achieved, which can be sensed as two distinct states: logic '1 ' and logic Ό'. The resistor 304 can provide a current limiter and cooperates with the transistors 306 and 308 to select the transistor 302.

[0012] The transistors 306 and 308 determine whether the transistor 302 is biased for reading/writing. When both the transistors 306 and 308 are turned on, the transistor 302 is biased and configured for reading/writing. If either of the transistors 306 and 308 is turned off, then the transistor 302 is not biased and cannot be programmed or read. When the transistor 302 is biased, the Ron of the transistor 302 can be measured (read) or altered (written) as discussed above through the read/write line. Generally, the transistors 306 and 308 exhibit a lower resistance (e.g., on the order of 100 ohms) as compared to the Ron of the transistor 302 (e.g., on the order of 1000 ohms). Thus, the overall resistance of the cell 1 12 measured from the read/write line primarily depends on the Ron of the transistor 302, with the transistors 306 and 308 providing parasitic resistance. The parasitic resistance measurement by the transistors 306 and 308 is not negligible and can affect the program ratio of the cell 1 12. The "program ratio" can be defined as the resistance of the cell 1 12 after programming divided by the resistance of the cell 1 12 before programming. Lower program ratio can cause yield loss during manufacturing, as the

"programmed" and "not programmed" resistance states become more difficult to distinguish and hence the cell 1 12 cannot effectively store a bit of information.

[0013] In an example, the transistors 306 and 308 are designed with a short- channeled gate to lower the parasitic resistance effect and thereby increase the program ratio of the cell 1 12. The SCG transistors 306 and 308 also increase hot carrier injection for the transistor 302 to have a tighter distribution. In electronics, a short-channel effect (SCE) is an effect whereby a MOSFET has a channel length on the same order of magnitude as the depletion-layer widths of the source and drain junction. Such a short channel causes several secondary effects, such as drain induced barrier lowering and punch through, surface scattering, velocity saturation, impact ionization, and hot electron effect. Short- channel transistors also exhibit a lower Ron. That is, as the channel length is reduces, the Ron is also reduced. Since the transistors 306 and 308 are connected to the lower potential side of the transistor 302 (e.g., a small voltage drop to the reference voltage over the transistors 306 and 308 due to the voltage divide effect), avalanche breakdown or other short-channel effects do not impact operation of the cell 1 12. [0014] Consider the following example. Assume the transistor 302 has a Ron of 3000 ohms before programming and 6000 ohms after programming. Assume further that the Ron of a non-SCG column select transistor is 100 ohms, and the Ron of a non-SCG row select transistor is 200 ohms. Thus, the total resistance of such an EPROM cell before programming is 3300 ohms and after programming is 6300 ohms. This results in a program ratio of 1 .91 . Now assume the column and row select transistors have short-channeled gates, as described above for the transistors 306 and 308. For example, the transistor 306 can have a Ron of 50 ohms, and the transistor 308 can have a Ron of 100 ohms. Thus, the total resistance of the cell 1 12 before programming is 3150 ohms and after programming is 6150 ohms. This results in a program ratio of 1 .95 and above, which is improved over the first scenario where the row and column select transistors do not have short-channeled gates due to the lower parasitic effect and gained HCI efficiency improvement.

[0015] In the foregoing description, numerous details are set forth to provide an understanding of the present invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these details. While the invention has been disclosed with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover such modifications and variations as fall within the true spirit and scope of the invention.

Claims

What is claimed is:

1 . A semiconductor device, comprising:

a non-volatile memory having a plurality of cells formed in rows and columns; and

a read/write line coupled to each of the plurality of cells, column select lines coupled to the columns of cells, and row select lines coupled to rows of the cells; where each of the cells includes a programmable transistor coupled to the read/write line, and first and second select transistors serially coupled between the programmable transistor and a reference voltage, each of the first and second select transistors having a short-channeled gate (SCG) electrically coupled to one of the column select lines and one of the row select lines, respectively.

2. The printhead of claim 1 , wherein the programmable transistor comprises a field effect transistor (FET) having a floating gate.

3. The printhead of claim 2, wherein the programmable transistor in each of the plurality of cells is programmed to have either a first on-resistance (Ron) or second Ron.

4. The printhead of claim 1 , wherein each of the first and second select transistors comprises a field effect transistor (FET) including a source, a drain, and a gate, the gate having a width such that a channel formed between the source and drain has a length of the same magnitude of depletion-layer widths of the source and the drain.

5. The printhead of claim 4, wherein the width of the gate of each of the first and second select transistors is less than or equal to a width of the gate of the

programmable transistor.

6. A printhead, comprising:

a plurality of drop ejectors; a non-volatile memory having an array of cells each having a programmable transistor that is addressable using a column select transistor and a row select transistor, where each of the column select transistor and the row select transistor has a short-channeled gate (SCG).

7. The printhead of claim 6, further comprising:

a read/write line coupled to each of the cells; and

an address generator having row select lines coupled to rows of the cells and column select lines coupled to columns of the cells.

8. The printhead of claim 6, wherein the programmable transistor comprises a field effect transistor (FET) having a floating gate.

9. The printhead of claim 8, wherein the programmable transistor in each of the plurality of cells is programmed to have either a first on-resistance (Ron) or second Ron.

10. The printhead of claim 6, wherein each of row and column select transistors comprises a field effect transistor (FET) including a source, a drain, and a gate, the gate having a width such that a channel formed between the source and drain has a length of the same magnitude of depletion-layer widths of the source and the drain.

1 1 . The printhead of claim 10, wherein the width of the gate of each of the row and column select transistors is less than or equal to a width of the gate of the programmable transistor.