WO2015043499A1 - 一种半导体封装结构及其成型方法 - Google Patents

一种半导体封装结构及其成型方法 Download PDF

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Publication number
WO2015043499A1
WO2015043499A1 PCT/CN2014/087508 CN2014087508W WO2015043499A1 WO 2015043499 A1 WO2015043499 A1 WO 2015043499A1 CN 2014087508 W CN2014087508 W CN 2014087508W WO 2015043499 A1 WO2015043499 A1 WO 2015043499A1
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Prior art keywords
pin
heat sink
frame
chip
lead frame
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PCT/CN2014/087508
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English (en)
French (fr)
Inventor
曹周
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杰群电子科技（东莞）有限公司
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Priority to US15/022,055 priority Critical patent/US9673138B2/en
Priority to JP2016537120A priority patent/JP2016532297A/ja
Publication of WO2015043499A1 publication Critical patent/WO2015043499A1/zh

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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the invention belongs to the field of semiconductor packaging, and in particular relates to a semiconductor package structure and a molding method thereof.
  • the lead frame is the skeleton of the semiconductor integrated circuit, and the lead frame is used as the chip carrier of the integrated circuit or the discrete device, and is a key for forming an electrical circuit by electrically connecting the terminal of the chip to the outer lead by means of the key alloy wire.
  • the lead frame is mainly composed of two parts: the chip holder and the pin. The chip holder provides mechanical support for the chip during the packaging process, and the pin is the electrical path connecting the chip to the outside of the package.
  • the function of the lead frame is obvious. First, it plays a supporting role for the packaged electronic device, while preventing the resin from suddenly escaping between the leads to provide support for the plastic. Secondly, it connects the chip to the substrate, providing the power of the chip circuit board. Hot aisle. When an integrated circuit is used, heat is inevitably generated. In particular, a circuit with a large power consumption generates more heat. Therefore, the lead frame must have good thermal conductivity during operation, otherwise it will work. The chip is burned out due to the large amount of heat and the inability to dissipate in time.
  • the main function of the lead frame is to provide a mechanical support carrier for the integrated circuit chip, and to connect the external circuit of the integrated circuit as a conductive medium, transmit electrical signals, and together with the packaging material, dissipate heat generated when the chip operates.
  • the existing lead frame is dissipated through the heat sink, but the disadvantage is that due to too many pins on the chip, The heat generation is too slow, and there are many other defects in the combination of the existing lead frame and the heat sink, such as inaccurate combination and inefficiency.
  • the Chinese utility model patent CN201629305U discloses a heat dissipation package structure of a lead frame, comprising a lead frame and a heat sink, wherein: a through hole is formed around the lead frame and the through hole is matched with a bump on the heat sink. The lead frame and the heat sink are press-fitted to the bump via the through hole.
  • the package structure is connected by bump stamping, but the heat dissipation function is limited.
  • An integrated circuit lead frame heat sink is disclosed in the Chinese utility model patent CN202394951U.
  • the integrated circuit lead frame heat sink of the utility model has a groove in the middle of the bottom surface of the sheet body, and a groove is matched in the groove.
  • the insert is silver plated on the outer surface of the insert.
  • the integrated circuit lead frame heat sink has limited heat dissipation function.
  • the invention provides a semiconductor package structure with clear and simple structure and good heat dissipation function.
  • the invention also provides a semiconductor package structure forming method which at least realizes a clear and simple structure of the package structure and a good heat dissipation function.
  • the present invention firstly provides a semiconductor package structure including a heat sink frame and a lead frame, the heat sink frame is connected with a heat sink, a chip is attached to the chip holder of the lead frame, and the heat sink and the chip are connected by a bonding material.
  • the lead frame is provided with a first pin
  • the heat sink frame is provided with a second pin and a third pin.
  • the four first pins on the lead frame are connected to the bottom electrode of the chip holder, which is a current input end; the three second pins on the heat sink frame are connected with the upper surface electrode of the chip, and are current output ends;
  • the third pin soldering wire on the heat sink frame is the current control terminal.
  • the lead frame is provided with a positioning groove
  • the heat sink frame is provided with a positioning leg.
  • the lead frame and the heat sink frame are respectively provided with a first link and a second link.
  • the invention also provides a semiconductor package structure forming method, which comprises the following steps:
  • a semi-etched area is arranged around the chip holder of the lead frame, the first pin is connected to the chip holder, and the chip holder electrode is directly connected to the first pin, and the first pin is provided with the first crawler a tin hole, the lead frame is further provided with a positioning groove and a first connecting rod;
  • Soldering chip soldering the chip on the chip holder using a bonding material
  • the heat sink frame is provided with a second pin and a third pin, and the second pin and the third pin are respectively provided with a second climbing hole, and the heat sink frame is further provided There is a second connecting rod and a positioning leg, and the heat sink frame is connected with a heat sink;
  • Chip soldering fin the bonding fin is used to solder the heat sink to the chip, and the positioning pin on the heat sink frame is inserted into the positioning groove on the lead frame;
  • Bonding wire use a wire to connect the third pin to the chip to achieve conduction
  • Injection molding a film is applied on the back surface of the lead frame, so that the upper surface of the semiconductor and the surface of the film are attached to the upper and lower surfaces of the abrasive tool during injection molding, and then the surfaces are exposed after the molding;
  • the first pin, the second pin, the third pin and the lead frame exposed on the outside of the glue are plated with a tin layer. At this time, the first climbing hole and the second climbing hole are also plated with tin. Floor;
  • Cutting the foot The excess lead frame and the heat sink frame, the first link, and the second link are cut off using the mold, and the excess portions of the first pin, the second pin, and the third pin are cut off.
  • the fin frame is provided with support legs for balancing the fins on the chip.
  • the lead frame is provided with a pin recognition hole.
  • the lead frame and the heat sink frame are provided with a back half etching region and a front half etching region.
  • the tin layer is contained after the excess portion of the first pin, the second pin and the third pin is cut, and the first pin, the second pin and the third pin are cut.
  • the position is the first climbing tin hole and the second climbing tin hole.
  • one lead frame is welded with 100 heat sinks each time the solder is soldered.
  • the first pin is connected to the bottom electrode of the chip holder and is a current input end; the three second pins on the heat sink frame are connected with the upper surface electrode of the chip, which is a current output end; the third on the heat sink frame
  • the pin welding wire is a current control terminal; the wire application is greatly reduced, thereby reducing heat loss.
  • the arrangement of the first climbing hole and the second climbing hole enables the tin layer on the sidewall of the cutting foot to be retained, thereby improving the reliability of soldering of the semiconductor and the circuit board.
  • FIG. 1 is a schematic structural view of a semiconductor package structure of the present invention
  • FIG. 2 is a schematic structural view of a lead frame of the present invention
  • Figure 3 is a side view of the lead frame of the present invention.
  • FIG. 4 is a schematic structural view of a heat sink frame of the present invention.
  • Figure 5 is a side elevational view of the heat sink frame of the present invention.
  • the present invention provides a semiconductor package structure including a heat sink frame 2 and a lead frame 1, to which a heat sink 4 is attached, and a chip holder 21 of the lead frame 1 is attached
  • the chip 3, the heat sink 4 and the chip 3 are connected together by a bonding material 5, wherein the lead frame 1 is provided with a first pin 22, and the heat sink frame 2 is provided with a second pin 43 and a third pin 44.
  • the four first pins 22 of the lead frame 1 are connected to the bottom electrode of the chip holder 21 as a current input terminal; the three second pins 43 on the heat sink frame 2 are connected to the upper surface electrode of the chip 3. It is a current output terminal; the third pin 44 on the heat sink frame 2 is welded with a wire, which is a current control terminal.
  • the lead frame 1 is provided with a positioning groove 25, and the heat sink frame 2 is provided with a positioning leg 48. More specifically, the lead frame 1 and the fin frame 2 are provided with a first link 27 and a second link 46, respectively.
  • the bonding material 5 is any bonding material known to those skilled in the art as long as it can accomplish its object in the present invention.
  • the present invention also provides a semiconductor package structure forming method, which comprises the following steps:
  • the lead frame 1 is prepared: a half etching region 23 is disposed around the chip holder 21 of the lead frame 1, and the first pin 22 is connected to the chip holder 21, and the electrode of the chip holder 21 is directly connected to the first pin 22, the first a first climbing hole 24 is disposed on the pin 22, and the lead frame 1 is further provided with a positioning groove 25, a foot recognition hole 26 and a first link 27;
  • Soldering chip 3 using the bonding material 5 to solder the chip 3 on the chip holder 21;
  • the heat sink frame 2 is provided with a back half etching region 41 and a front half etching region 42, and is provided with a second pin 43 and a third pin 44, a second pin 43 and a third A second climbing hole 45 is disposed on the pin 44.
  • the heat sink frame 2 is further provided with a second connecting rod 46, a supporting leg 47 and a positioning leg 48.
  • the heat sink frame 2 is connected with a heat sink 4 ;
  • the chip 3 is soldered to the heat sink 4: the heat sink 4 is soldered to the chip 3 using the bonding material 5, and the positioning legs 48 on the heat sink frame 2 are inserted into the positioning grooves 25 on the lead frame 1;
  • Bonding wire the third pin 44 is connected to the chip 3 by using a wire to achieve conduction
  • Injection molding a film is applied on the back surface of the lead frame 1, so that the upper surface of the semiconductor and the surface of the film are attached to the upper and lower surfaces of the abrasive tool during injection molding, and then the double surfaces are exposed after the molding;
  • Electroplating the first pin 22, the second pin 43, the third pin 44 and the lead frame 1 exposed outside the glue are plated with a tin layer, at this time, the first climbing hole 24 and the second climbing hole 45 will also be plated with tin;

Abstract

一种半导体封装结构及其成型方法，所述半导体封装结构包括散热片框架（2）和引线框架（1），所述散热片框架（2）连有散热片（4），所述引线框架（1）的芯片座（21）上贴有芯片（3），所述散热片（4）和芯片（3）通过结合材（5）连接在一起，所述引线框架（1）设有第一管脚（22），所述散热片框架（2）上设有第二管脚（43）和第三管脚（44）。所述半导体封装结构成型方法将第二管脚（43）、第三管脚（44）设置在散热片（4）上面，第一管脚（22）与芯片座（21）底部电极相连接，为电流输入端；散热片框架（2）上的3个第二管脚（43）与芯片（3）上表面电极相连接，为电流输出端；散热片框架（2）上的第三管脚（44）焊接导线，为电流控制端，大大减少了导线的应用，进而减少热量的损耗；注塑成型后，半导体双面均露出胶体，实现双面散热，提高半导体的散热功能。

Description

一种半导体封装结构及其成型方法
本专利申请要求于2013年09月26日提交的，申请号为201310443963.4，申请人为杰群电子科技(东莞)有限公司，发明名称为“一种半导体封装结构及其成型方法”的中国专利申请的优先权，该申请的全文以引用的方式并入本申请中。
技术领域
本发明属于半导体封装领域，具体涉及一种半导体封装结构及其成型方法。
背景技术
近些年来，随着半导体器件的集成度越来越高，其存储量、信号处理速度和功率也越来越高，但其体积却越来越小，这一趋势加速了半导体集成电路的高速发展。其中，引线框架是半导体集成电路的骨架，引线框架作为集成电路或分立器件的芯片载体，是一种借助于键合金丝实现芯片内部电路引出端与外引线的电气连接、从而形成电气回路的关键结构件，它起到了和外部导线连接的桥梁作用。引线框架主要由两部分组成：芯片座和引脚。其中芯片座在封装过程中为芯片提供机械支撑，而引脚则是连接芯片到封装外的电学通路。引线框架的功能是显而易见的，首先它起到了封装电子器件的支撑作用，同时防止树脂在引线间突然涌出，为塑料提供支撑；其次它使芯片连接到基板，提供了芯片线路板的电及热通道。集成电路在使用时，不可避免的会产生热量，尤其是功耗较大的电路，产生的热量更大，因此在工作时就要求引线框架必须具有很好的导热性，否则在工作中就会由于热量较大且不能及时散发出去而烧坏芯片。引线框架的主要功能是为集成电路芯片提供机械支撑载体，并且作为导电介质连接集成电路外部电路、传送电信号，以及与封装材料一起，向外散发芯片工作时产生的热量。
现有导线框架通过散热片来进行散热，但缺点是由于芯片上管脚过多，造 成热量散发过慢，同时现有导线框架与散热片的结合还有很多其他缺陷，比如：结合不精确、效率低下等。
中国实用新型专利CN201629305U中公开了一种引线框架的散热封装结构，包括一引线框架及散热片，其中：所述引线框架四周开设有通孔与所述通孔配合在散热片上开设有凸块，所述引线框架及散热片经通孔与凸块冲压卡合连接。所述封装结构通过凸块冲压卡合连接这种方式，但散热功能有限。
中国实用新型专利CN202394951U中公开了一种集成电路引线框架散热片，该实用新型的集成电路引线框架散热片，在片体底面中部设一个凹槽，在凹槽内设有一个与凹槽匹配一致的镶件，在镶件的外表面上镀银层。所述集成电路引线框架散热片散热功能有限。
发明内容
本发明提供了一种构造清晰简洁、散热功能良好的半导体封装结构；本发明同时提供了一种至少实现封装结构构造清晰简洁、散热功能良好的半导体封装结构成型方法。
本发明首先提供一种半导体封装结构，包括散热片框架和引线框架，所述散热片框架连有散热片，所述引线框架的芯片座上贴有芯片，所述散热片和芯片通过结合材连接在一起，所述引线框架设有第一管脚，所述散热片框架上设有第二管脚和第三管脚。
其中，所述引线框架上4个第一管脚与芯片座底部电极相连接，为电流输入端；散热片框架上的3个第二管脚与芯片上表面电极相连接，为电流输出端；散热片框架上的第三管脚焊接导线，为电流控制端。
较佳地，为控制引线框架和散热片框架的精确位置叠合，所述引线框架上设有定位槽，所述散热片框架上设有定位脚。
较佳地，为了将芯片座和散热片与相对应的框架连接及提高连接强度，所述引线框架和散热片框架上分别设有第一连杆和第二连杆。
本发明同时提供一种半导体封装结构成型方法，其包括以下步骤：
准备引线框架：所述引线框架的芯片座四周设有半蚀刻区，第一管脚连接芯片座，将芯片座电极直接导通第一管脚，所述第一管脚上设有第一爬锡孔，所述引线框架上还设有定位槽和第一连杆；
焊接芯片：使用结合材在芯片座上面焊接芯片；
准备散热片框架：所述散热片框架上设有第二管脚和第三管脚，第二管脚和第三管脚上皆设有第二爬锡孔，所述散热片框架上还设有第二连杆和定位脚，所述散热片框架上连有散热片；
芯片焊接散热片：使用结合材将散热片与芯片焊接，同时散热片框架上的定位脚插入到引线框架上的定位槽内；
焊线：使用导线将第三管脚与芯片连接，实现导通；
载入治具烘烤：将焊线后的半导体放入治具，然后送入烤箱烘烤，烘烤后结合材固化，进而半导体整体高度确定；
注塑成型：在引线框架背面贴上一次胶膜，从而在注塑的时候半导体上表面和胶膜表面贴合在磨具的上下表面，进而成型后双表面均露出胶体；
电镀：将裸露在胶体外的第一管脚、第二管脚、第三管脚和引线框架上镀上锡层，此时，第一爬锡孔和第二爬锡孔也会镀上锡层；
切脚成型：使用模具将多余的引线框架和散热片框架、第一连杆、第二连杆切除，同时将第一管脚、第二管脚和第三管脚多余部分切除。
较佳地，所述散热片框架上设有用来平衡散热片站立在芯片上的支撑脚。
较佳地，为了防止在安装时无法区分各个管脚的脚位将半导体装反，所述引线框架上设有脚位识别孔。
其中，为了注塑时能够牢牢锁住树脂，所述引线框架及散热片框架上设有背面半蚀刻区和正面半蚀刻区。
更佳地，为增加第一管脚、第二管脚和第三管脚切除多余部分后尽可能多的含有锡层，在切除第一管脚、第二管脚和第三管脚时切割位置为第一爬锡孔和第二爬锡孔处。
更佳地，为增加焊接效率，在为芯片焊接散热片时，每次焊接时一引线框架焊接100个散热片。
本发明至少具有以下优点：
1)将第二管脚、第三管脚设置在散热片上面，减少了导线的使用减少了作业流程加速了散热，同时减少了第二连杆的使用，解决了后续注塑成型及第二连杆切割问题。
2)第一管脚与芯片座底部电极相连接，为电流输入端；散热片框架上的3个第二管脚与芯片上表面电极相连接，为电流输出端；散热片框架上的第三管脚焊接导线，为电流控制端；大大减少了导线的应用，进而减少热量的损耗。
3)注塑成型后，半导体双面均露出胶体，实现双面散热，提高半导体的散热功能。
4)通过定位槽和定位脚，能够精确控制引线框架和散热片框架的位置叠合。
5)第一爬锡孔和第二爬锡孔的设置，使得切脚成型后侧壁上的锡层能够保留下来，提高了半导体与电路板焊接的可靠性。
6)通过散热片凸出高度、治具压紧后烘烤以及引线框架贴胶膜等工艺有效的防止了溢胶的发生及芯片的破裂。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明半导体封装结构的结构示意图；
图2是本发明引线框架的结构示意图；
图3是本发明引线框架侧视图；
图4是本发明散热片框架的结构示意图；
图5是本发明散热片框架侧视图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例1
参考本发明的图1至图5，本发明提供了一种半导体封装结构，包括散热片框架2和引线框架1，散热片框架2连有散热片4，引线框架1的芯片座21上贴有芯片3，散热片4和芯片3通过结合材5连接在一起，其中，引线框架1设有第一管脚22，散热片框架2上设有第二管脚43和第三管脚44。
具体地，引线框架1上4个第一管脚22与芯片座21底部电极相连接，为电流输入端；散热片框架2上的3个第二管脚43与芯片3上表面电极相连接，为电流输出端；散热片框架2上的第三管脚44焊接导线，为电流控制端。
具体地，引线框架1上设有定位槽25，散热片框架2上设有定位脚48。更具体地，引线框架1和散热片框架2上分别设有第一连杆27和第二连杆46。其中，结合材5为本领域技术人员所公知的任意一种结合材料，其只要能够完成其在本发明中的目的即可。
实施例2
参考图1至图5，本发明还提供了一种半导体封装结构成型方法，其包括以下步骤：
准备引线框架1：所述引线框架1的芯片座21四周设有半蚀刻区23，第一管脚22连接芯片座21，将芯片座21电极直接导通第一管脚22，所述第一管脚22上设有第一爬锡孔24，所述引线框架1上还设有定位槽25、脚位识别孔26和第一连杆27；
焊接芯片3：使用结合材5在芯片座21上面焊接芯片3；
准备散热片框架2：所述散热片框架2上设有背面半蚀刻区41和正面半蚀刻区42，同时设有第二管脚43和第三管脚44，第二管脚43和第三管脚44上皆设有第二爬锡孔45，所述散热片框架2上还设有第二连杆46、支撑脚47和定位脚48，所述散热片框架2上连有散热片4；
芯片3焊接散热片4：使用结合材5将散热片4与芯片3焊接，同时散热片框架2上的定位脚48插入到引线框架1上的定位槽25内；
焊线：使用导线将第三管脚44与芯片3连接，实现导通；
载入治具烘烤：将焊线后的半导体放入治具，然后送入烤箱烘烤，烘烤后结合材固化，进而半导体整体高度确定；
注塑成型：在引线框架1背面贴上一次胶膜，从而在注塑的时候半导体上表面和胶膜表面贴合在磨具的上下表面，进而成型后双表面均露出胶体；
电镀：将裸露在胶体外的第一管脚22、第二管脚43、第三管脚44和引线框架1上镀上锡层，此时，第一爬锡孔24和第二爬锡孔45也会镀上锡层；
切脚成型：使用模具将多余的引线框架1和散热片框架2、第一连杆27、第二连杆46切除，同时将第一管脚22、第二管脚43和第三管脚44多余部分切除。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (10)

  1. 一种半导体封装结构，包括散热片框架和引线框架，所述散热片框架连有散热片，所述引线框架的芯片座上贴有芯片，所述散热片和芯片通过结合材连接在一起，其特征是，所述引线框架设有第一管脚，所述散热片框架上设有第二管脚和第三管脚。
  2. 根据权利要求1所述一种半导体封装结构，其特征是，所述引线框架上4个第一管脚与芯片座底部电极相连接，为电流输入端；散热片框架上的3个第二管脚与芯片上表面电极相连接，为电流输出端；散热片框架上的第三管脚焊接导线，为电流控制端。
  3. 根据权利要求2所述一种半导体封装结构，其特征是，所述引线框架上设有定位槽，所述散热片框架上设有定位脚。
  4. 根据权利要求1所述一种半导体封装结构，其特征是，所述引线框架和散热片框架上分别设有第一连杆和第二连杆。
  5. 一种半导体封装结构成型方法，其特征是，其包括以下步骤：
    准备引线框架：所述引线框架的芯片座四周设有半蚀刻区，第一管脚连接芯片座，将芯片座电极直接导通第一管脚，所述第一管脚上设有第一爬锡孔，所述引线框架上还设有定位槽和第一连杆；
    焊接芯片：使用结合材在芯片座上面焊接芯片；
    准备散热片框架：所述散热片框架上设有第二管脚和第三管脚，第二管脚和第三管脚上皆设有第二爬锡孔，所述散热片框架上还设有第二连杆和定位脚，所述散热片框架上连有散热片；
    芯片焊接散热片：使用结合材将散热片与芯片焊接，同时散热片框架上的定位脚插入到引线框架上的定位槽内；
    焊线：使用导线将第三管脚与芯片连接，实现导通；
    载入治具烘烤：将焊线后的半导体放入治具，然后送入烤箱烘烤，烘烤后结合材固化，进而半导体整体高度确定；
    注塑成型：在引线框架背面贴上一次胶膜，从而在注塑的时候半导体上表面和胶膜表面贴合在磨具的上下表面，进而成型后双表面均路出胶体；
    电镀：将裸露在胶体外的第一管脚、第二管脚、第三管脚和引线框架上镀 上锡层，此时，第一爬锡孔和第二爬锡孔也会镀上锡层；
    切脚成型：使用模具将多余的引线框架和散热片框架、第一连杆、第二连杆切除，同时将第一管脚、第二管脚和第三管脚多余部分切除。
  6. 根据权利要求5所述一种半导体封装结构成型方法，其特征是，所述散热片框架上设有用来平衡散热片站立在芯片上的支撑脚。
  7. 根据权利要求5所述一种半导体封装结构成型方法，其特征是，所述引线框架上设有脚位识别孔。
  8. 根据权利要求5所述一种半导体封装结构成型方法，其特征是，所述散热片框架上设有背面半蚀刻区和正面半蚀刻区。
  9. 根据权利要求5所述一种半导体封装结构成型方法，其特征是，在切除第一管脚、第二管脚和第三管脚时切割位置为第一爬锡孔和第二爬锡孔处。
  10. 根据权利要求5所述一种半导体封装结构成型方法，其特征是，在芯片焊接散热片时，每次焊接时一引线框架焊接100个散热片。
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