WO2015002681A1 - Monolithic integrated circuit die having modular die regions stitched together - Google Patents
Monolithic integrated circuit die having modular die regions stitched together Download PDFInfo
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- WO2015002681A1 WO2015002681A1 PCT/US2014/033526 US2014033526W WO2015002681A1 WO 2015002681 A1 WO2015002681 A1 WO 2015002681A1 US 2014033526 W US2014033526 W US 2014033526W WO 2015002681 A1 WO2015002681 A1 WO 2015002681A1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31721—Power aspects, e.g. power supplies for test circuits, power saving during test
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31723—Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318516—Test of programmable logic devices [PLDs]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
- H03K19/1774—Structural details of routing resources for global signals, e.g. clock, reset
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/17772—Structural details of configuration resources for powering on or off
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/1778—Structural details for adapting physical parameters
- H03K19/17788—Structural details for adapting physical parameters for input/output [I/O] voltages
Definitions
- ICs integrated circuit devices
- the following description relates to a monolithic integrated circuit die having modular die regions stitched together for an IC.
- Integrated circuits have become more "dense" over time, i.e., more logic features have been implemented in an IC of a given size. Therefore, power consumption has become an increasingly more significant issue, including power consumption during wafer-level testing. Hence, it is desirable to provide an IC having power consumption more suitable for wafer-level testing.
- An apparatus relates generally to a monolithic integrated circuit die.
- the monolithic integrated circuit die has a plurality of modular die regions.
- the modular die regions respectively have a plurality of power distribution networks for independently powering each of the modular die regions.
- Each adjacent pair of the modular die regions is stitched together with a respective plurality of metal lines.
- a method relates generally to a monolithic integrated circuit die.
- an obtained monolithic integrated circuit die has a first die region and a second die region.
- the first die region has a first power distribution network
- the second die region has a second power distribution network.
- the first power distribution network is separate from the second power distribution network for operation of the first die region independently from the second die region.
- the first die region and the second die region are interconnected to one another through a first plurality of metal lines and a second plurality of metal lines.
- the first plurality of metal lines and the second plurality of metal lines are coupled to a first plurality of select circuits and a second plurality of select circuits.
- the first die region is powered up with the first power distribution network while leaving the second power distribution network of the second die region powered down.
- the first die region is put in a loopback mode.
- the first die region is tested while in the loopback mode.
- the monolithic integrated circuit die has a first die region and a second die region.
- the first die region has a first power distribution network
- the second die region has a second power distribution network.
- the first power distribution network is separate from the second power distribution network for operation of the first die region independently from the second die region.
- the first die region and the second die region are
- the first die region has a defective portion.
- the second die region is used to provide the monolithic integrated circuit die as a functional die with the defective portion isolated from the second die region.
- FIG. 1 is a simplified block diagram depicting an exemplary columnar Field Programmable Gate Array (“FPGA”) architecture.
- FPGA Field Programmable Gate Array
- FIG. 2 is a block diagram of a top view depicting an exemplary monolithic integrated circuit die ("die”) having die regions.
- die monolithic integrated circuit die
- FIG. 3 is a block diagram of a cross-sectional view depicting an exemplary portion of a monolithic integrated circuit die (“die”), which may be the die of FIG. 2.
- die monolithic integrated circuit die
- FIG. 4 is a block diagram from a top view depicting an exemplary portion of a prior wafer having multiple die regions.
- FIG. 5 is a block diagram from a top view depicting an exemplary portion of a wafer having multiple die regions, such as die regions of FIG. 2 for example.
- FIG. 6 is a block diagram depicting an exemplary layer stack, such as for die regions of FIG. 2 for example.
- FIG. 7 is a bock diagram depicting an exemplary die of FIG. 2 with three die regions of different sizes.
- FIG. 8 is a flow diagram depicting an exemplary wafer-level test flow.
- FIG. 9 is a flow diagram depicting an exemplary chip-level test flow.
- Formation of monolithic integrated circuit die may be limited by a maximum field size of a lithography used. Furthermore, even if a monolithic integrated circuit die is formed which exceeds such a maximum field size, it may consume too much power to be tested at a wafer level. However, a monolithic integrated circuit die may have performance advantages over a functionally equivalent stacked die or stacked interposer die.
- Such monolithic integrated circuit die has separately powered modular die regions, which may be isolated from one another. Furthermore, a monolithic integrated circuit die may be operated in a loopback mode or a interconnected die region mode ("stitch mode").
- PLDs Programmable logic devices
- FPGA field programmable gate array
- programmable tiles can include, for example, input/output blocks (“lOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth.
- lOBs input/output blocks
- CLBs configurable logic blocks
- BRAMs dedicated random access memory blocks
- DSPs digital signal processing blocks
- processors processors
- clock managers delay lock loops
- DLLs delay lock loops
- Each programmable tile typically includes both programmable
- the programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points ("PIPs").
- PIPs programmable interconnect points
- the programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
- the programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured.
- the configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device.
- the collective states of the individual memory cells then determine the function of the FPGA.
- a CPLD includes two or more "function blocks” connected together and to input/output ("I/O") resources by an interconnect switch matrix.
- Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays ("PLAs”) and Programmable Array Logic (“PAL”) devices.
- PLAs Programmable Logic Arrays
- PAL Programmable Array Logic
- configuration data is typically stored on-chip in non-volatile memory.
- configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
- PLDs programmable logic devices
- the data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
- volatile memory e.g., static memory cells, as in FPGAs and some CPLDs
- non-volatile memory e.g., FLASH memory, as in some CPLDs
- Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device.
- PLDs are known as mask programmable devices.
- PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology.
- PLD and "programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
- one type of PLD includes a combination of hard- coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
- FIG. 1 illustrates an FPGA architecture 100 that includes a large number of different programmable tiles including multi-gigabit transceivers (“MGTs”) 101 , configurable logic blocks (“CLBs”) 102, random access memory blocks (“BRAMs”) 103, input/output blocks (“lOBs”) 104, configuration and clocking logic (“CONFIG/CLOCKS”) 105, digital signal processing blocks (“DSPs”) 106, specialized input/output blocks (“I/O”) 107 (e.g., configuration ports and clock ports), and other programmable logic 108 such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth.
- Some FPGAs also include dedicated processor blocks (“PROC”) 1 10.
- each programmable tile includes a programmable interconnect element ("INT") 1 1 1 having standardized connections to and from a corresponding interconnect element in each adjacent tile. Therefore, the programmable interconnect elements taken together implement the
- programmable interconnect element 1 1 1 also includes the connections to and from the programmable logic element within the same tile, as shown by the examples included at the top of FIG. 1 .
- a BRAM 103 can include a BRAM logic element (“BRL”) 1 13 in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured example, a BRAM tile has the same height as five CLBs, but other numbers (e.g., four) can also be used.
- a DSP tile 106 can include a DSP logic element (“DSPL”) 1 14 in addition to an appropriate number of programmable interconnect elements.
- An IOB 104 can include, for example, two instances of an input/output logic element (“IOL”) 1 15 in addition to one instance of the programmable interconnect element 1 1 1 . As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the I/O logic element 1 15 typically are not confined to the area of the input/output logic element 1 15.
- a horizontal area near the center of the die (shown in FIG. 1 ) is used for configuration, clock, and other control logic.
- Vertical columns 109 extending from this horizontal area or column are used to distribute the clocks and configuration signals across the breadth of the FPGA.
- Some FPGAs utilizing the architecture illustrated in FIG. 1 include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA.
- the additional logic blocks can be programmable blocks and/or dedicated logic.
- processor block 1 10 spans several columns of CLBs and BRAMs.
- FIG. 1 is intended to illustrate only an exemplary FPGA architecture.
- the numbers of logic blocks in a row the relative width of the rows, the number and order of rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and the
- interconnect/logic implementations included at the top of FIG. 1 are purely exemplary.
- more than one adjacent row of CLBs is typically included wherever the CLBs appear, to facilitate the efficient implementation of user logic, but the number of adjacent CLB rows varies with the overall size of the FPGA.
- Masks may be lithographically "stitched" together to make a large die, such as described for stacked-silicon interposer technology.
- lithographic stitching may likewise be used to form a monolithic integrated circuit die, as described below in additional detail.
- the number of ultra-high resolution masks used to make a "supersized” monolithic integrated circuit die may be limited by having stitching performed at the highest metal layers.
- the number of layers used to "stitch" across a mask-field boundary may be substantially reduced by reusing regions of self-contained circuitry ("modular”), which may be separated by scribe line for at least one or more of the initial semiconductor process layers.
- module self-contained circuitry
- a stitched die may have had two complete mask sets for each layer, for example, where there is a top half and a bottom half of a final die.
- the top and bottom halves may be similar, but are different halves of the final die product.
- this may involve a substantial number of ultra-high resolution double patterning masks.
- substantially fewer mask, as well as substantially fewer ultra-high resolution double pattern masks may be used to form a monolithic integrated circuit die.
- fewer of such masks may be stitched together to form such monolithic integrated circuit die.
- a modular monolithic die namely where a larger die is made up of substantially similar and/or identical smaller dies, is a reduction in verification overhead. Verification is a time and resource intensive engineering task. Being able to divide verification into a problem which is a fraction of the size of an overall die, such as one-half or one-third the size for example, can have substantial value in accelerated time to market and reduced cost of engineering infrastructure. Yet another benefit of a modular monolithic die is a reduction in database management. As technology advances, dies are getting larger, and larger and larger dies put increasing strain on the manufacturing process.
- a modular designed monolithic die substantially reduces the data used to manufacture, transmit, and/or simulate a large monolithic device formed of two or more modules, as identical data sets for identical modules means that only one of such data sets may be sent
- FIG. 2 is a block diagram of a top view depicting an exemplary monolithic integrated circuit die ("die") 200 having a die region 21 1 and a die region 212.
- Die regions 21 1 and 212 may each have a same width 223.
- Die region 21 1 may have a length 222, and die region 212 may have a same or different length, namely length 224, than length 222 of die region 212.
- Die 200 may have an overall length 221 , which is a sum or a combination of lengths 222 and 224 respectively of die regions 21 1 and 212.
- width 223 is
- each die region 21 1 and 212 may be within width and length maximum limitations of lithography; however, overall length 221 of die 200 may exceed a maximum limitation of such lithography.
- a maximum limitation of lithography may be 26 mm or 33 mm, where heretofore a monolithic die conventionally did not have one or more dimensions greater than 26 mm and did not have any dimension greater than 33 mm.
- a modular monolithic integrated circuit die formed of a die modules may exceed such present day maximums.
- lengths 222 and 224 are illustratively depicted as being equal, they need not be. For example, an asymmetric rather than a symmetric division may be used. Along those lines, length 222 may be close to 26 mm, and length 221 may be substantially shorter than 26 mm, where die region 212 is used to provide redundancy for die region 21 1 .
- die regions 21 1 and 212 may have equivalent
- die regions 21 1 and 212 are illustratively depicted with same blocks, including without limitation CFG and PCIe blocks, as well as each having a column of I/O blocks ("l/Os") 201 ; however, in other configurations these or other blocks may be used.
- I/Os 201 may include gigabit transceivers ("GTs"). This allows mask sets for forming die regions 21 1 and 212 to be substantially the same, except for one or more upper metal layers, as described below in additional detail.
- GTs gigabit transceivers
- die region 21 1 may be formed with a wall 241 as a part of a die seal, generally indicated as an upward facing "U”
- die region 212 may be formed with another part of a wall 242 of a die seal, generally indicated as a downward facing "U”.
- a die seal of a monolithic integrated circuit die may include a first wall formed in one die region and a second wall formed in an adjacent second die region, where the first wall and the second wall face one another and are connected to one another to provide the die seal of such monolithic integrated circuit die.
- wall ends of such walls 241 and 242 may respectively contact one another to form a perimeter wall or a die seal of die 200.
- Each die region 21 1 and 212 may have a column of l/Os 201 .
- Some of l/Os 201 may be specialized.
- l/Os 201 B may be long range l/Os of l/Os 201 operating with a larger voltage swing than others of such l/Os 201 , and such other l/Os may be high-speed l/Os operating with a smaller voltage swing.
- I/O 201 C may be a configuration I/O, where configuration I/O 201 C of die region 21 1 may be a master block for controlling and/or configuring a slave I/O block 201 of die region 212, as generally indicated by line 203.
- Line 203 interconnects configuration (“CFG") blocks 281 and 282 respectively of die regions 21 1 and 212.
- Line 203 represents a master-to-slave configuration bus. This bus in the past was implemented on an interposer connecting two dies.
- die 200 such interconnection of two independent configurations blocks of separate die regions 21 1 and 212 is done using a layer that is stitched across a mask field boundary, namely mask stitching region 210.
- These interconnections may also include JTAG interconnections.
- JTAG blocks of each die region 21 1 and 212 may be interconnected within die 200.
- die regions 21 1 and 212 may be separately tested at wafer sort, where only a die region currently being tested is powered up.
- die 200 may be sold, though with less functionality than if all die regions were good.
- a partially functional die 200 may be sold.
- both or all die regions had to be powered namely had a common powering-up configuration, and/or had only one JTAG block for testing all die regions, it may not be possible to use only good die regions of a partially functional die 200.
- JTAG blocks in failing die regions need not be used in a packaged part.
- failing die regions in a packaged part need not be powered up.
- Die region 21 1 and die region 212 may be coupled to one another via mask stitching region 210.
- conductors 260 may cross a border between die regions 21 1 and 212, as described below in additional detail.
- mask stitching region 210 may be in a location formerly used for scribe lines on a wafer.
- mask stitching region 210 may be formed with its own mask set.
- each of the mask sets used to form die regions 21 1 and 212 has an extra mask field portion for a respective portion of mask stitching region 210.
- Die region 21 1 has a power distribution network ("PDN"), generally PDN 271
- die region 212 has a PDN, generally PDN 272.
- PDNs 271 and 272 are separate from one another.
- PDN 271 may be separately or independently operated from PDN 272.
- die region 21 1 may be separately powered from die region 212. Accordingly, die region 21 1 may be powered-up and operated while die region 212 is powered-off, and vice versa.
- Having separately powered die regions or die modules allows a monolithic die to be formed having multiple die modules, where the entirety of such monolithic die need not be tested at one time. Rather, each die module may be separately powered up and tested. Additionally, as previously indicated, there are other benefits, such as reduced time to market, reduced engineering overhead, and/or reduced data size for example, to having die modules used to form a monolithic integrated circuit die.
- FIG. 3 is a block diagram of a cross-sectional view depicting an exemplary portion of a monolithic integrated circuit die (“die”) 300, which may be die 200 of FIG. 2. Accordingly, with simultaneous reference to FIGS. 2 and 3, die 300 is further described.
- die monolithic integrated circuit die
- die region 21 1 and die region 212 are each formed with a same set of initial or lower layers 31 1 , and thus a same set of mask sets may be used for such initial layers.
- Upper conductive or metal layers 312, where lithographic limitations may be substantially relaxed as compared with lower layers 31 1 may be used to provide one or more stitching lines, such as stitching lines 301 through 304 for example.
- stitching lines or traces 301 through 304 may represent vertically routed traces or vertical routing.
- Lower layers 31 1 may not have features that extend across mask stitching region 210 for interconnecting die regions 21 1 and 212; however, upper layers 312 may have stitching lines, such as stitching lines 301 through 304 for example, that extend across mask stitching region 210 for interconnection of die regions 21 1 and 212, as described below in additional detail.
- Stitching line 301 extends horizontally across mask stitching region 210 from or to die region 21 1 to or from die region 212.
- conductive lines 321 of a same metal layer as stitching line 301 extend out of the page or orthogonally with respect to a plane of the page.
- conductive lines 322 of a same metal layer as stitching line 303 extend out of the page.
- Conductive lines or traces 321 and 322 in this example may represent horizontally routed traces or horizontal routing. Having a large number of horizontal lines extending from one die region to another die region may be used to increase bandwidth for communication between such die regions.
- Stitching lines 301 through 304 conventionally are "double pitch" lines, namely each stitching line may be twice as wide as a comparably positioned signal line of a same metal layer, and spacing between adjacent stitching lines of a same metal layer may be twice as large as a comparably positioned signal line of such same metal layer.
- stitching lines 301 through 304 may not have contending orthogonal lines within their associated metal layers, which allows for more double pitch lines to be used by having them in more than one metal layer of metal layers 312. By not having perpendicular lines, more sets of parallel stitching lines may be formed to increase bandwidth.
- stitching region 210 may have only horizontal lines running through it. Orthogonal lines, like lines 322 and 321 for example, are not allowed in stitching region 210. Lines 302 and 304 can only carry approximately half the bandwidth through region 210 since they are at approximately twice the pitch ("double pitch") of lines not in stitching region 210.
- bandwidth across stitching region 210 can be increased to that of regions outside of stitching region 210 with respect to other lines for example in layers having lines 302 and 304.
- metal traces may be stitched across a mask field boundary with twice the minimum width and twice the minimum space to bridge such mask field boundary.
- Alternating metal layers may respectively be vertically and horizontally routed.
- such metal layers may be spaced across eight layers with horizontal layers between each of such vertical layers.
- horizontal traces need not be located in mask stitching region 210, and any metal layer may be used for vertically routed traces.
- Lower layers 31 1 including without limitation lower metal layers, that are formed using double patterning need not use stitching. This may reduce mask costs for such masks.
- a mask stitching region 210 may be located in what once was a scribe region. Along those lines, as such scribe region previously did not have any intervening device circuit structures, there may be a significant amount of semiconductor area in which to stitch. Furthermore, even though additional masks may be used to account for differences in modules with respect to stitching layers, uses of a common database for each of such modules may reduce development, verification, and/or test time, as well as reducing database size, in comparison to having one large database covering all circuitry of a large monolithic die.
- FIG. 4 is a block diagram from a top view depicting an exemplary portion of a prior wafer 400 having multiple die regions.
- a die region 401 is separated from a die region 402 by scribe lines of a scribe region 410. Separate dies respectively associated with separate die regions 401 and 402 may be diced or otherwise severed from wafer 400 along scribe lines of scribe regions 410.
- Interconnect lines 41 1 of die region 401 each have a loopback 421 .
- FIG. 5 is a block diagram from a top view depicting an exemplary portion of a wafer 500 having multiple die regions, such as die regions 21 1 and 212 for example. Wafer 500 may include one or more dies 200.
- Die region 21 1 includes a set of select circuits, such as multiplexers 51 1 for example, and die region 212 includes a set of select circuits, such as multiplexers 521 for example.
- die regions 21 1 and 212 may be separately powered, and thus either set of multiplexers may be on while the other set of such multiplexers is off. Furthermore, both sets of multiplexers may be on or off.
- Output conductive lines (“output lines”) 515 of multiplexers 51 1 may extend from output ports of multiplexers 51 1 into die region 21 1 , and such output lines 515 may be interconnect long lines.
- output lines 525 of multiplexers 521 may extend into die region 212, and such output lines 525 may be interconnect long lines, with a couple of respective pairs of input/output lines provided to controller blocks, as described below in additional detail.
- Input conductive lines (“input lines”) 516 of die region 21 1 may extend into mask stitching region 210 for interconnection with input lines 524 of die region 212.
- input lines 526 of die region 212 may extend into mask stitching region 210 for interconnection with input lines 514 of die region 21 1 .
- input lines 514, 516, 524, and 526 may be one or more stitching lines, such as stitching lines 301 through 304 of FIG. 3 for example.
- Input lines 516 may be respectively tapped at nodes 513 for providing data inputs to multiplexers 51 1 .
- Other data inputs to multiplexers 51 1 may be respectively provided from input lines 514.
- Outputs of multiplexers 51 1 may be controllably selected responsive to select signal 512, which may be provided to each of multiplexers 51 1 .
- Select signal 512 may be sourced from a
- input lines 526 may be respectively tapped at nodes 523 for providing data inputs to multiplexers 521 .
- Other data inputs to multiplexers 521 may be respectively provided from input lines 524.
- Outputs of multiplexers 521 may be controllably selected responsive to select signal 522, which may be provided to each of multiplexers 521 .
- Select signal 522 may be sourced from a programmable termination block 527 of die region 212.
- stitching lines that extend from die region 212 to another set of input ports of such select circuits of die region 21 1 , which stitching lines may effectively be tapped and/or routed to another set of input ports of such select circuits of die region 212.
- Die regions 21 1 and 212 may be tested at a wafer level, sometimes referred to as "wafer sort," where good and bad die regions may be identified for each wafer tested. However, die regions 21 1 and 212 may individually be quite complex and have many circuit elements. In other words, die regions 21 1 and 212 may individually draw a significant amount of power during testing.
- wafer sort testers may not be able to power-up all of a die 200.
- such die 200 may be modularly tested by testing die region 21 1 and then testing die region 212.
- die region 212 may be powered down for wafer-level testing of die region 21 1 , the amount of power provided to a wafer for such testing may be substantially reduced.
- die region 21 1 may be powered down for wafer-level testing of die region 212.
- Such modular powering of die regions for testing a die 200 is not limited to wafer-level testing, but may be used after die 200 has been diced from a wafer 500.
- die 200 may be configured such that only signals pass across mask stitching region 210, as power is provided separately to each die region of die regions 21 1 and 212.
- Ground busing may pass across mask stitching region 210.
- die regions may be used to form a die 200.
- Multiple die regions may be used to limit the amount of power to be used for testing each such die region.
- Multiplexers 51 1 are coupled to receive a select signal 512 for selection between a loopback mode for die region 21 1 and a stitch mode for die region 21 1 .
- a loopback mode for die region 21 1 signaling on input lines 516 is selected for output from multiplexers 51 1 responsive to select signal 512.
- a stitch mode for die region 21 1 signaling from die region 212 on input lines 514 is selected for output from multiplexers 51 1 responsive to select signal 512.
- signals on lines 516 input to multiplexers 51 1 are selected for output from such multiplexers 51 1 , wherein such signals on lines 516 are effectively "looped back" into die region 21 1 .
- multiplexers 521 are coupled to receive a select signal 522 for selection between a loopback mode for die region 212 and a stitch mode for die region 212.
- signaling on input lines 526 is selected for output from multiplexers 521 responsive to select signal 522.
- signaling from die region 21 1 on input lines 524 is selected for output from multiplexers 521 responsive to select signal 522.
- signals on lines 526 input to multiplexers 521 are selected for output from such multiplexers 521 , wherein such signals on lines 526 are effectively "looped back" into die region 212.
- die 200 may be sold as a chip though with less functionality than had both die regions 21 1 and 212 passed.
- select signal 522 may be set, such as by fuse or other programming, to select a loopback mode for die region 212.
- die region 21 1 may be set so as to disable it from being powered up, again such as by fuse or other programming.
- a "partials" strategy may be used.
- having more than two die regions may be used for greater granularity in such partials strategy; however, a master die region may be designated among such one or more passing die regions.
- Designating a master die may be performed after modular testing. Selection of a master die may be predetermined; however, during testing any modular die may be temporarily made to appear to be a master, or a slave, for verification and test purposes, which may be useful so as to have a same verification and test procedure for each module.
- die region 21 1 may provide redundancy for die region 21 1 .
- select signals 512 and 522 may each be set, such as by efuse, hard wire, or other programming, to select a stitch mode for their respective die regions.
- FIG. 5 illustratively depicts global select signals for respective die regions, multiple sets of multiplexers and associated select signals may be used for each die region in order to provide greater granularity for supplanting a passing portion of one die region for a failing portion of another die region.
- each of die regions 21 1 and 212 may fail, and redundant passing portions in each of die regions 21 1 and 212 may be used to supplant corresponding failing portions.
- controller e.g., JTAG tap
- JTAG tap JTAG tap
- controller blocks 571 and 572 may each be respectively coupled to an input/output signal pair to and from multiplexers 51 1 and 521 , respectively.
- an output line 515 from a multiplexer 51 1 may be input to controller block 571
- an input line 516 may be output from controller block 571 .
- an output line 525 from a multiplexer 521 may be input to controller block 572, and an input line 526 may be output from controller block 571 . All other lines 515, 516, 525, and 526 may extend to or from their associated region edge.
- a die 200 with programmable termination blocks 517 and 527 respectively in die regions 21 1 and 212 may be used to allow each interconnect, including without limitation each clock input, to provide loop back within an associated die region or to connect to a signal from one die region to another die region on an opposite side of a stitching region of die 200.
- select signals 521 and 522 may propagate at least in part along a metal connection defined by mask layers, where such mask layers are different for different die regions, as described below in additional detail.
- configuration blocks 281 and 282 of FIG. 2 may be used to drive select signals 521 and 522, respectively, in order to allow such signals to be dynamically controlled during test.
- select signals 521 and 522 may be set at power up by efuse values in configuration blocks 281 and 282, respectively. Dynamic control of select signals 521 and 522 may provide flexibility in testing and/or defining a functional die.
- select signals 521 and 522 By having "soft”, as opposed to hard wired connected, select signals 521 and 522, both die regions 21 1 and 212 do not have to be powered up at the same time for testing during wafer sort. Furthermore, by having select signals 521 and 522 as soft signal states set in a configuration controller, such as for example configuration blocks 281 and 282, respectively, each die region 21 1 and 212 may be independently tested during wafer sort and/or partially functional die may be sold where a faulty die region in such die is bypassed in a chip package. In other words, select signals 521 and 522 may be used to isolate or disable a faulty die region from a passing die region. A manufacturer may set an efuse so as to prevent use of a faulty die region, and to set an associated select signal accordingly.
- JTAG may be used for loopback for including or excluding registers in one die region from a scan chain in another die region.
- a circuit design may allow signals which go from one die region to another die region ("stitched signals") to have the possibility of electrically floating or being grounded to allow for an unused condition of a die region.
- inputs to such die region under test may be to gates or to pass gates with floating wells, with appropriate outputs of such die region grounded, to prevent a die region under test from powering a die region not under test through a stitched interface.
- power signals may be sourced from bumps or pins respectively associated with die regions 21 1 and 212, where such bumps or pins are coupled to PDNs 271 and 272. Equalization of power may be performed using power planes of a package substrate holding die 200.
- a portion of stitching or stitched lines 301 through 304 of a stitched interface may be redundant. Along those lines, an extra trace may be used for every some number of traces of such stitched interface. Additionally, multiplexers 51 1 and 521 may include buffers or provide buffering of stitch signals. Along those lines, configuration and JTAG traces crossing a stitched interface may be buffered by controller blocks 571 and/or 572. While JTAG and/or configuration signals may not use loopback, such configuration and JTAG signals may be isolated responsive to die region of a die 200 but still allow for the possibility of interconnection across a stitched interface.
- a JTAG scan chain may involve more than one die region of a die 200, and/or a master-slave association of die regions for configuration control may involve more than one die region of a die 200. Accordingly, multiplexers 51 1 and 521 as described herein may be used for such isolation as well as for such multi-die region interconnection.
- top and bottom termination cells of such blocks may be programmable.
- Each termination top may be at the edge of a "super-sized-monolithic" ("SSM") die 200 or a connection across a stitched boundary 210 to the bottom termination of the other half or portion of an SSM die.
- SSM super-sized-monolithic
- Each termination bottom can be at the edge of an SSM die or a connection across the stitched boundary to the top termination of the other half or portion of an SSM device.
- Control of each halves' or portion's top and bottom termination cell may come from an associated efuse in each of such halves' or portion's respective configuration block or from hard wired connections made using a metal layer in a half or portion thereof.
- steppers used for wafer sort may have limitations in stepping range based on a die being less than maximum width and maximum length or height, such as for example 26x33mm.
- a wafer sort stepper may be used to independently test each die region, such as die regions 21 1 and 212 for example, of an SSM die 200.
- all die regions of an SSM die 200 need not be tested and powered at wafer sort at the same time, but rather die region modular testing may be used.
- FIG. 6 is a block diagram depicting an exemplary layer stack 600, such as for die regions 21 1 and 212 for example.
- layers 601 up to and including an Nth via layer may be the same for both of die regions 21 1 and 212.
- An Nth metal layer 602T for a top die region 212 may be different from an Nth metal layer 602B for a bottom die region 21 1 , and such metal layers 602 may have stitched metal lines, as previously described, across a die region boundary, such as across mask stitching region 210.
- N+1 and N+2 metal layers 604T and 606T for a top die region 212 may be different from corresponding N+1 and N+2 metal layers 604B and 606B for a bottom die region 21 1 , and such metal layers 604 and 606 may each have stitched metal lines.
- Corresponding intervening N+1 and N+2 via layers 603 and 605 may be the same for both die regions 21 1 and 212.
- via redistribution ("RD") layer 607 and metal RD layer 608 may be the same for both die regions 21 1 and 212.
- via masks, even for stitched layers may be the same for die regions 21 1 and 212.
- RD layer 608 namely by having a same bump definition layer, as between die regions, modular testing of each die region with a same or same configuration of a wafer sort probe card may be used.
- Having stitched metal layers at the highest metal layers in a stack may be useful, because: (1 ) higher layer masks may be less expensive to duplicate; (2) higher layers may have more relaxed process integration, design, routing, and/or placement rules which may be more compatible with stitching; (3) higher layers may leave open an option for performing stitching in a different manufacturing facility than used for processing of lower layers; and/or (4) higher layers may have increased ability to visually inspect stitching for initial process development.
- an SSM die 200 does not have twice the number of masks as only some stitching layers may be different between die regions.
- SSM die 200 By subdividing SSM die 200 into manageably sized die regions, range of steps of wafer sort steppers may be within the operating parameters thereof even though overall size of SSM die 200 exceeds a step size of such wafer sort steppers. Moreover, by subdividing into die regions, power, memory, and/or probe point demands during wafer level testing are more manageable. The ability to isolate each die region or section allows for construction of a software- derived die ("SDD") or partially functional die (“partial").
- SDD software- derived die
- partial partially functional die
- FIG. 7 is a bock diagram depicting an exemplary die 200 with three die regions 701 -703 of different sizes.
- die 200 has a mask stitching region 210 for interconnecting die regions 701 and 702 to one another, and another mask stitching region 210 for interconnecting die regions 702 and 703.
- Die regions 701 through 703 may be modularly interconnected or isolated using select circuits and input and output lines, such as previously described with reference to FIG. 5.
- die regions 701 and 703 are the same size, but die region 702 is larger than either die region 701 or 703.
- FIG. 8 is a flow diagram depicting an exemplary wafer-level test flow 800. FIG. 8 is further described with simultaneous reference to FIGS. 2, 3, 5, and 8.
- a die 200 having two or more die regions such as for example a die region 21 1 and a die region 212, is obtained. Again, die regions have separate PDNs for independently operating such die regions.
- die region has separate PDNs for independently operating such die regions.
- 21 1 may be powered up with a PDN 271 , while leaving PDN 272 of die region
- die region 21 1 may be put in a loopback mode responsive to assertion of select signal 512.
- die region 21 1 may be tested while in such a loopback mode.
- die region 21 1 may be powered down.
- die region 212 may be powered up with a PDN 272.
- die region 212 may be put in a loopback mode responsive to assertion of select signal 522.
- die region 212 may be tested while in such a loopback mode.
- die region 212 may be powered down.
- Testing at 804 and 808 may both performed at a wafer level. However, once a die 200 is separated from a wafer 500, die 200 may be tested as a whole die with both of regions powered up and with select signals 512 and 522 asserted to allowing stitching of signals between die regions 21 1 and 212.
- FIG. 9 is a flow diagram depicting an exemplary chip-level test flow 900.
- Chip-level test flow 900 may be performed after wafer-level test flow 800, such as being part of an overall test flow.
- FIG. 9 is further described with
- die regions of a die such as die regions 21 1 and 212 of die 200 for example, are powered up.
- each of die regions 21 1 and 212 is put in a stitch mode.
- die 200 may be tested as a whole, namely tested as a monolithic integrated circuit die, at a chip level.
- die 200 may be powered down.
- test vectors may be reduced, which may save testing time and storage space, as each die region may be independently tested.
- verification time for a design may be reduced with reduced complexity afforded by a modular design, namely simulation time and other complications associated with management of a large design may be reduced by being able to verify individual modules at a time rather than having to verify an entire large monolithic integrated circuit die at the same time.
- the amount of mask definition data may be reduced by use of die regions, as one set of mask definition data for a die region may be repeated for multiple die regions apart from differences in stitching layers. Quality and reliability may likewise be enhanced by use of die regions, as larger more complex designs are more susceptible to unverified or untested regions and modes resulting in latent failures.
- modular die regions have a more manageable size for being more thoroughly verified and tested than non-modular large complex integrated circuit designs.
- modular die regions may be more suitable for characterization models used by PLD design tools.
- An exemplary apparatus described herein relates generally to a monolithic integrated circuit die.
- the monolithic integrated circuit die has a plurality of modular die regions.
- the modular die regions respectively have a plurality of power distribution networks for independently powering each of the modular die regions.
- Each adjacent pair of the modular die regions is stitched together with a respective plurality of metal lines.
- the plurality of modular die regions can includes a first die region and a second die region; the first die region can have a first power distribution network of the plurality of power distribution networks; the second die region can have a second power distribution network of the plurality of power distribution networks; the first power distribution network can be separate from the second power distribution network for operation of the first die region independently from the second die region; the first die region and the second die region can be interconnected to one another through the plurality of metal lines; the first die region can include first select circuits coupled to a first programmable termination block to receive a first select signal; and the second die region can include second select circuits coupled to a second programmable termination block to receive a second select signal.
- the monolithic integrated circuit die can have an overall length which is a combination of a length of the first die region and a length of the second die region; and the overall length can exceed a maximum imaging dimension for a lithographic operation.
- a die seal of the monolithic integrated circuit die can comprise: a first wall formed in the first die region; and a second wall formed in the second die region; wherein the first wall and the second wall face one another and are connected to one another to provide the die seal of the monolithic integrated circuit die.
- a first portion of the plurality of metal lines can extend from the first die region to first input ports of the second select circuits of the second die region; and a second portion of the plurality of metal lines can extend within the second die region to second input ports of the second select circuits of the second die region.
- a third portion of the plurality of metal lines can extend from the second die region to first input ports of the first select circuits of the first die region; and a fourth portion of the plurality of metal lines extend within the first die region to second input ports of the first select circuits of the first die region.
- the first select circuits can be first multiplexers of the first die region; and the second select circuits can be second multiplexers of the second die region.
- the first multiplexers can be coupled to receive the first select signal for selection between a first loopback mode and a first stitch mode for the first die region; and the second multiplexers can be coupled to receive the second select signal for selection between a second loopback mode and a second stitch mode for the second die region.
- the first portion and the third portion of the plurality of metal lines can extend through a mask stitching region between the first die region and the second die region.
- the first programmable termination block and the second programmable termination block can be respectively provided with a first configuration block of the first die region and a second configuration block of the second die region.
- An exemplary method described herein relates generally to a monolithic integrated circuit die.
- an obtained monolithic integrated circuit die has a first die region and a second die region.
- the first die region has a first power distribution network
- the second die region has a second power distribution network.
- the first power distribution network is separate from the second power distribution network for operation of the first die region
- the first die region and the second die region are interconnected to one another through a first plurality of metal lines and a second plurality of metal lines.
- the first plurality of metal lines and the second plurality of metal lines are coupled to a first plurality of select circuits and a second plurality of select circuits.
- the first die region is powered up with the first power distribution network while leaving the second power distribution network of the second die region powered down.
- the first die region is put in a loopback mode.
- the first die region is tested while in the loopback mode.
- the loopback mode is a first loopback mode
- the method can further include powering down the first die region to cease the first loopback mode; powering up the second die region with the second power distribution network; putting the second die region in a second loopback mode; and testing the second die region while in the second loopback mode.
- the testing of the first die region and the testing of the second die region can both be performed at a wafer level.
- Some such methods can include: powering up the first die region and the second die region; putting each of the first die region and the second die region in a stitch mode; and testing the monolithic integrated circuit die.
- the testing of the monolithic integrated circuit die can be performed at a chip level.
- the monolithic integrated circuit die has a first die region and a second die region.
- the first die region has a first power distribution network
- the second die region has a second power distribution network.
- the first power distribution network is separate from the second power distribution network for operation of the first die region
- the first die region and the second die region are interconnected to one another through a first plurality of metal lines and a second plurality of metal lines.
- the first plurality of metal lines and the second plurality of metal lines are coupled to a first plurality of select circuits and a second plurality of select circuits.
- the first die region has a defective portion.
- the second die region is used to provide the monolithic integrated circuit die as a functional die with the defective portion isolated from the second die region.
- the monolithic integrated circuit die can have an overall length which is a combination of a length of the first die region and a length of the second die region; and the overall length can exceed a maximum imaging dimension for a lithographic operation.
- the first plurality of select circuits can be coupled to a first programmable termination block to receive a first select signal; and the second plurality of select circuits can be coupled to a second programmable termination block to receive a second select signal.
- a first portion of the plurality of metal lines can extend from the first die region to first input ports of the second select circuits of the second die region; a second portion of the plurality of metal lines can extend within the second die region to second input ports of the second select circuits of the second die region; a third portion of the plurality of metal lines can extend from the second die region to first input ports of the first select circuits of the first die region; a fourth portion of the plurality of metal lines can extend within the first die region to second input ports of the first select circuits of the first die region; and the first portion and the third portion of the plurality of metal lines can be approximately twice the pitch of the second portion and the fourth portion of the plurality of metal lines.
- the first select signal can be for selection between a first loopback mode and a first stitch mode for the first die region; and the second select signal can be for selection between a second loopback mode and a second stitch mode for the second die region.
Abstract
Description
Claims
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JP2016523730A JP6313436B2 (en) | 2013-07-03 | 2014-04-09 | Monolithic integrated circuit die having modular die regions stitched together |
CN201480037676.6A CN105379122B (en) | 2013-07-03 | 2014-04-09 | Single stone integrated-circuit die with the module grained region being bonded together |
EP14724269.7A EP3017546B1 (en) | 2013-07-03 | 2014-04-09 | Monolithic integrated circuit die having modular die regions stitched together |
KR1020167002971A KR102155402B1 (en) | 2013-07-03 | 2014-04-09 | Monolithic integrated circuit die having modular die regions stitched together |
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US13/935,066 | 2013-07-03 | ||
US13/935,066 US9547034B2 (en) | 2013-07-03 | 2013-07-03 | Monolithic integrated circuit die having modular die regions stitched together |
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