WO2014195806A3 - Methods and systems for insertion of spare wiring structures for improved engineering change orders - Google Patents

Methods and systems for insertion of spare wiring structures for improved engineering change orders Download PDF

Info

Publication number
WO2014195806A3
WO2014195806A3 PCT/IB2014/001914 IB2014001914W WO2014195806A3 WO 2014195806 A3 WO2014195806 A3 WO 2014195806A3 IB 2014001914 W IB2014001914 W IB 2014001914W WO 2014195806 A3 WO2014195806 A3 WO 2014195806A3
Authority
WO
WIPO (PCT)
Prior art keywords
wiring structures
spare wiring
spare
structures
integrated circuit
Prior art date
Application number
PCT/IB2014/001914
Other languages
French (fr)
Other versions
WO2014195806A2 (en
Inventor
Peter Hallschmid
James Cicalo
A.K.M. Kamruzzaman MOLLAH
Original Assignee
Blackcomb Design Automation Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/270,267 external-priority patent/US9236343B2/en
Application filed by Blackcomb Design Automation Inc. filed Critical Blackcomb Design Automation Inc.
Publication of WO2014195806A2 publication Critical patent/WO2014195806A2/en
Publication of WO2014195806A3 publication Critical patent/WO2014195806A3/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/394Routing

Abstract

A method for insertion of spare wiring structures into an integrated circuit comprises determining an architecture of spare wiring structures upon which to base the insertion of spare wiring structures, inserting spare wiring structures into a physical design of the integrated circuit according to the determined architecture, and outputting an engineering-change-order-ready integrated circuit layout. The determined architecture depends upon a design characteristic or design characteristic value. The spare wiring structures include a plurality of spare electrically conductive interconnect layer structures disposed on at least one of a plurality of interconnect layers, which are disposed on one or both sides of a substrate including a plurality of electronic devices. The plurality of interconnect layers include at least one horizontal interconnect layer and at least one vertical- interconnect-access (VIA) layer. The plurality of spare electrically conductive interconnect layer structures are electrically isolated from a plurality of active electrically conductive interconnect layer structures.
PCT/IB2014/001914 2013-06-03 2014-06-03 Methods and systems for insertion of spare wiring structures for improved engineering change orders WO2014195806A2 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201361830556P 2013-06-03 2013-06-03
US61/830,556 2013-06-03
US14/270,267 2014-05-05
US14/270,267 US9236343B2 (en) 2013-05-03 2014-05-05 Architecture of spare wiring structures for improved engineering change orders
US201462006758P 2014-06-02 2014-06-02
US62/006,758 2014-06-02

Publications (2)

Publication Number Publication Date
WO2014195806A2 WO2014195806A2 (en) 2014-12-11
WO2014195806A3 true WO2014195806A3 (en) 2015-04-30

Family

ID=52008657

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2014/001914 WO2014195806A2 (en) 2013-06-03 2014-06-03 Methods and systems for insertion of spare wiring structures for improved engineering change orders

Country Status (1)

Country Link
WO (1) WO2014195806A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015015319A2 (en) * 2013-05-03 2015-02-05 Blackcomb Design Automation Inc. Architecture of spare wiring structures for improved engineering change orders
WO2021252239A1 (en) * 2020-06-08 2021-12-16 The Regents Of The University Of California Integrated-circuit global routing method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4722084A (en) * 1985-10-02 1988-01-26 Itt Corporation Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits
US6753253B1 (en) * 1986-06-18 2004-06-22 Hitachi, Ltd. Method of making wiring and logic corrections on a semiconductor device by use of focused ion beams
US7337103B2 (en) * 2004-01-15 2008-02-26 International Business Machines Corporation Method and apparatus for the automatic correction of faulty wires in a logic simulation hardware emulator / accelerator
US20120047480A1 (en) * 2010-08-17 2012-02-23 Kabushiki Kaisha Toshiba Design method of semiconductor integrated circuit and computer readable medium
US8140942B2 (en) * 2004-10-29 2012-03-20 International Business Machines Corporation System, method and storage medium for providing fault detection and correction in a memory subsystem

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4722084A (en) * 1985-10-02 1988-01-26 Itt Corporation Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits
US6753253B1 (en) * 1986-06-18 2004-06-22 Hitachi, Ltd. Method of making wiring and logic corrections on a semiconductor device by use of focused ion beams
US7337103B2 (en) * 2004-01-15 2008-02-26 International Business Machines Corporation Method and apparatus for the automatic correction of faulty wires in a logic simulation hardware emulator / accelerator
US8140942B2 (en) * 2004-10-29 2012-03-20 International Business Machines Corporation System, method and storage medium for providing fault detection and correction in a memory subsystem
US20120047480A1 (en) * 2010-08-17 2012-02-23 Kabushiki Kaisha Toshiba Design method of semiconductor integrated circuit and computer readable medium

Also Published As

Publication number Publication date
WO2014195806A2 (en) 2014-12-11

Similar Documents

Publication Publication Date Title
WO2015015319A3 (en) Architecture of spare wiring structures for improved engineering change orders
WO2012166451A3 (en) Conductive structures, systems and devices including conductive structures and related methods
WO2015103580A3 (en) Encapsulated conformal electronic systems and devices, and methods of making and using the same
EP3544284A4 (en) Array camera module having height difference, circuit board assembly and manufacturing method therefor, and electronic device
EP2816604A3 (en) Array substrate and organic light-emitting display including the same
EP3799118A3 (en) Ground via clustering for crosstalk mitigation
WO2015047321A8 (en) Previous layer self-aligned via and plug patterning for back end of line (beol) interconnects
WO2014051741A3 (en) Integrated circuits having accessible and inaccessible physically unclonable functions
WO2010145907A3 (en) Methods and systems for fabrication of mems cmos devices
TW200610017A (en) Wiring board, method of manufacturing the same, and semiconductor device
JP2014197181A5 (en)
WO2011103266A3 (en) Shielding structure for transmission lines
JP2016085983A5 (en)
WO2008135596A3 (en) Design tool for the type and form of a circuit production
JP2014131041A5 (en)
WO2009158551A3 (en) Integrated circuit with ribtan interconnects
WO2014139666A8 (en) Electronic sub-assembly, method for the production thereof and printed circuit board having an electronic sub-assembly
WO2011112409A3 (en) Wiring substrate with customization layers
EP2640169A3 (en) Multilayered wiring substrate and electronic apparatus
EP2833388A3 (en) A MEMS Switch Device and Method of Fabrication
MY170809A (en) Information processing device
TW200715525A (en) Semiconductor integrated circuit device and method for manufacturing same
WO2014095316A3 (en) Electronic device and method for producing an electronic device
WO2014195806A3 (en) Methods and systems for insertion of spare wiring structures for improved engineering change orders
WO2012092092A3 (en) A method and apparatus for mounting electronic components on an antenna structure

Legal Events

Date Code Title Description
122 Ep: pct application non-entry in european phase

Ref document number: 14808460

Country of ref document: EP

Kind code of ref document: A2