WO2014155080A1

WO2014155080A1 - Frequency regulator

Info

Publication number: WO2014155080A1
Application number: PCT/GB2014/050926
Authority: WO
Inventors: Peter BRADBEER
Original assignee: Eosemi Limited
Priority date: 2013-03-28
Filing date: 2014-03-25
Publication date: 2014-10-02
Also published as: GB201305771D0

Abstract

According to the invention a monolithically integrated non-oscillatory master frequency regulator for use with at least one slave oscillator, the master frequency regulator including: an arrangement of passive circuit elements having an associated time constant, wherein the arrangement of passive circuit elements is controllable; an input section connectable to a reference frequency source and a slave oscillator wherein the input section is configured to selectively input i) a reference frequency signal or ii) a slave frequency signal from a slave oscillator to the arrangement of passive circuit elements; an output connectable to the slave oscillator; and a control arrangement to control i) the arrangement of adjustable passive circuit elements and ii) the slave oscillator; in which the control arrangement is configured so that i) when the reference frequency signal is input, the control arrangement controls the arrangement of passive circuit elements to achieve a reference set point, and ii) when a slave frequency signal is input, the control arrangement produces a control signal which is outputted via the output to the slave oscillator in order to tune the slave frequency signal produced by the slave oscillator, wherein the control signal is derived from the reference set point.

Description

Frequency Regulator

This invention relates to a frequency regulator, in particular to a master frequency regulator, associated slave oscillators, and to methods of operating same.

The most common frequency regulator device used in electronic products is the quartz crystal. It is a resonator to which an oscillator is connected, and to which it provides a stable frequency reference. The reference quantity exploited is the 'designed-in' mechanical resonance frequency which is determined by the shape, the axis of cutting and the mechanical dimensions of a mounted quartz crystal. The principal difficulties with such a device are its relatively large size, its relatively high unit cost, its bulky hermetically sealed package and its lack of programmability; in addition it is a passive device that is very sensitive to noise and parasitic loading on its terminals due to proximal PCB tracks. This gives rise to design challenges.

Complex consumer products such as mobile phones, tablets and laptop computers have requirements for multiple clock reference frequencies and currently require a multitude of crystals.

By contrast, for IC (integrated circuit) technology both cost and size are reducing continuously over time bringing down the cost per function and consequently there is a strong desire to integrate some form of timing reference which can overcome the drawbacks of quartz crystals.

There is a clear market need to reduce the number of quartz crystals required for a system such as a mobile phone or tablet device. There is also a clear market need to reduce power consumption within the clock generation and distribution parts of current and future systems.

The main challenges when implementing an all-silicon integrated circuit reference are the stability of frequency over temperature, stress and aging: i.e. "stability". This is the main benefit the quartz crystal promises, though even here quartz is not ideal. Its main commercial drawback is that it must forever remain a separate, external component to the integrated circuit it serves and can never be integrated into the integrated circuit itself.

Frequently a system will require multiple frequency references. Often, to avoid using several crystals, such systems will use a system of frequency synthesisers (or fractional-N phase-locked loops, PLLs) linked to a primary reference to deliver the frequencies needed. Such PLLs draw large currents and in systems such as mobile phones can be a drain on valuable battery charge. This is usually because of the use of a high-frequency ring oscillator or LC oscillator and a frequency divider. In such cases, it is the performance of the LC oscillator rather than the crystal oscillator that is of primary relevance. Here, only the so called close-in (near to carrier frequency) phase-noise is attenuated effectively by the crystal because the PLL loop filter will of necessity have limited bandwidth.

Alternative resonators are known which are based on ceramic materials or MEMS (micro electro-mechanical systems). These would include a reference oscillator circuit. This oscillator is expected to deliver a precise frequency to which an integrated high-frequency system oscillator can be "locked" (via PLL) to maintain frequency stability. The internal oscillator must deliver a signal integrity suitable to the system it serves, e.g. needs to have good enough jitter or phase noise performance.

All such alternative resonators, like crystal, present integration problems, and the system oscillator/PLL still consumes large current as a result of its means of operation.

The ideal situation would be where: a reliable frequency reference integrates economically alongside the system oscillator(s) without the need for any external reference oscillator components; the frequency reference can be used to maintain frequency stability in multiple system oscillators; and the system oscillator(s) can deliver a frequency of choice without consuming large currents.

The present invention, in at least some of its embodiments, addresses the above described problems and desires.

According to a first aspect of the invention there is provided a monolithically integrated non-oscillatory master frequency regulator for use with at least one slave oscillator, the master frequency regulator including:

an arrangement of passive circuit elements having an associated time constant, wherein the arrangement of passive circuit elements is controllable; an input section connectable to a frequency reference source and slave oscillator wherein the input section is configured to selectively input i) a reference frequency signal or ii) a slave frequency signal from a slave oscillator to the arrangement of passive circuit elements; an output connectable to the slave oscillator; and

a control arrangement to control i) the arrangement of adjustable passive circuit elements and ii) the slave oscillator;

in which the control arrangement is configured so that i) when the reference frequency signal is input, the control arrangement controls the arrangement of passive circuit elements to achieve a reference set point, and ii) when a slave frequency signal is input, the control arrangement produces a control signal which is outputted to the slave oscillator via the output in order to tune the slave frequency signal produced by the slave oscillator, wherein the control signal is derived from the reference set point.

The inputting of the reference frequency signal to achieve the reference set point only requires a reference frequency source to be connected to the frequency regulator for a limited time. This might be at the time of manufacture. Further calibrations with a reference frequency source may not be necessary.

Generally, the frequency regulation is provided as part of an integrated circuit.

The arrangement of passive circuit elements may include a bridge circuit. The reference set point achieved by adjusting the adjustable passive circuit element may correspond to a balancing of the bridge circuit. In some embodiments, the control arrangement includes a comparator which compares the outputs of different parts of the bridge circuit. Generally, the arrangement of passive circuit elements has an associated RC, RL, or LC time constant.

The control arrangement may control the arrangement of passive circuit elements by controlling at least one controllable passive circuit element. The control arrangement may control the controllable passive circuit element to control the time constant.

Advantageously, the controllable passive circuit element is a frequency- controlled variable resistor (FCVR). Systems incorporating FCVR are described in Mijuskovic et al 1994, IEEE ISSC, Vol.29, No.3, pp271 -279 and Vlswanathan et al IEEE JSFC, 1982, Vol. SC-17, pp776-778, the entire contents of which are herein incorporated by reference. However, neither of these documents suggests that a FCVR might be utilised in a master frequency regulator in accordance with the present invention.

The control signal may be a serial data signal, a N-bit data word, an analog signal or any other suitable signal. The frequency regulator may tune the frequency of the slave frequency signal to the frequency of the reference frequency signal. In these embodiments, the control signal outputted to the slave oscillator may be related to a numerical relationship (typically the difference) between the slave frequency and the frequency associated with the reference set point.

Alternatively, the frequency regulator may tune the frequency of the slave frequency signal to a tuning frequency which is different to the frequency of the reference frequency signal. In these embodiments, a tuning set point may be determined which is different to the reference set point, the difference being functionally related to a numerical relationship between the tuning frequency and the reference frequency. Typically, the numerical relationship is the ratio of the tuning frequency to the reference frequency, or a quantity functionally related thereto. The control signal outputted to the slave oscillator may be related to a numerical relationship (typically the difference) between the slave frequency and the frequency associated with the tuning set point. The skilled reader will readily appreciate that the frequency associated with the tuning set point is the tuning frequency.

Generally, the control signal varies with respect to time as the frequency of the slave oscillator is tuned to the frequency of the reference signal or to the tuning frequency. The control signal may vary as part of a successive approximation algorithm and may settle to a value which is dictated by the reference set point or the tuning set point, as the case may be. Other ways of varying the control signal for this purpose may be contemplated.

Numerous embodiments of the invention are possible which make the setting of the tuning set point highly convenient. The arrangement of passive circuit elements may be implemented so that there is a substantially linear relationship between the tuning frequency associated with the tuning set point and a control signal provided by the control arrangement to control the arrangement of adjustable passive circuit elements. In embodiments in which the arrangement of passive circuit elements includes a bridge circuit, the tuning set point may correspond to a frequency at which the bridge circuit balances. This frequency may be substantially linearly adjusted with a substantially linear adjustment of the control signal inputted to the bridge from the control arrangement. Embodiments in which the arrangement of passive circuit elements includes a FCVR which is controlled by the control arrangement are advantageous, because a FCVR may be easily controlled with a substantially linear relationship between the control signal and the frequency produced by the FCVR. In embodiments in which the FCVR is controlled using a digital control word, the reference frequency can be adjusted to a different tuning frequency by a simple linear adjustment to the value of the digital control word. The desirable property of a substantially linear relationship between the frequency at which the bridge circuit balances and the control signal provided by the control arrangement to the arrangement of passive circuit elements may be achieved in other ways. For example, the value of a reference resistor in the bridge circuit may be programmable. Alternatively, the voltage at a reference node may be adjusted linearly. This may be achieved by using linearly programmable resistors in the bridge circuit or by different means such as the output of a high-resolution DAC whose input value is linearly adjusted.

In some embodiments, the control arrangement may include a data converter which produces at least one of i) a signal which is used to control the arrangement of passive circuit elements to achieve the reference set point and ii) the control signal which is outputted to the slave oscillator.

Typically, the control arrangement includes at least one control element which: i) arranges for the control arrangement to control the arrangement of passive circuit elements when a reference frequency source is connected to the input section; and ii) arranges for the control arrangement to produce the control signal which is outputted via the output when a slave oscillator is connected to the input section.

The control arrangement may be implemented using digital techniques. Alternatively, the control arrangement may be implemented using analog techniques. The skilled reader will appreciate that digital or analog implementation can be achieved in many ways. For example, the output of the data converter could drive a digital-to-analog converter (DAC). The output of the DAC may be used to control the arrangement of passive circuit elements. The arrangement of passive circuit elements may include an analog-controlled capacitor (varactor) which is controlled by the output of the DAC. In other analog embodiments, the output of a low pass filter may be used to control a varactor or other element in the arrangement of passive circuit elements.

According to a second aspect of the invention there is provided a monolithically integrated slave oscillator for use with a master frequency regulator including:

an input connectable to the master frequency regulator for receiving a control signal therefrom;

an output connectable to the master frequency regulator to send a slave frequency signal thereto;

a controllable electronic oscillator for producing the slave frequency signal or a signal functionally related thereto; and a slave control arrangement in connection to the input so as to receive the control signal from the master frequency regulator, wherein the slave control management controls the frequency of the controllable electronic oscillator in response to the control signal so as to tune the slave frequency signal to a frequency associated with the master frequency regulator.

The slave control arrangement may include an arrangement of passive circuit elements having an associated time constant, wherein the arrangement of passive circuit elements is controllable in response to the control signal. The arrangement of passive circuit elements may include a bridge circuit, wherein a state of the bridge circuit is used to control the controllable electronic oscillator. Typically, the slave control arrangement operates to control the frequency of the controllable electronic oscillator such that it maintains a state of electrical balance in the bridge circuit.

The control signal from the master frequency may control at least one passive circuit element. The passive circuit element controlled by the control signal from the master frequency regulator may be a frequency-controlled variable resistor (FCVR).

According to a third aspect of the invention there is provided an oscillator system including a monolithically integrated master frequency regulator according to the first aspect of the invention and at least one monolithically integrated slave oscillator according to the second aspect of the invention which is connected or connectable to the master frequency regulator. The master frequency regulator and at least one slave oscillator may be integrated on a common integrated circuit.

Alternatively (or additionally) the master frequency regulator and at least one slave oscillator may be integrated on separate integrated circuits.

According to a fourth aspect of the invention there is provided a method of calibrating a master frequency regulator including the steps of:

providing a master frequency regulator according to the first aspect of the invention;

connecting the input section to a reference frequency source so that the input section receives a reference frequency signal and inputs said reference frequency signal to the arrangement of passive circuit elements;

using the control arrangement to control the arrangement of passive circuit elements to achieve a reference set point;

disconnecting the reference frequency source from the input section; and subsequently maintaining the reference set point to enable the control arrangement to produce a control signal for controlling a slave oscillator.

According to a fifth aspect of the invention there is provided a method of tuning the frequency of at least one slave oscillator including the steps of:

(a) providing a master frequency regulator according to the first aspect of the invention and at least one slave oscillator according to the second aspect of the invention.

(b) connecting the input section of the master frequency regulator to the output of a slave oscillator so that the input section receives a slave frequency signal and inputs said slave frequency signal to the arrangement of passive circuit elements;

(c) connecting the output of the master frequency regulator to the input of the slave oscillator;

(d) using the control arrangement to produce a control signal which is derived from the reference set point and the response of the arrangement of passive circuit elements to the slave frequency signal;

(e) outputting the control signal from the output of the master frequency regulator to the input of the slave oscillator so that the slave control arrangement receives the control signal; and

(f) using the slave control arrangement to control the frequency of the controllable electronic oscillator in response to the control signal;

steps (d) - (f) being performed until the slave frequency signal is tuned to a frequency associated with the master frequency regulator.

The method may include the further steps of (g) disconnecting the input section of the master frequency regulator from the output of the slave oscillator and (h) disconnecting the output of the master frequency regulator from the input of the slave oscillator.

The invention describes a frequency regulator that can be integrated into a silicon IC and that can offer significantly improved stability over existing solutions. The frequency regulator does not need to include an oscillator, and does not need to meet any specific jitter or phase noise specifications. Its role is to regulate the frequency of one or more local oscillators. Such local oscillators can be of various implementations based on known techniques, but offer a means of tuning using either analog or digital techniques.

Whilst the invention has been described above, it extends to any inventive combination of the features set out above, or in the following description, drawings or claims. For example, features described above in relation to one aspect of the invention may be incorporated with features described in relation to another aspect of the invention.

Embodiments of frequency regulators and slave oscillators in accordance with the invention will now be described with reference to the accompanying drawings, in which:-

Figure 1 is a schematic diagram of a master frequency regulator of the invention; and

Figure 2 is a schematic diagram of a slave oscillator of the invention. Generally, the invention uses a combination of two passive circuit elements which when combined provide a timing reference or time-constant according to known techniques. Passive elements are chosen as they are the most reliable means of delivering stable references in an integrated circuit, though they are not perfect: their characteristics will vary with temperature, stress and age. Techniques for correcting such variations are know to the skilled reader, and may be used in conjunction with devices of the present invention. Typically in an integrated circuit such elements will be RC (resistor-capacitor), RL (resistor-inductor) and LC (inductor- capacitor). However any method of delivering a time-constant will be relevant to this invention. In the examples provided below, the use of resistor-capacitor (RC) is described, and though the invention is not limited to RC.

The present invention can deliver a monolithically integrated frequency regulator whose natural frequency is variable and can be calibrated extremely accurately against a reference clock. Furthermore, the frequency regulator can thereafter be used to calibrate a target oscillator or another frequency reference either continuously or periodically to suit the needs of a particular application. The frequency regulator does not itself contain any oscillator.

Calibrating the frequency regulator:

Figure 1 shows a frequency regulator of the invention, depicted generally at 10. Its basic operational function is to initially calibrate to a known frequency F_cai and then subsequently observe and "check" any frequency F_osc having been calibrated.

The system is a Frequency Locked Loop (FLL) as is known in the art, at the heart of which is a Bridge circuit 12 incorporating two nodes a "Ref Node" 14 and "Sense Node" 16. A control loop including a high gain path operates to equalise these voltages by varying the voltage on the Sense Node. In the example provided in Figure 1 , this is done by varying the value of a frequency-controlled variable resistor FCVR 18. The FCVR 18 could be a frequency-controlled switched capacitor similar to those known in the art, wherein the capacitor might be further programmable using a binary-weighted array of capacitor segments to allow for variable digital value control which is also known in the art. The FCVR 18 could also be implemented using other known means. A switched capacitor pair technique which may be employed in the present invention is described in the applicant's co-pending UK patent application entitled Ά controllable passive circuit element', filed on 28 March 2013, the entire contents of which are herein incorporated by reference. Other techniques may be employed instead.

A successive approximation control sequence is delivered by the SAR (Successive approximation register) data converter 20 to the FCVR 18, whose value is adjusted accordingly. The FCVR 18 is switched using Fcai via a non-overlapping clock generator NOCG 22. An amplifier 24, low- pass filter (LPF) 26 and comparator arrangement 28 senses the difference in voltage between the "Sense node" 26 and "Ref node" 14 and delivers a logic signal back to the SAR converter that determines the next control code in the sequence. The SAR control code length determines the resolution of calibration. The SAR control sequence is delivered to FCVR control logic 30 during this calibration sequence, eg, when a switch 32 is closed.

The calibration sequence is complete once all bits within the FCVR control word are set. At this point the Bridge is deemed to be "balanced". The resulting code is stored in the FCVR control logic 30. The combination of a resistor 34 R_ref and FCVR capacitor 18 value setting comprises the "RC" time constant, which is not only stable but now calibrated precisely against an external reference frequency F_cai.

Calibration time is very short, limited only by the stabilisation of the

SAR algorithm and loop settling time.

The functions supporting the balancing of the Bridge (e.g. comparator 28, SAR converter 20, FCVR control 30 and FCVR 18) may equally be implemented using analog techniques. For example the SAR output could drive a digital-to-analog converter which could be used to directly control an input to an analog-controlled FCVR capacitor value (varactor). Alternatively, the output of the LPF 26 could be used as an analog output to the frequency regulator instead of the digital SAR output.

Fcai is any external timing reference of known frequency. This reference may be presented once at manufacture time by instrumentation, or it may be available in the field as a clock from another part of the system in which the frequency regulator resides. This reference may be available from time to time, allowing for multiple calibration cycles. The skilled reader will appreciate that the reference frequency need only be present for a limited time in order to calibrate the frequency regulator.

Post-Calibration Selection of Desired Regulation Frequency:

The FCVR 18 can be constructed to have a very linear relationship between its control input and its resulting value. It is a benefit of the invention that the frequency of F_cai (or F_osc) at which the Bridge balances can be simply adjusted with a linear adjustment of the FCVR control. In the case where the FCVR control is a digital control word, this adjustment is a simple numerical adjustment. So by simply making a linear adjustment to the value of the FCVR 18 control code, it is possible to impose a corresponding scaling of the frequency that balances the Bridge circuit 12. This effectively means that the frequency regulator can regulate other devices by tuning them to a different frequency (henceforth, the Regulation Frequency) than the frequency that the frequency regulator was calibrated at.

This is not the only means by which the Regulation Frequency can be adjusted. It is feasible that the value of the resistor R_ref be programmable, and that any adjustment to its value would have a corresponding effect on the Regulation Frequency according to a linear relationship. Alternatively, the voltage at "Ref Node" 14 could be adjusted linearly, either by replacing the resistors in the bridge illustrated in Figure 1 with linearly programmable equivalents or by generating the Ref Node voltage through a completely different means, such as a high-resolution digital-to-analog converter (DAC) output whose input value is linearly adjusted. All of these techniques would provide a means of linearly adjusting the Regulation Frequency.

It will be apparent that the present invention can provide a monolithically integrated master frequency regulator having a means to be calibrated for loop balance at a calibration frequency F_cai and which loop balance means can thereafter be numerically varied ("tuned") such that an input frequency F_osc gives rise to loop balance at a Regulation Frequency which is different to the calibration frequency.

The frequency regulator 10 can now be used to regulate a variety of frequencies of other oscillators. These oscillators can be on-chip, or can be remote (e.g. on another chip).

Using the Frequency Regulator to Tune an Oscillator:

Once calibrated, the master frequency regulator 10 can be deployed to monitor and correct the frequency of oscillators in the system. Figure 2 illustrates a deployment of the frequency regulator in such a mode, where a frequency regulator including a master loop is used to control one or more oscillator circuits including slave loops.

Now a calibration value is established for the FCVR value control, balance of the master bridge circuit in the frequency regulator is dependent on the correct frequency being applied at the input F_0Sc, i.e. a frequency that matches the original F_cai. (in this example, no adjustment is made to the FCVR control after calibration).

The oscillator being controlled can be any oscillator in the system that is capable of having its frequency varied. It might have digital or analog frequency control. An example of such a control loop is shown in Figure 2, which shows a slave oscillator 40 in connection with a master frequency regulator 42. The master frequency regulator 42 is identical to the master frequency regulator 10 shown in Figure 1 . For ease of presentation, the international components of the master frequency regulator 42 are not shown in Figure 2 except to denote the master control loop generally at 44. The slave oscillator 40 has a slave loop comprising a controlled oscillator 46 and a slave bridge 48.

Figure 2 shows a digital master/slave control system, where by connecting the master SAR output 50 to the slave FCVR control 52, and by connecting the slave oscillator output 54 to the F_osc input of the master frequency regulator, a feedback loop involving the master loop and the slave loop is completed wherein balance of the master bridge can only be achieved when the controlled oscillator frequency matches the frequency needed to balance the master bridge. Thus the slave loop becomes regulated according to the original calibration of the master loop in the frequency regulator. It will be appreciated that the arrangement shown in Figure 2 can be readily adapted to provide a combination of a monolithically integrated master frequency regulator with any of a plurality of slave oscillators wherein the frequency of the target slave oscillator F_osc can be tuned to the calibrated frequency of the master frequency regulator. The master SAR output 50 can be connected to the slave FCVR control 52 by closing the switch 56 or through other logic means.

Further, because the frequency needed to balance the master frequency regulator can be simply changed with, for example, a numerical scale factor, so each slave oscillator can be regulated to a different frequency.

Furtherstill, it is possible to provide a combination of a monolithically integrated master frequency regulator with any of a plurality slave Oscillators wherein the frequency of the target slave oscillator F_osc can be selected and regulated by numerically adjusting tuning of the master frequency regulator.

Just as the master loop can be adjusted with a different numerical scale factor to allow for choice or variety in the reference frequency and subsequent oscillator frequency, so the slave loop can equally have its natural frequency adjusted after regulation. With this facility, the slave oscillator can be numerically adjusted according to prescribed increments or to deliver a specific new frequency without the need for further regulation by the master regulator.

The control loop illustrated in Figure 2 is not the only possible configuration. For example the slave FCVR control input signal (here illustrated as being an SAR output) could equally be the binary output of the comparator, could be an analog signal from the amplifier of LPF or could be conveyed in another suitable means, e.g. one of the above control signals modulating a carrier signal.

Claims

1 . A monolithically integrated non-oscillatory master frequency regulator for use with at least one slave oscillator, the master frequency regulator including: an arrangement of passive circuit elements having an associated time constant, wherein the arrangement of passive circuit elements is controllable; an input section connectable to a reference frequency source and a slave oscillator wherein the input section is configured to selectively input i) a reference frequency signal or ii) a slave frequency signal from a slave oscillator to the arrangement of passive circuit elements;

an output connectable to the slave oscillator; and

in which the control arrangement is configured so that i) when the reference frequency signal is input, the control arrangement controls the arrangement of passive circuit elements to achieve a reference set point, and ii) when a slave frequency signal is input, the control arrangement produces a control signal which is outputted via the output to the slave oscillator in order to tune the slave frequency signal produced by the slave oscillator, wherein the control signal is derived from the reference set point.

2. A frequency regulator according to claim 1 in which the arrangement of passive circuit elements includes a bridge circuit.

3. A frequency regulator according to claim 2 in which the set point achieved by adjusting the adjustable passive circuit elements corresponds to a balancing of the bridge circuit.

4. A frequency regulator according to claim 3 in which the control arrangement includes a comparator which compares the outputs of different parts of the bridge circuit.

5. A frequency regulator according to any previous claim in which the control arrangement includes a frequency-locked loop.

6. A frequency regulator according to any one of claims 1 to 5 in which the arrangement of passive circuit elements has an associated RC, RL, or LC time constant.

7. A frequency regulator according to any previous claim in which the control arrangement controls the arrangement of passive circuit elements by controlling at least one controllable passive circuit element.

8. A frequency regulator according to claim 7 in which the control arrangement controls the controllable passive circuit element to control the time constant.

9. A frequency regulator according to claim 7 or claim 8 in which the controllable passive circuit element is a frequency-controlled variable resistor.

10. A frequency regulator according to any previous claim for tuning the frequency of the slave frequency signal to the frequency of the reference frequency signal, in which the control signal outputted to the slave oscillator is related to a numerical relationship between the slave frequency and the frequency associated with the reference set point.

1 1 . A frequency regulator according to any one of claims 1 to 9 for tuning the frequency of the slave frequency signal to a tuning frequency which is different to the frequency of the reference frequency signal, in which a tuning set point is determined which is different to the reference set point, the difference being functionally related to a numerical relationship between the tuning frequency and the reference frequency; and the control signal outputted to the slave oscillator is related to a numerical relationship between the slave frequency and the frequency associated with the tuning set point.

12. A frequency regulator according to claim 10 or 1 1 in which the control signal is varied as part of a successive approximation algorithm.

13. A frequency regulator according to any previous claim in which the control arrangement includes a data converter which produces at least one of i) the control signal which is outputted to the slave oscillator and ii) a signal which is used to control the arrangement of passive circuit elements to achieve the reference set point.

14. A frequency regulator according to any previous claim in which the control arrangement includes at least one control element which: i) arranges for the control arrangement to control the arrangement of passive circuit elements when a reference source is connected to the input section; and ii) arranges for the control arrangement to produce the control signal which is outputted via the output when a slave oscillator is connected to the input section.

15. A monolithically integrated slave oscillator for use with a master frequency regulator including:

a controllable electronic oscillator for producing the slave frequency signal or a signal functionally related thereto; and

a slave control arrangement in connection to the input so as to receive the control signal from the master frequency regulator, wherein the slave control arrangement controls the frequency of the controllable electronic oscillator in response to the control signal so as to tune the slave frequency signal to a frequency associated with the master frequency regulator.

16. A slave oscillator according to claim 15 in which the slave control arrangement includes an arrangement of passive circuit elements having an associated time constant, wherein the arrangement of passive circuit elements is controllable in response to the control signal.

17. A slave oscillator according to claim 16 in which the arrangement of passive circuit elements includes a bridge circuit, wherein a state of the bridge circuit is used to control the controllable electronic oscillator.

18. A slave oscillator according to claim 16 or claim 17 in which the control signal from the master frequency regulator controls at least one passive circuit element.

19. A slave oscillator according to claim 18 in which the passive circuit element controlled by the control signal from the master frequency regulator is a frequency-controlled variable resistor.

20. An oscillator system including a monolithically integrated master frequency regulator according to claim 1 and at least one monolithically integrated slave oscillator according to claim 15 which is connected or connectable to the master frequency regulator.

21 . An oscillator system according to claim 20 in which the master frequency regulator and at least one slave oscillator are integrated on a common integrated circuit.

22. An oscillator system according to claim 20 in which the master frequency regulator and at least one slave oscillator are integrated on separate integrated circuits.

23. A method of calibrating a master frequency regulator including the steps of:

providing a master frequency regulator according to claim 1 ;

24. A method of tuning the frequency of at least one slave oscillator including the steps of:

(a) providing a master frequency regulator according to claim 1 and at least one slave oscillator according to claim 15;

25. A method according to claim 24 including the further steps of (g) disconnecting the input section of the master frequency regulator from the output of the slave oscillator and (h) disconnecting the output of the master frequency regulator from the input of the slave oscillator.