WO2014153844A1

WO2014153844A1 - Array substrate and display device

Info

Publication number: WO2014153844A1
Application number: PCT/CN2013/076956
Authority: WO
Inventors: 王国磊; 李小和; 马睿; 胡明
Original assignee: 合肥京东方光电科技有限公司; 京东方科技集团股份有限公司
Priority date: 2013-03-29
Filing date: 2013-06-07
Publication date: 2014-10-02
Also published as: CN103235452A; CN103235452B

Abstract

An array substrate and a display device. The array substrate comprises a base substrate. Multiple grid lines and multiple data lines are formed on the base substrate along a first direction and a second direction that intersect, multiple pixel units arranged evenly are further formed thereon, and each pixel unit comprises a thin film transistor, and a pixel electrode and a common electrode for forming an electric field; at least one of the common electrode and the pixel electrode of each pixel unit comprises a slit electrode with a bent slit, a corresponding grid line is disposed at the slit bent position of the slit electrode, sources of the thin film transistors of the adjacent pixel units at two sides of the data line are connected to the same data line, and gates thereof are connected to different grid lines separately.

Description

Array substrate and display device

Embodiments of the present invention relate to an array substrate and a display device. Background technique

With the development of display manufacturing technology, liquid crystal display technology has developed rapidly, and has gradually replaced the traditional picture tube display and become the mainstream of future flat panel displays. In the field of liquid crystal display technology, TFT-LCD (Thin Film Transistor Liquid Crystal Display) is widely used in televisions, computers, etc. due to its large size, high integration, powerful functions, flexible technology, and low cost. Mobile phones and other fields.

ADS (ADvanced Super Dimension Switch, ADSDS, Advanced Super Dimensional Field Conversion Technology, ADS) TFT-LCD has high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, no The advantages of squeezed water ripple (push Mura) are widely used in the field of liquid crystal displays. The ADS type TFT-LCD forms a multi-dimensional electric field by the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer, so that the slit electrode between the liquid crystal cell and the electrode are directly above All oriented liquid crystal molecules are capable of rotating, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency, thereby improving the picture quality of the TFT-LCD product.

In order to increase the aperture ratio and thereby improve the transmittance of the display device, a HADS (High aperture ADS, high aperture ratio - advanced super-dimensional field conversion technology) type TFT-LCD has appeared. Further, in order to shorten the pixel charging time to realize low-cost, high-quality picture display, the display panel of the existing HADS type TFT-LCD generally adopts a dual gate driving method (Dual Gate), wherein the array substrate includes a village substrate. a gate line, a data line, and a plurality of pixel units uniformly arranged on the substrate of the substrate, each of the pixel units including a thin film transistor (TFT), and a pixel electrode (Pixel electrode) and a common electrode (Com) for forming an electric field The pixel electrode and the common electrode are used to drive liquid crystal molecules corresponding to the pixel unit to be deflected; the source of the thin film transistor located in adjacent pixel units on both sides of one data line is connected to the data line (Data line) The gates are respectively connected to different gate lines such that two gate lines are disposed between adjacent pixel units of two rows. The pixel unit of the conventional HADS type TFT-LCD generally has a single domain structure (1-Domain), wherein the direction of the multi-dimensional electric field generated between the pixel electrode and the common electrode in each pixel unit is uniform, so each pixel unit The deflection directions of the corresponding liquid crystal molecules are also uniform. However, liquid crystal molecules have different refractive indices at different viewing angles, and their optical path differences are also different, resulting in different wavelength ranges of transmitted light, which results in different chromaticities of liquid crystal molecules at different viewing angles, that is, color shift phenomenon. . For example, when parallel to the optical axis direction of the liquid crystal molecules, the wavelength of the transmitted light is small, resulting in a bluish phenomenon (Bluish), and when the optical axis is perpendicular to the optical axis of the liquid crystal molecule, the wavelength of the transmitted light is too large, causing a yellowish phenomenon. ( Yellowish ). That is to say, due to the single domain structure, the deflection directions of the liquid crystal molecules corresponding to each pixel unit are uniform, resulting in a serious color shift of the liquid crystal panel. Summary of the invention

One of the technical problems to be solved by the present invention is to provide an array substrate and a display device capable of compensating for color shift and avoiding light leakage in view of the above-described drawbacks in the prior art.

An embodiment of the present invention provides an array substrate including a substrate substrate on which a plurality of gate lines and a plurality of data lines along a first direction and a second direction intersecting each other are formed, and a plurality of pixel units each of which is arranged in a first direction and a second direction, each of the pixel units including a thin film transistor and a pixel electrode and a common electrode for forming an electric field,

Wherein at least one of the common electrode and the pixel electrode of each pixel unit comprises a slit electrode with a slit bent, and a corresponding gate line is disposed at a slit of the slit electrode of the slit electrode, and is located at the data line The sources of the thin film transistors in the adjacent pixel units on both sides are connected to the same data line, and the gates are respectively connected to different gate lines.

In one example, the slit bend of the slit electrode in each pixel unit is located in the middle of the pixel unit.

In one example, as seen in plan view, the pixel electrode of each pixel unit and the common electrode intersect with the corresponding gate line, and the corresponding gate line passes through the middle of the pixel unit.

In one example, the slit electrode includes a plurality of slits intersecting with respective gate lines, and having different extending directions on both sides of the gate line to form a bend at the position of the gate line fold.

In one example, a plurality of slits of the slit electrode in the same pixel unit are disposed in parallel. In one example, two adjacent pixel units in the gate line direction are shifted by half of the length of the pixel unit in a direction perpendicular to the gate line, such that the corresponding gate line passes through the adjacent two pixel sheets. The edge of one pixel unit in the element passes through the middle of the other pixel unit, and the distance between the adjacent two gate lines is equal to half the length of the pixel unit in the direction perpendicular to the gate line.

In one example, the gate line extends in a straight line along the first direction, and the data line extends in a fold line along the second direction.

In one example, the slit electrodes are symmetrical with respect to the gate line in the extending direction of the slits on both sides of the respective gate lines crossing the same.

In one example, the slits of the slit electrodes in the adjacent two pixel units in the gate line direction are bent in opposite directions; the slit electrodes in the adjacent two pixel units in the direction perpendicular to the gate lines The seams are bent in the same direction.

In one example, the array substrate further includes a common electrode line formed on the substrate of the substrate, and the common electrode in each pixel unit is connected to the common electrode line;

The common electrode line and the data line are alternately arranged on the substrate of the village and are parallel to each other;

The pixel electrode and the common electrode in each pixel unit are located between a data line and a common electrode line adjacent to the data line.

In one example, a data line connected to a source of a thin film transistor in each pixel unit, and a common electrode line connected to a common electrode in each pixel unit, and a slit electrode corresponding to a corresponding portion of the pixel unit The slits are parallel.

In one example, the drain of the thin film transistor in each pixel unit is connected to the pixel electrode in the pixel unit;

The array substrate further includes a passivation layer disposed between the common electrode and the pixel electrode.

In one example, the common electrode in each pixel unit is a slit electrode including a bend, and the pixel electrode is a plate electrode;

Or the pixel electrode in each pixel unit is a slit electrode including a bend, and the common electrode is a plate electrode;

Alternatively, the common electrode and the pixel electrode in each of the pixel units are slit electrodes including a bend. Another embodiment of the present invention provides a display device comprising an array substrate according to any of the embodiments of the present invention.

The common electrode and the pixel electrode in each pixel unit on the array substrate in the embodiment of the present invention have at least one slit electrode including a slit bent, so that the common electrode and the pixel in each pixel unit The direction of the electric field formed between the electrodes includes two directions, so that the deflection direction of the liquid crystal molecules corresponding to each pixel unit is also divided into two types, so each pixel unit can be divided into two regions with different viewing angles, effectively compensating The color shift caused by the liquid crystal molecules having only a single deflection direction. A grating line is disposed at a bend of the slit electrode in each pixel unit, which effectively avoids light leakage caused by a dark region formed at a bend of the slit electrode. DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, rather than to the present invention. limit.

1 is a schematic plan view showing the planar structure of the array substrate after the step s101 is completed in the second embodiment of the present invention; FIG. 2 is a schematic diagram showing the planar structure of the array substrate after the step s102 is completed in the second embodiment of the present invention; FIG. 4 is a schematic plan view showing the planar structure of the array substrate after the step s10 is completed in the second embodiment of the present invention; FIG. 5 is a schematic plan view showing the planar structure of the array substrate after the step s105 is completed in the second embodiment of the present invention. detailed description

The technical solutions of the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present invention. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.

In order to enable those skilled in the art to better understand the technical solutions of the present invention, the array substrate and display device of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

Example 1

The embodiment provides an array substrate, comprising a substrate substrate, a plurality of horizontally and vertically interlaced gate lines and a plurality of data lines formed on the substrate substrate, and a plurality of pixel units uniformly arranged, each pixel unit Each includes a thin film transistor, and a pixel electrode and a common electrode for forming an electric field. The plurality of gate lines and the plurality of data lines are not limited to the arrangement of the horizontal and vertical staggered. For example, the plurality of gate lines and the plurality of data lines may extend in a first direction and a second direction that intersect each other in a plane of the substrate. At this time, multiple The pixel units are also arranged in the first direction and the second direction.

Each of the common electrode and the pixel electrode of each pixel unit has at least one slit electrode including a slit bent such that an electric field direction formed between the common electrode and the pixel electrode in each pixel unit includes two directions, thereby The deflection direction of the liquid crystal molecules corresponding to each pixel unit is also divided into two types, and the pixel unit corresponding to the liquid crystal molecules having two deflection directions is divided into two regions with different viewing angles, effectively compensating for only a single deflection direction. Color shift caused by liquid crystal molecules;

A gate line (a gate line corresponding to the pixel unit) is disposed at a slit of the slit electrode in each pixel unit to avoid a dark area formed at a bend of the slit electrode Leakage phenomenon

The sources of the thin film transistors in the pixel cells adjacent to both sides of the data line are connected to the same data line, and the gates are respectively connected to different gate lines (the different gate lines may be adjacent gate lines, also It may be a non-adjacent gate line), that is, the array substrate adopts a double gate driving method.

For example, slit slits of the slit electrodes in each pixel unit are located in the middle of the pixel unit; slits of the slit electrodes in the same pixel unit are disposed in parallel. The electric field distribution in the two directions formed between the common electrode and the pixel electrode in each pixel unit is the same (or almost the same), thereby better compensating for the color shift.

For example, as seen in plan view, the pixel electrode of each pixel unit and the common electrode intersect with the corresponding gate line, and the corresponding gate line passes through the middle of the pixel unit. For example, the slit electrode includes a plurality of slits that intersect the corresponding gate lines and have different extending directions on both sides of the gate lines to form a bend at the position of the gate lines.

For example, the positions of two adjacent pixel units on the substrate substrate in the direction of the gate line are staggered so that the gate lines are straight lines, and the distance between adjacent two gate lines is equal to the pixel unit Half of the length in the direction perpendicular to the gate line, that is, any adjacent two gate lines are equally spaced. In the existing array substrate using the double gate driving method, the gate lines are disposed between adjacent two rows of pixel units, and in this embodiment, each gate line is alternately disposed in the middle of the pixel unit and adjacent rows of pixels. Between the cells, the arrangement of the gate lines in this embodiment increases the aperture ratio as compared with the prior art.

For example, two adjacent pixel units in the gate line direction are shifted by half of the length of the pixel unit in a direction perpendicular to the gate line, such that the corresponding gate line passes through one of the adjacent two pixel units. The edge passes through the middle of the other pixel unit, and the distance between the adjacent two gate lines is equal to half the length of the pixel unit in the direction perpendicular to the gate line. For example, the slits of the slit electrodes in the adjacent two pixel units in the gate line direction are bent in opposite directions; the slits of the slit electrodes in the adjacent two pixel units in the direction perpendicular to the gate lines are bent. The directions are the same so that more pixel units can be arranged on the substrate of the village.

For example, the array substrate further includes a common electrode line formed on the substrate of the substrate, and the common electrode in each pixel unit is connected to the common electrode line; the common electrode line and the data line are alternately arranged on the substrate of the substrate and Parallel to each other; the pixel electrode and the common electrode in each pixel unit are located between a data line and a common electrode line adjacent to the data line. A data line connected to the source of the thin film transistor in each pixel unit, and a common electrode line connected to the common electrode in each pixel unit are parallel to the slit of the slit electrode of the corresponding portion of the pixel unit. The pixel unit adopting such a structure has a higher aperture ratio when arranged on the substrate of the substrate, and is also advantageous for the arrangement of the pixel unit on the substrate substrate.

As can be seen from the above description and Fig. 5, the gate lines extend in a straight line in the first direction, and the data lines extend in the form of a broken line in the second direction. Here, extending in the second direction in the form of a broken line does not mean that each portion of the fold line is strictly in the second direction, but the overall direction of the fold line is along the second direction, and the extending direction of each portion may deviate from the second direction. .

In one example, each of the slit electrodes is symmetrical with respect to the gate line in a direction in which the slits on both sides of the respective gate lines crossing the same.

For example, the drain of the thin film transistor in each pixel unit is connected to the pixel electrode in the pixel unit; the array substrate further includes a passivation layer disposed between the common electrode and the pixel electrode.

For example, the common electrode in each pixel unit is a slit electrode including a bend, and the pixel electrode is a plate electrode;

Alternatively, the common electrode and the pixel electrode in each of the pixel units are slit electrodes including a bend. The embodiment also provides a display device including the above array substrate. The display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any display product or component.

Example 2:

This embodiment provides an array substrate, including a village substrate, which is formed on a substrate substrate. A plurality of staggered gate lines and data lines, a common electrode line, a gate insulating layer, a passivation layer, and a plurality of pixel units uniformly arranged.

Each of the pixel units includes a thin film transistor, and a pixel electrode and a common electrode for forming an electric field; wherein, the common electrode in each pixel unit is a slit electrode including a bend, and the pixel electrode is a plate electrode, a grid line is disposed at a bend of the common electrode (ie, the slit electrode) to prevent light leakage in the dark region formed at the bend, and a bend of the common electrode is located in a middle portion of the pixel unit, that is, The gate lines are located in the middle of the pixel unit; the slits of the common electrodes in the same pixel unit are all arranged in parallel; each thin film transistor includes a gate, a semiconductor layer (also referred to as an active layer), a source and a drain .

The sources of the thin film transistors in the adjacent pixel units on both sides of the same data line are connected to the same data line, and the gates are respectively connected to different two gate lines (two adjacent pixels as shown in FIG. 5) The gate of the cell is connected to the adjacent two gate lines, which is only one of the cases. The drain is connected to the corresponding pixel electrode, that is, the array substrate in this embodiment adopts a double gate driving mode. The positions of two adjacent pixel units on the substrate substrate in the direction of the gate line are staggered so that the gate lines are all straight lines, and the distance between adjacent two gate lines is equal to the pixel unit in the gate Half the length of the line in the vertical direction. The slits of the common electrodes of the adjacent two pixel units in the direction of the gate line are bent in opposite directions; the slits of the common electrodes of the adjacent two pixel units in the direction perpendicular to the gate lines are bent in the same direction.

The common electrode line is connected to a common electrode in each pixel unit for supplying a voltage to the common electrode; the common electrode line and the data line are alternately arranged on the village substrate and parallel to each other; pixels in each pixel unit The electrode and the common electrode are both located between a data line and a common electrode line adjacent to the data line. A data line connected to the source of the thin film transistor in each pixel unit, and a common electrode line connected to the common electrode in each pixel unit are parallel to the slit of the slit electrode of the corresponding portion in the pixel unit.

The gate insulating layer is disposed between the gate of the thin film transistor and the semiconductor layer in each pixel unit, and the passivation layer is disposed between the common electrode and the pixel electrode to function as an insulating layer.

The embodiment also provides a display device including the above array substrate. The display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any display product or component.

The method for fabricating the array substrate of the present embodiment will be described in detail below with reference to FIGS. Although A plurality of pixel units arranged in a row are formed on the array substrate of the embodiment, but for convenience of description and understanding, only one case of the structure of two adjacent pixel units is shown in FIGS. Further, in order to facilitate observation of the respective layer patterns, the pixel electrode 8 and the common electrode 9 in the drawing are subjected to translucent processing.

The method comprises the following steps:

slOO. Provides a village base substrate.

The substrate of the village should be cleaned and free of dust and impurity ions. The substrate substrate may be a transparent substrate such as a glass substrate, a quartz substrate, or a plastic substrate.

slOl. As shown in Fig. 1, a pattern of a gate electrode 1 and a gate line 2 are formed on a substrate (not shown) by a patterning process, and the gate electrode 1 is connected to a corresponding gate line 2.

Sl02. As shown in FIG. 2, a gate insulating layer (not shown) and a pattern of the semiconductor layer 3 are sequentially formed on the substrate substrate of the step s101 by a patterning process, and the gate insulating layer is completely covered. The substrate substrate of the step s101 is thus also covered on the gate 1 and the gate line 2, and the semiconductor layer 3 is disposed directly above the corresponding gate 1.

Sl03. As shown in FIG. 3, a pattern of the source electrode 4, the drain electrode 5, the data line 6, and the common electrode line 7 is formed on the substrate substrate of the step S102 by a patterning process, and the source electrode 4 and the drain electrode 5 are respectively Connected to the semiconductor layer 3, and a channel is formed between the source 4 and the drain 5, and the source 4 is connected to the corresponding data line 6.

Step s102 and step s03 can be performed by using a common mask technique and using two patterning processes, or a two-tone mask (such as a half Tone mask or a Gray Tone Mask). The technology is completed in a patterning process.

Sl04. As shown in Fig. 4, a pattern of the plate-like pixel electrode 8 is formed on the substrate of the substrate at step sl03 by a patterning process, and the pixel electrode 8 is connected to the corresponding drain 5.

Sl05. As shown in FIG. 5, a pattern of a passivation layer (not shown) and a common electrode 9 (ie, a slit electrode) are sequentially formed on the substrate of the substrate at step S104 by a patterning process, the passivation layer It is completely covered on the substrate substrate on which the step S104 is completed, and a via hole for connecting the common electrode 9 and the common electrode line 7 is formed on the passivation layer.

Other structures and functions in this embodiment are the same as those in Embodiment 1, and are not described herein again. The patterning process described above generally includes a process of photoresist coating, exposure, development, etching, photoresist stripping, and the like. The above is only the exemplary embodiments of the present invention, and is not intended to limit the scope of the invention. The scope of the invention is determined by the appended claims.

Claims

Claim

An array substrate comprising a substrate substrate, wherein the substrate substrate is formed with a plurality of gate lines and a plurality of data lines along a first direction and a second direction crossing each other, and along the first direction a plurality of pixel units uniformly arranged in the second direction, each of the pixel units including a thin film transistor and a pixel electrode and a common electrode for forming an electric field,

2. The array substrate according to claim 1, wherein

The slit bend of the slit electrode in each pixel unit is located at the middle of the pixel unit.

3. The array substrate according to claim 2, wherein

As seen in plan view, the pixel electrode and the common electrode of each pixel unit intersect with the corresponding gate line, and the corresponding gate line passes through the middle of the pixel unit.

The array substrate according to any one of claims 1 to 3, wherein

The slit electrode includes a plurality of slits that intersect the corresponding gate lines and have different extending directions on both sides of the gate lines to form a bend at the position of the gate lines.

The array substrate according to any one of claims 1 to 4, wherein a plurality of slits of the slit electrode in the same pixel unit are disposed in parallel.

6. The array substrate according to claim 2, wherein

Two adjacent pixel units in the gate line direction are shifted by half of the length of the pixel unit in a direction perpendicular to the gate line such that the corresponding gate line passes through an edge of one of the adjacent two pixel units Passing through the middle of another pixel unit, and the distance between adjacent two gate lines is equal to half the length of the pixel unit in a direction perpendicular to the gate line.

7. The array substrate according to claim 6, wherein

The gate line extends in a straight line along the first direction, and the data line extends in a fold line along the second direction.

The array substrate according to claim 4, wherein The slit electrode is symmetric with respect to the gate line in a direction in which the slits on both sides of the corresponding gate line intersecting therewith.

The array substrate according to any one of claims 1 to 8, wherein

The slits of the slit electrodes in the adjacent two pixel units in the gate line direction are bent in opposite directions; the slit electrodes in the adjacent two pixel units in the direction perpendicular to the gate lines are bent in the same direction .

The array substrate according to any one of claims 1 to 9, wherein

The array substrate further includes a common electrode line formed on the substrate of the substrate, and the common electrode in each pixel unit is connected to the common electrode line;

11. The array substrate according to claim 10, wherein

A data line connected to the source of the thin film transistor in each pixel unit, and a common electrode line connected to the common electrode in each pixel unit are parallel to the slit of the slit electrode of the corresponding portion of the pixel unit.

The array substrate according to any one of claims 1 to 11, wherein

The drain of the thin film transistor in each pixel unit is connected to the pixel electrode in the pixel unit; the array substrate further includes a passivation layer disposed between the common electrode and the pixel electrode.

The array substrate according to any one of claims 1 to 12, wherein

The common electrode in each pixel unit is a slit electrode including a bend, and the pixel electrode is a plate electrode;

Alternatively, the common electrode and the pixel electrode in each of the pixel units are slit electrodes including a bend.

A display device comprising the array substrate according to any one of claims 1-13.