WO2014032940A1 - Carrier plate, device having the carrier plate and method for producing a carrier plate - Google Patents
Carrier plate, device having the carrier plate and method for producing a carrier plate Download PDFInfo
- Publication number
- WO2014032940A1 WO2014032940A1 PCT/EP2013/066731 EP2013066731W WO2014032940A1 WO 2014032940 A1 WO2014032940 A1 WO 2014032940A1 EP 2013066731 W EP2013066731 W EP 2013066731W WO 2014032940 A1 WO2014032940 A1 WO 2014032940A1
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- layer
- carrier plate
- area
- interrupted
- substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K1/00—Soldering, e.g. brazing, or unsoldering
- B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
- B23K1/0016—Brazing of electronic components
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K1/00—Soldering, e.g. brazing, or unsoldering
- B23K1/20—Preliminary treatment of work or areas to be soldered, e.g. in respect of a galvanic coating
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K31/00—Processes relevant to this subclass, specially adapted for particular articles or purposes, but not covered by only one of the preceding main groups
- B23K31/02—Processes relevant to this subclass, specially adapted for particular articles or purposes, but not covered by only one of the preceding main groups relating to soldering or welding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0361—Stripping a part of an upper metal layer to expose a lower metal layer, e.g. by etching or using a laser
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
- H05K2203/107—Using laser light
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1173—Differences in wettability, e.g. hydrophilic or hydrophobic areas
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Definitions
- a carrier plate It is specified a carrier plate. Furthermore, a device with a support plate and a on the
- Carrier plate arranged electrical component and a method for producing a carrier plate specified.
- solder stop solder stop
- solder resist for example, a layer of a poorly wettable polymer is used over which the solder does not run away. Due to the required accuracy, the polymer layer must be photostructured.
- SMD solder mask defined
- NSMD non-solder mask defined
- soldering areas are determined by the conductor tracks themselves.
- Embodiments to specify a carrier plate which in the
- Has properties and also is inexpensive to produce. Further objects of at least some embodiments are to specify a device with a carrier plate and an electrical component arranged on the carrier plate and a method for producing a carrier plate.
- a carrier plate has a substrate and at least one conductor track.
- the substrate preferably has an organic or a ceramic
- the substrate may be a
- the substrate comprises or consists of an LTCC, a HTCC, or an MLV ceramic.
- LTCC stands for "low temperature cofired ceramics", ie for ceramics that are typically sintered at temperatures below 1000 ° C
- HTCC for "high temperature cofired ceramics ", ie for ceramics that are typically sintered at temperatures above 1000 ° C
- MLV for multi-layer varistor ".
- the at least one conductor track is applied to a surface of the substrate.
- the conductor track has a first layer, which is applied directly to the substrate.
- the first layer can be referred to here and below as “base metallization” or as
- the first layer may comprise copper or silver or a combination thereof or one of these
- the conductor track furthermore has a second layer, which is arranged on the first layer.
- the second layer is preferably the uppermost layer of the conductor track which is furthest from the substrate of the carrier plate.
- the second layer can here and below also be referred to as “final metallization”, as “final metallization layer” or as
- the second layer may be applied directly to the first layer.
- one or more further layers to be arranged between the first and the second layer.
- the second layer has a different material from the first layer.
- the second layer may, for example, comprise gold or consist of gold.
- flash gold that is to say a thin, for example at most 120 nm thick, generally rapidly applied gold surface, which is particularly suitable for Soldering is used, such as so-called "direct immersion gold” (DIG).
- the second layer has a supply region and a soldering region, wherein the second layer between the supply region and the
- Soldering area is completely interrupted. That can
- the second layer is removed in the interrupted area.
- the soldering area can be provided in particular for applying a solder, for example in the form of a solder ball, by means of which a contact, for example, of a solder
- Supply line can form a so-called “fan-in” or “fan-out” or at least part of it.
- the first layer is below the first layer
- the second layer may be removed in the interrupted area, with the underlying first layer in this area
- Wettability of the conductor can be reduced so that the interrupted area acts as a solder stop.
- the gold or flashgold contained in the uppermost layer that is to say in the second layer, is responsible for a high wettability.
- solder resist can be produced inexpensively, as can be dispensed expensive solder mask, which must meet various requirements.
- solder resist would have to have sufficient adhesion both to the substrate and to the metallization.
- the solder resist should be so thin that flip chips can be underfilled and should additionally withstand any electroplating baths.
- a part of the second layer is removed in the interrupted region by means of a laser.
- a laser for example, a C02 laser or a UV laser can be used for ablation.
- a C02 laser or a UV laser can be used for ablation.
- the laser used by the choice of wavelength absorption in the various materials
- the first layer is oxidized below the discontinuous area. This can be achieved, for example, by the fact that up to the first layer, ie up to the first layer
- Base metallization is lasered so that the first layer is at least superficially influenced by the laser, which is used to produce the interruption of the second layer, but not severed.
- the action of the laser can form an oxidation at least in a partial region of the surface of the first layer.
- oxidized part of the area can be poorly wetted. Furthermore, it is possible to chemically oxidize or otherwise chemically treat the first layer so that the first layer becomes poorly wetting.
- the conductor track has a third layer, which is arranged between the first and the second layer.
- the third layer preferably adjoins directly to the first layer of the conductor track. Furthermore, the third layer can be directly connected to the second
- Adjacent layer of the conductor track Adjacent layer of the conductor track.
- one or more further layers to be arranged between the third and the second layer.
- the third layer comprises, for example, nickel or consists of nickel.
- nickel may be used as
- the third layer is continuous below the interrupted area.
- the third layer is interrupted below the interrupted area.
- interrupted portion of the second layer may be removed and below the interrupted area and a part of the third layer, wherein the underlying first layer, for example, undamaged or alternatively oxidized as described above.
- the conductor track has a fourth layer, which is arranged between the second and the third layer.
- the fourth layer preferably adjoins both the second and the third layer of the conductor track.
- the fourth layer may, for example, comprise palladium or palladium
- the fourth layer is interrupted below the discontinuous region of the second layer.
- the second layer may be in the interrupted area and the fourth layer below the interrupted area by means of a laser, wherein the third layer may be continuous or also interrupted below the interrupted area.
- the fourth layer is below the second layer
- Constellation can be achieved, for example, by only the second layer in the interrupted area is removed.
- a layer of the conductor track exposed by one or more interrupted layers has a lower wettability than the one
- the soldering area is at least partially covered by a solder.
- a solder For example, at least part of the soldering area may be covered by a solder ball ("solder bump") arranged on the soldering area 12.
- solder bump solder ball
- the conductor track has an end of the soldering area opposite the soldering area
- the supply area is again separated from the further soldering area by means of an interrupted area.
- the further soldering area is preferably also at least partially covered by a solder.
- the carrier plate is free of solder mask.
- a device has a carrier plate and an electrical component arranged on the carrier plate.
- the electrical component may in particular be a semiconductor component, for example a semiconductor chip in the form of a semiconductor chip
- the electrical component may be a component which is mounted on a carrier by means of a so-called "under-bump metallization” (UBM), which is for example directly connected to one or more strip conductors.
- UBM under-bump metallization
- the device may comprise a carrier plate having one or more features of the foregoing and others
- Embodiments include. According to one embodiment, the carrier plate has a
- Substrate and a plurality of conductor tracks are each applied to the substrate.
- the conductor tracks each have a first
- each of the conductor tracks according to the previously described embodiments can be designed for the at least one conductor track.
- the second conductor tracks according to the previously described embodiments can be designed for the at least one conductor track.
- Layers of the plurality of conductor tracks in particular each have a supply area and a soldering area, wherein the second layers are completely interrupted in each case between the supply area and the soldering area.
- Soldering areas of the plurality of conductor tracks a surface which forms a connection area for the electrical component. For example, a plurality of soldering areas one
- Component can be arranged and fixed on this surface.
- the electrical component is connected to the solder areas by means of solder.
- the electrical component can be mechanically fastened to the carrier plate as well as electrically
- the lead areas are outside of
- a carrier plate is produced in one method.
- the carrier plate may have one or more features of the foregoing
- a carrier plate which comprises a substrate and at least one
- the conductor preferably has a first layer directly on the substrate and a second layer disposed on the first layer.
- a region of the second layer is removed, so that the second layer is completely interrupted between the supply region and the soldering region. Furthermore, it is possible to have a third and / or a fourth layer arranged between the first and the second layer in the interrupted region
- the removal takes place by means of laser ablation.
- a laser with a suitable power and wavelength is used.
- a CO 2 - laser or a UV laser can be used.
- the method described here has the advantage that a rewiring can be made directly on the substrate, without burying it in inner layers in the substrate, that is, a solder joint can be connected to the circuit on the surface of the substrate. As a result, space can be saved within the carrier plate and the integration density can be increased.
- FIG. 1 shows a schematic plan view of a carrier plate according to an embodiment
- FIG. 2 shows a schematic cross section of a carrier plate with a conductor track according to a further exemplary embodiment
- FIG. 3 shows a detail of a schematic plan view of a conductor track of a carrier plate according to a further exemplary embodiment
- Figure 4 is a plan view of a device with a
- FIGS 5 and 6 are schematic representations of methods for
- Figure 1 is a support plate 1 according to a
- the carrier plate 1 comprises a substrate 2 made of an LTCC ceramic and a plurality of
- the substrate 2 may also be a HTCC or MLV ceramic or a printed circuit board, for example a FR4 printed circuit board.
- the individual interconnects 3 each have a solder region 422, an interrupted region 423 and a supply region 421, as described in connection with the following exemplary embodiments.
- the carrier plate 1 has a plurality of
- soldering regions 422 of the conductor tracks form a surface which forms a connection region for an electrical component, while the supply line regions form rewirings.
- carrier plate 1 are purely exemplary and not limiting to understand.
- FIG. 2 shows a carrier plate 1 according to another
- the arranged on the substrate 2 interconnects 3 has a first layer 41 which is applied directly to the substrate 2.
- the first layer 41 contains copper in the embodiment shown.
- the first layer 41 may also contain silver.
- the first layer 41 may also contain silver.
- the conductor 3 has a second, gold containing layer 42 which is disposed on the first layer 41 and the uppermost layer of
- Layer 42 may, for example, be a layer of so-called "direct immersion gold” (DIG)
- DIG direct immersion gold
- the second layer 42 may, for example, have a layer thickness of approximately 50 nm.
- the second layer 42 has a feed region 421 and a solder region 422, the second layer 42
- the carrier plate 1 has a via 9, which is filled with an electrically conductive material and is electrically conductively connected to the conductor track 3.
- another soldering region can be formed on an end of the supply region 421 opposite the soldering region 422
- the conductor track 3 may also have a third layer 43, which is arranged between the first and the second layer 41, 42, and optionally also a fourth layer 44, which is arranged between the second and the third layer 42, 43.
- the metallization of the third and second layers 43, 42 or of the third, fourth and second layers 43, 44, 42 applied to the first layer 41, that is to say on the base metallization may be, for example, Ni / Au (electroless nickel / immersion gold, ENIG) or to act without current Ni / Pd / Au (electroless nickel / electroles palladium / immersion gold, ENEPIG).
- the third layer 43 may, for example, have a layer thickness between 2 ⁇ m and 4 ⁇ m
- the fourth layer 44 may have, for example, a layer thickness between 0.3 ⁇ m and 0.5 ⁇ m.
- Figure 3 shows a section of a conductor 3 on a substrate 2 according to a further embodiment, which may be, for example, a conductor 3 of the support plate 1 of Figure 1.
- the conductor track 3 has an interrupted region 423, which is arranged between a soldering region 422 and a supply region 421.
- the carrier plate 1 shown here advantageously by means of the interrupted region 423 of the second layer 42, ie the gold-containing and for a high
- the carrier plate described here can be inexpensive
- FIG. 4 shows a plan view of a device 10 which comprises a carrier plate 1 and an electrical component 7 arranged on the carrier plate 1.
- the electrical component 7 is only indicated in order to represent the underlying structures.
- the carrier plate 1 has a substrate 2 and a plurality of conductor tracks 3, each on the substrate. 2
- the conductor tracks 3 each have one First layer 41, which is applied directly to the substrate 2, and a second layer 42, which is arranged on the first layer 41.
- the second layers 42 each have a feed region 421 and a solder region 422.
- the second layers 42 are completely interrupted between the feed region 421 and the solder region 422 by a discontinuous region 423.
- the solder regions 422 define an area that has a
- Connecting area 8 for the electrical component 7 forms.
- the electrical component 7 is by means of Lot 6 with the
- Component is mounted on the support plate 1.
- the electrical component 7 may have one or more contact surfaces, by means of which the
- electrical component 7 is electrically connected by solder 6 to the soldering regions 422.
- Feed line regions 421 outside the connection region 8 are free of solder 6 and form a rewiring.
- a solder stop for the solder 6 applied to the solder regions 422 can be produced.
- Component 7 may, for example, a semiconductor device, such as a semiconductor chip in the form of a
- FIG. 5 shows a schematic view of a method for producing a carrier plate 1, as shown for example in the previous embodiments.
- a carrier plate 1 is provided, which comprises a substrate 2 and at least one
- Conductor 3, which is applied to the substrate 2 comprises.
- the conductor 3 has a first layer 41, which is applied directly to the substrate and a second layer 42, which is arranged on the first layer 41 and forms an uppermost layer of the conductor 3.
- a region of the second layer 42 is removed, so that the second layer 42 between the feed region 421 and the solder region 422 is completely interrupted. Preferably, this is done
- Wetting properties also acts as a soldering stop.
- FIG. 6 shows a schematic representation of the
- Layer 44 are removed by means of a laser beam 5.
- only one region 423 of the second layer 42 can be removed, or only one region 423 of the second layer 42 and an underlying region of the fourth layer 44.
- the invention is not limited by the description based on the embodiments of these, but includes each new feature and any combination of features. This includes in particular any combination of features in the claims, even if this feature or these
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015528944A JP2015533260A (en) | 2012-08-27 | 2013-08-09 | Carrier plate, device equipped with carrier plate, and method of manufacturing carrier plate |
US14/424,754 US10117329B2 (en) | 2012-08-27 | 2013-08-09 | Carrier plate, device having the carrier plate and method for producing a carrier plate |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102012107876.9 | 2012-08-27 | ||
DE102012107876.9A DE102012107876A1 (en) | 2012-08-27 | 2012-08-27 | Support plate, device with carrier plate and method for producing a carrier plate |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2014032940A1 true WO2014032940A1 (en) | 2014-03-06 |
Family
ID=48953401
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2013/066731 WO2014032940A1 (en) | 2012-08-27 | 2013-08-09 | Carrier plate, device having the carrier plate and method for producing a carrier plate |
Country Status (4)
Country | Link |
---|---|
US (1) | US10117329B2 (en) |
JP (1) | JP2015533260A (en) |
DE (1) | DE102012107876A1 (en) |
WO (1) | WO2014032940A1 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170113297A1 (en) * | 2015-10-27 | 2017-04-27 | Hutchinson Technology Incorporated | Metallizing polymers, ceramics and composites for attachment structures |
US10076800B2 (en) | 2015-11-30 | 2018-09-18 | Cree Fayetteville, Inc. | Method and device for a high temperature vacuum-safe solder stop utilizing laser processing of solderable surfaces for an electronic module assembly |
US10925663B2 (en) | 2016-06-27 | 2021-02-23 | Mound Laser & Photonics Center, Inc. | Metallized components and surgical instruments |
US10307851B2 (en) * | 2016-12-14 | 2019-06-04 | Raytheon Company | Techniques for providing stop-offs for brazing materials or other materials on structures being joined |
DE102019205967A1 (en) * | 2019-04-25 | 2020-10-29 | Volkswagen Aktiengesellschaft | Process for the pretreatment and coating of a substrate |
Citations (3)
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US6577012B1 (en) * | 2001-08-13 | 2003-06-10 | Amkor Technology, Inc. | Laser defined pads for flip chip on leadframe package |
US20080237814A1 (en) * | 2007-03-26 | 2008-10-02 | National Semiconductor Corporation | Isolated solder pads |
US20090236756A1 (en) * | 2008-03-19 | 2009-09-24 | Oh Han Kim | Flip chip interconnection system |
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US5773764A (en) * | 1996-08-28 | 1998-06-30 | Motorola, Inc. | Printed circuit board panel |
DE19927046B4 (en) * | 1999-06-14 | 2007-01-25 | Electrovac Ag | Ceramic-metal substrate as a multi-substrate |
KR20080031522A (en) * | 2000-02-25 | 2008-04-08 | 이비덴 가부시키가이샤 | Multilayer printed wiring board and method for producing multilayer printed wiring board |
EP1202390B1 (en) * | 2000-10-25 | 2008-05-21 | Japan Aviation Electronics Industry, Limited | An electronic component and a method of manufacturing the same |
US7242099B2 (en) * | 2001-03-05 | 2007-07-10 | Megica Corporation | Chip package with multiple chips connected by bumps |
EP1667225A4 (en) * | 2003-09-24 | 2009-04-01 | Ibiden Co Ltd | Interposer and multilayer printed wiring board |
US7394161B2 (en) * | 2003-12-08 | 2008-07-01 | Megica Corporation | Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto |
JP2006086201A (en) | 2004-09-14 | 2006-03-30 | Shinei Hitec:Kk | Flexible wiring board and surface treating method therefor |
JP4493664B2 (en) | 2007-01-16 | 2010-06-30 | 京セラ株式会社 | Ceramic circuit board and semiconductor module |
JP5145729B2 (en) * | 2007-02-26 | 2013-02-20 | 富士電機株式会社 | Solder bonding method and semiconductor device manufacturing method using the same |
JP2008227055A (en) | 2007-03-12 | 2008-09-25 | Mitsubishi Electric Corp | Circuit board |
DE102007044046B4 (en) * | 2007-09-14 | 2013-01-03 | Infineon Technologies Ag | Method for internal contacting of a power semiconductor module |
JP2009147210A (en) | 2007-12-17 | 2009-07-02 | Stanley Electric Co Ltd | Ceramic circuit substrate and semiconductor light-emitting module |
DE102009038674B4 (en) | 2009-08-24 | 2012-02-09 | Epcos Ag | Carrier device, arrangement with such a carrier device and method for producing a structured layer stack comprising at least one ceramic layer |
US8304919B2 (en) * | 2010-03-26 | 2012-11-06 | Stats Chippac Ltd. | Integrated circuit system with stress redistribution layer and method of manufacture thereof |
-
2012
- 2012-08-27 DE DE102012107876.9A patent/DE102012107876A1/en not_active Ceased
-
2013
- 2013-08-09 WO PCT/EP2013/066731 patent/WO2014032940A1/en active Application Filing
- 2013-08-09 US US14/424,754 patent/US10117329B2/en not_active Expired - Fee Related
- 2013-08-09 JP JP2015528944A patent/JP2015533260A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6577012B1 (en) * | 2001-08-13 | 2003-06-10 | Amkor Technology, Inc. | Laser defined pads for flip chip on leadframe package |
US20080237814A1 (en) * | 2007-03-26 | 2008-10-02 | National Semiconductor Corporation | Isolated solder pads |
US20090236756A1 (en) * | 2008-03-19 | 2009-09-24 | Oh Han Kim | Flip chip interconnection system |
Also Published As
Publication number | Publication date |
---|---|
DE102012107876A1 (en) | 2014-02-27 |
US20150223329A1 (en) | 2015-08-06 |
JP2015533260A (en) | 2015-11-19 |
US10117329B2 (en) | 2018-10-30 |
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