WO2014030040A1

WO2014030040A1 - Methods of forming semiconductor structures and devices including graphene, and related structures and devices

Info

Publication number: WO2014030040A1
Application number: PCT/IB2013/001721
Authority: WO
Inventors: Christiaan J. Werkhoven
Original assignee: Soitec
Priority date: 2012-08-24
Filing date: 2013-08-02
Publication date: 2014-02-27

Abstract

Methods of forming semiconductor structures include providing graphene over at least one of two substrates. The first substrate is bonded to the second substrate with the graphene disposed between substrates. Semiconductor structures include a first substrate comprising a semiconductor material and having a major surface, a second substrate having a major surface, and at least one graphene monolayer disposed between the major surface of the first substrate and the major surface of the second substrate. The at least one graphene monolayer may bond the major surface of the first substrate to the major surface of the second substrate. Composite semiconductor substrates comprise a base substrate, a thin layer of semiconductor material disposed over the base substrate, and at least one graphene monolayer disposed between the thin layer of semiconductor material and the base substrate.

Description

TITLE

METHODS OF FORMING SEMICONDUCTOR STRUCTURES AND DEVICES INCLUDING GRAPHENE, AND RELATED STRUCTURES AND DEVICES

TECHNICAL FIELD

[0001] The present disclosure relates to methods of manufacturing semiconductor structures and devices that include two or more substrates bonded together, and to semiconductor structures and devices fabricated using such methods. Embodiments of the present disclosure relate to using one or more graphene monolayers to bond the two or more substrates together.

BACKGROUND

[0002] Semiconductor devices include, for example, electronic signal processors, electronic memory devices, photoactive devices, and microelectromechanical (MEM) devices. Such structures and materials often include one or more semiconductor materials (e.g., silicon, germanium, a III-V semiconductor material, a II- VI semiconductor material, etc.), and may include at least a portion of an integrated circuit.

[0003] Some semiconductor devices are fabricated using so-called "engineered substrates," which generally include multiple layers or structures of different material. Engineered substrates may include, for example, a semiconductor material layer bonded to a heat dissipation layer, to a dielectric material layer, to a layer including an integrated circuit (e.g., a so-called "active layer"), and/or to a carrier substrate. For example, silicon dioxide (Si0₂) layers and/or silicon nitride (Si₃N₄) layers have been used to bond layers or structures of engineered substrates together based on their good bonding strength. However, these materials are generally dielectric materials with low electrical and/or thermal conductivity. In engineered substrates where relatively higher electrical and/or thermal conductivity is desired, such as in light emitting diodes (LEDs) or power switches, Si0₂ and/or Si₃N₄ are not ideal as adhesion layers due to their low electrical and/or thermal conductivity.

BRIEF SUMMARY

[0004] This summary is provided to introduce a selection of concepts in a simplified form. These concepts are described in further detail in the detailed description of example embodiments of the disclosure below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0005] In some embodiments, the present disclosure includes methods of forming semiconductor structures. In accordance with such methods, graphene is disposed over at least one of a major surface of a first substrate and a major surface of a second substrate. At least the first substrate comprises a semiconductor material. The major surface of the first substrate is bonded to the major surface of the second substrate with the graphene disposed between the major surface of the first substrate and the major surface of the second substrate.

[0006] In additional embodiments, the present disclosure includes semiconductor structures that comprise a first substrate comprising a semiconductor material and having a major surface, a second substrate having a major surface, and at least one graphene monolayer disposed between the major surface of the first substrate and the major surface of the second substrate. The at least one graphene monolayer bonds the major surface of the first substrate to the major surface of the second substrate.

[0007] In yet further embodiments, the present disclosure includes composite

semiconductor substrates that comprise a base substrate, a thin layer of semiconductor material disposed over the base substrate, and at least one graphene monolayer disposed between the thin layer of semiconductor material and the base substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] While the specification concludes with claims particularly pointing out and distinctly claiming what are regarded as embodiments of the invention, the advantages of embodiments of the disclosure may be more readily ascertained from the description of certain examples of embodiments of the disclosure when read in conjunction with the accompanying drawings, in which:

[0009] FIGS. 1 and 2 illustrate an example of a method that may be used to form a semiconductor structure according to an embodiment of the present disclosure;

[0010] FIG. 1 is a simplified cross-sectional side view illustrating graphene disposed over a major surface of a substrate; [0011] FIG. 2 is a simplified cross-sectional side view illustrating another substrate with graphene thereon bonded to the structure of FIG. 1 with the graphene on both substrates disposed between the substrates;

[0012] FIGS. 3 through 10 illustrate an example of a method like that of FIGS. 1 and 2, but including further processing;

[0013] FIG. 3 is a simplified cross-sectional side view illustrating ions being implanted into the first substrate along an ion implant plane;

[0014] FIG. 4 is a simplified cross-sectional side view illustrating a structure of the first substrate with the implanted ions bonded to the second substrate using graphene for adhesion therebetween;

[0015] FIG. 5 is a simplified cross-sectional side view illustrating a structure formed by fracturing the first substrate in the structure of FIG. 4 along the ion implant plane, leaving a thin layer of material bonded to the second substrate with graphene therebetween;

[0016] FIG. 6 is a simplified cross-sectional side view illustrating a structure formed by treating an exposed surface of the thin layer of material in the structure of FIG. 5;

[0017] FIG. 7 is a simplified cross-sectional side view illustrating a structure that includes an active layer formed over the thin layer of material of the structure of FIG. 5;

[0018] FIG. 8 is a simplified cross-sectional side view illustrating a carrier substrate attached over the active layer of the structure of FIG. 7;

[0019] FIG. 9 is a simplified cross-sectional side view illustrating the structure of FIG. 8 being cleaved or otherwise fractured along the graphene to remove the second substrate; and

[0020] FIG. 10 is a simplified cross-sectional side view illustrating a structure formed by removing graphene from a structure shown in FIG. 9.

DETAILED DESCRIPTION

[0021] The illustrations presented herein are not meant to be actual views of any particular semiconductor material, structure, or device, but are merely idealized representations that are used to describe embodiments of the disclosure.

[0022] Any headings used herein should not be considered to limit the scope of embodiments of the invention as defined by the claims below and their legal equivalents. Concepts described in any specific heading are generally applicable in other sections throughout the entire specification.

[0023] A number of references are cited herein, the entire disclosures of which are incorporated herein in their entirety by this reference for all purposes. Further, none of the cited references, regardless of how characterized herein, is admitted as prior art relative to the invention of the subject matter claimed herein.

[0024] As used herein, the term "substantially," in reference to a given parameter, property, or condition, means to a degree that one of ordinary skill in the art would understand that the given parameter, property, or condition is met within a degree of variance, such as within acceptable manufacturing tolerances.

[0025] As used herein, the term "semiconductor device" means and includes any operative device comprising one or more semiconductor materials that is capable of performing one or more functions when properly and functionally integrated into an electronic or optoelectronic device or system. Semiconductor devices include, but are not limited to, electronic signal processors, memory devices, optoelectronic devices (e.g., light-emitting diodes, laser-emitting diodes, solar cells, etc.), and devices that include two or more such devices operatively connected with one another.

[0026] As used herein, the term "semiconductor structure" means and includes any structure that is used or formed during the fabrication of a semiconductor device. Semiconductor structures include, for example, dies and wafers (for example, carrier substrates and device substrates), as well as assemblies or composite structures that include two or more dies and/or wafers three-dimensionally integrated with one another. Semiconductor structures also include fully fabricated semiconductor devices, as well as intermediate structures formed during fabrication of semiconductor devices.

[0027] As used herein, any relational term, such as "first," "second," "over," "on," etc., is used for clarity and convenience in understanding the disclosure and accompanying drawings and does not connote or depend on any specific preference, orientation, or order, except where the context clearly indicates otherwise.

[0028] The present disclosure includes methods of forming semiconductor structures and devices wherein graphene is disposed between two substrates, and may be used to adhere the substrates together, and to semiconductor structures fabricated using such methods. Examples of such methods and semiconductor structures are disclosed in further detail below.

[0029] FIGS. 1 and 2 illustrate a non-limiting example of a method of forming a semiconductor structure that includes disposing graphene over a surface of one or both of two substrates, and bonding the two substrates together with the graphene disposed between the two substrates.

[0030] FIG. 1 is a simplified cross-sectional view illustrating a first substrate 100 having a first major surface 104 and an opposing second major surface 106. As shown in FIG. 1, graphene 110 is disposed over the first major surface 104 of the first substrate 100. The graphene 110 may comprise one or more monolayers of graphene (i.e., graphene layers).

[0031] The first substrate 100 may comprise what is referred to in the art as a "die" or a "wafer," and may be generally planar. In some embodiments, the first substrate 100 may comprise a semiconductor material. For example, the first substrate 100 may comprise one or more of silicon, germanium, silicon carbide, a III-V semiconductor material (e.g., GaN, GaP, GaAs, InN, InP, InAs, . A1N, A1P, AlAs, BN, InGaN, InGaP, GalnN, InGaNP, GalnNAs, etc.), and a II- VI semiconductor material (CdSe, CdS, CdTe, ZnO, ZnSe, ZnS, ZnTe, CdZnTe, HgCdTe, HgZnTe, etc.). The material of the first substrate 100 may be substantially amorphous (e.g., glass-like) in some embodiments. In other embodiments, the material of the first substrate 100 may be substantially crystalline (e.g., polycrystalline or monocrystalline). The material of the first substrate 100 may include one or more dopants implanted therein, such as to alter one or more electrical properties thereof. Further, the first substrate 100 may be at least substantially comprised of a single, generally homogeneous material, or the first substrate 100 may comprise a multi-layer structure or a multiphase composite material.

[0032] In some embodiments, the first substrate 100 may have an average layer thickness between the first major surface 104 and the second major surface 106 (i.e., the vertical dimension from the perspective of FIG. 1) of about two hundred and fifty microns (250 μηι) or more, about five hundred microns (500 μπι) or more, or even about seven hundred and fifty microns (750 μιτι) or more. Of course, the first substrate 100 may have any desired thickness selected by one of ordinary skill in the art, depending on a desired application of the semiconductor structure to be formed, and the average layer thickness may be less than two hundred and fifty microns (250 μηι) in additional embodiments. [0033] The graphene 110 may be disposed over the first major surface 104 of the first substrate 100. As will be explained in more detail below, disposing the graphene 110 over the first major surface 104 of the first substrate 100 may include forming graphene separately from the first substrate 100 and subsequently transferring the graphene 110 to the first major surface 104 in some embodiments. In other embodiments, at least a portion of the graphene 110 may be formed {e.g., grown) directly on or over the first major surface 104 of the substrate 100. The graphene 110 may comprise a single monolayer or multiple monolayers of graphene. Graphene is formed of a monolayer of carbon atoms arranged hexagonally and bonded with one another by covalent bonds, such that each carbon atom is bonded to three adjacent carbon atoms. Graphene has been shown to exhibit high electrical conductivity (higher than copper) and high thermal conductivity (about ten (10) times higher than copper). In addition, graphene is more than about one hundred (100) times stronger than the strongest steel, while being mechanically flexible. Graphene 110 may adhere to a surface, such as the major surface 104 of the first substrate 100, by so-called "van der Waals" ^■ interactions, although adhesion between graphene 110 and other materials has been shown to be relatively higher than van der Waals adhesion between other materials. Thus, in some

embodiments, inter-atomic bonds may be established directly between the graphene 110 and the first major surface 104 of the first substrate 100.

[0034] The graphene 110 may be provided on the first major surface 104 of the first substrate 100 by various methods. For example, one or more graphene monolayers of the graphene 110 may be grown directly on the first major surface 104 of the first substrate 100. As a specific non-limiting example, the graphene 110 may be grown on the first maj or surface 104 of the first substrate 100 by a chemical vapor deposition (CVD) process. In additional embodiments, the graphene 110 may be grown on a growth substrate, such as a copper foil, separate from the substrate 100, and subsequently transferred from the growth substrate to the first major surface 104 of the first substrate 100 using, for example, the "roll-to-roll" process as described in Sukang Bae et al., " oll-to-Roll Production of 30-inch Graphene Films for Transparent Electrodes," 5 Nature Nanotechnology, 51 '4 (Aug. 2010) (hereinafter "Bae"), which is hereby incorporated herein by this reference in its entirety.

[0035] For example, as described in Bae, a quartz tube having an approximately 7.5 inch (19.05 cm) diameter may be wrapped with a copper foil and inserted inside another quartz tube having an approximately 8 inch (20.32 cm) diameter. The copper foil may be heated to about 1,000°C while flowing hydrogen gas (H₂) within the 8 inch (20.32 cm) quartz tube. For example, about 8 standard cubic centimeters per minute (seem) of H₂ may be flowed at a pressure of about 90 mtorr. The copper foil may be heat-treated (i.e., annealed) for about 30 minutes, while

substantially maintaining the temperature of about 1,000°C, the flow of the H₂, and the pressure, to increase grain size in the copper foil. After the heat treatment, methane (CH₄) and H₂ may be flowed in the 8 inch (20.32 cm) quartz tube under a pressure of about 460 mtorr. The methane may be flowed at a rate of about 24 seem, and the H₂ may be flowed at a flow rate of about 8 seem. After about 30 minutes of flowing the methane, the methane flow may be stopped and the copper foil may be rapidly cooled (e.g., about 10°C per second) to about room temperature while flowing the H₂ under a pressure of about 90 mtorr. Under these conditions, carbon from the methane may react to form graphene 110 on an exposed surface of the copper foil.

[0036] After the graphene 1 10 is formed on the copper foil, a polymer support (e.g. , a thermal release tape) may be applied over the graphene 1 10, such as by pressing and adhering. For example, the polymer support may be pressed against the graphene 1 10 with a pressure of about 0.2 MPa between two rollers (not shown). The material of the polymer support may be selected such that the copper foil is selectively etchable with respect to the material of the polymer support. Next, the copper foil may be removed by exposing at least the copper foil, and, optionally, the graphene 110 and polymer support, to an etchant that removes (e.g., dissolves) the copper foil. The graphene 1 10 may remain on the polymer support after the copper foil is removed.

[0037] Finally, the graphene 110 may be transferred to the first major surface 104 of the first substrate 100 to form at least a portion of the graphene 110 bonded or otherwise attached to the first substrate 100. For example, transferring the graphene 110 to the first substrate 00 may include pressing the graphene 110 and the polymer support against the first substrate 100 with a roller and exposing the polymer support to heat sufficient to release the polymer support from the graphene 1 10. For example, the polymer support may be exposed to a temperature of between about 90°C and about 120°C. After releasing the polymer support from the graphene 1 0, the graphene 1 10 may remain over the first substrate 100 to form at least a portion of the graphene 1 10. In some embodiments, depending on the specific materials used at the interface between the first substrate 100 and the graphene 1 10, the graphene 1 10 may be attached to the first substrate 100 by van der Waals forces. In some embodiments, the graphene 110 may be directly attached to the first substrate 100. In other words, there may be substantially no material between the first substrate 100 and the graphene 110.

[0038] If it is desired to form the graphene 1 10 to comprise multiple monolayers of graphene 110, the process described above may be repeated using the same first substrate 100, which may add one monolayer of graphene 1 10 over the first substrate 100 per repetition.

[0039] By way of another non-limiting example, one or more monolayers of graphene 1 10 may be formed using ion implantation techniques, as disclosed in U.S. Patent Application Serial No. 12/487,100 to Ramappa et al., filed June 18, 2009, titled "Method to Synthesize

Graphene," published as U.S. Patent Application Publication No. 2010/03231 13 (hereinafter "Ramappa"), the disclosure of which is hereby incorporated herein by this reference in its entirety. For example, carbon ions may be implanted in a metal foil substrate comprising, for example, one or more of copper, nickel, ruthenium, iron, and aluminum, using a plasma doping system or a beam line implanter, as is known in the art. The carbon ions may be implanted in the metal foil substrate at an elevated temperature to enable a large number of carbon ions to be absorbed by the metal foil substrate (e.g., to over-saturate the metal foil substrate with carbon ions). An example source of the carbon ions may be, for example, methane or carbon tetrachloride (CC1₄). After the carbon ions are implanted in the metal foil substrate, a temperature of the metal foil substrate may be reduced, and at least some of the implanted carbon ions may diffuse (also referred to in the art as "precipitate") to the surface of the metal foil substrate. The carbon ions that diffuse to the surface of the metal foil substrate may form one or more monolayers of graphene 110 on the surface of the metal foil substrate.

[0040] After the one or more monolayers of graphene 110 are formed on the surface of the metal foil substrate, a process like that described above with reference to Bae may be performed to transfer the one or more monolayers of graphene 110 from the metal foil substrate to the first substrate 100 to dispose the graphene 110 on the first major surface 104 of the first substrate 100.

[0041] In another embodiment, such as if the first substrate 100 comprises silicon carbide, graphene 1 10 may be epitaxially grown directly on the first major surface 104 of the first substrate 100 to form at least a portion of the graphene 1 10. For example, silicon carbide of the first substrate 100 may be heated to a temperature of between about 1,000°C and about 1,400°C under a reduced pressure (e.g., less than about 1 mtorr) for between about 1 minute and about 20 minutes to induce formation (e.g., epitaxial growth) of one or more monolayers of graphene 1 10 directly on the first major surface 104.

[0042] Referring to FIG. 2, after disposing the graphene 1 10 over the first major surface 104 of the first substrate 100, the first major surface 104 of the first substrate 100 may be bonded to a major surface 124 of a second substrate 120 with the graphene 110 disposed between the first major surface 104 of the first substrate 100 and the major surface 124 of the second substrate 120. In some embodiments, the graphene 1 10 may be used to adhere the first major surface 104 of the first substrate 100 to the major surface 124 of the second substrate 120.

[0043] The second substrate 120 may comprise a substrate as disclosed in relation to the first substrate 100 with reference to FIG. 1. The second substrate 120, however, may or may not comprise a semiconductor material. In some embodiments, the second substrate 120 may comprise a semiconductor material as disclosed in relation to the first substrate 100. In other embodiments, the second substrate 120 may comprise a ceramic material such as an oxide (e.g., silicon oxide, aluminum oxide, mullite), a nitride (e.g., silicon nitride, boron nitride), or a carbide (e.g., boron carbide), or the second substrate 120 may comprise a metal material (e.g., molybdenum or a molybdenum alloy). Like the first substrate 100, the second substrate 120 may be at least substantially comprised of a single, generally homogeneous material, or the second substrate 120 may comprise a multi-layer structure or a multi-phase composite material.

[0044] Optionally, graphene 130 (shown in dashed lines in FIG. 2) also may be disposed over the major surface 124 of the second substrate 120 prior to bonding the second substrate 120 to the first substrate. The graphene 130 may comprise one or more monolayers of graphene. If the additional graphene 130 is present, the additional graphene 130 may be formed over the major surface 124 of the second substrate 120 by any of the processes described above, depending on the material of the second substrate 120. For example, if the second substrate 120 is substantially comprised of a metal material, such as copper, the additional graphene 130 may be grown using a CVD process directly on the major surface 124 of the second substrate 120, as described above with reference to Bae, or the additional graphene 130 may be formed by implantation of carbon ions into the second substrate 120 followed by diffusion of the carbon ions to the major surface 124 of the second substrate 120 to form the additional graphene 130, as described above with reference to Ramappa. In other embodiments, the additional graphene 130 may be transferred to the major surface 124 of the second substrate 120 from a copper foil, as described above with reference to Bae, for example.

[0045] As stated above, the second substrate 120 and the first substrate 100 may be bonded together using the graphene 110 (and, optionally, the additional graphene 130) as an adhesion layer therebetween. The first substrate 100 may be positioned over the second substrate 120, and the first substrate 100 and the second substrate 120 may be pressed together. By way of example and not limitation, one or more rollers (not shown) may be used to press the second substrate 120 against the first substrate 100.

[0046] The second substrate 120 may be bonded directly to the first substrate 100 substantially without using an adhesive between the second substrate 120 and the first substrate 100 other than the graphene 110 and/or the graphene 130. In other words, in embodiments in which graphene 110 is disposed on the first substrate 100, but graphene 130 is not provided on the second substrate 120, direct inter-atomic bonds may be established between the first major surface 104 of the first substrate 100 and the graphene 110, and direct inter-atomic bonds may be established between the graphene 110 and the major surface 124 of the second substrate 120. In embodiments in which graphene 130 is provided on the second substrate 120, direct inter-atomic bonds may be established between the first major surface 104 of the first substrate 100 and the graphene 110, direct inter-atomic bonds may be established between the graphene 110 and the graphene 130, and direct inter-atomic bonds may be established between the graphene 130 and the major surface 124 of the second substrate 120. Although the graphene 110 and the additional graphene 130 are shown in FIG. 2 as being distinct layers for clarity, it is to be understood that no physical boundary between the graphene 110, 130 may be identifiable. In other words, after being bonded together, the graphene 110 and the graphene 130 may form a single, substantially homogeneous graphene layer comprising multiple (i.e., two or more) monolayers of graphene.

[0047] In some embodiments, the bond between the first major surface 104 of the first substrate 100 and the major surface 124 of the second substrate 120 may be established by forming one, or both, of the first major surface 104 of the first substrate 100 and the major surface 124 of the second substrate 120 to be relatively smooth, and subsequently abutting the bonding surfaces together (but for the graphene 1 10, 130 therebetween) and initiating propagation of a bonding wave along the interface between the first substrate 100 and the second substrate 120. Graphene is generally highly conformal to deviations in planarity of surfaces to which it is attached. Additionally, the graphene 110 (and, optionally, the additional graphene 130) may be relatively thin. Thus, the first major surface 104 of the first substrate 100 may be smoothed (e.g., planarized) prior to disposing the graphene 110 over the first major surface 104 and/or prior to attaching the second substrate 120 to the first substrate 100. Similarly, the major surface 124 of the second substrate 120 may be smoothed prior to disposing the additional graphene 130 thereover, when present, and/or prior to attaching the second substrate 120 to the first substrate 100 using the graphene 1 10, 130 as an adhesion layer.

[0048] For example, each of the first major surface 104 of the first substrate 100 and the major surface 124 of the second substrate 120 may be formed to have a root mean square surface roughness (RR S) of about two nanometers (2.0 nm) or less, about one nanometer (1.0 nm) or less, or even about one-quarter of a nanometer (0.25 nm) or less. Each of the first major surface 104 of the first substrate 100 and the major surface 124 of the second substrate 120 may be smoothed using at least one of a mechanical polishing process and a chemical etching process. For example, a chemical-mechanical polishing (CMP) process may be used to planarize and/or reduce the surface roughness of each of the first major surface 104 of the first substrate 100 and the major surface 124 of the second substrate 120.

[0049] Prior to attaching the first substrate 100 to the second substrate 120, the bonding surfaces optionally may be cleaned using processes known in the art. Such a cleaning process may be used to remove defects and/or obstructions that may weaken the bond between the first substrate 100 and the second substrate 120.

[0050] The bonding surfaces may be brought into direct physical contact with one another, and pressure may be applied in a localized area across the bonding interface. Bonds may be initiated in the vicinity of the localized pressure area, and a bonding wave may propagate across the interface between the bonding surfaces.

[0051] Optionally, an annealing process may be used to strengthen the bond between the first substrate 100 and the second substrate 120. Such an annealing process may comprise heating the first substrate 100 and the second substrate 120 in a furnace at a temperature of between about 100°C and about 400°C for a time of between about two minutes (2 mins.) and about twenty-five hours (25 hrs.), for example.

[0052] Although the formation of the bonded semiconductor structure shown in FIG. 2 has been described as including the graphene 1 10 on the first substrate 100, and, optionally, the graphene 130 on the second substrate 120, the present disclosure is not so limited. In additional embodiments, the graphene 110 may be omitted and the first substrate 100 may be attached to the second substrate 120 using only graphene 130 on the second substrate 120 as an adhesion layer.

[0053] Alternatively, in some embodiments, the second substrate 120 may be provided over the first substrate 100 by forming at least a portion of the second substrate 120 directly on the graphene 110, such that the second substrate 120 is bonded to the first substrate 100. For example, in an embodiment wherein the second substrate 120 is substantially comprised of a metal material, a metal may be sputtered or otherwise provided over and on the graphene 110. Additional metal may be deposited using, for example, an electrolytic plating process to form the second substrate 120 over the graphene 110 and the first substrate 100.

[0054] In some embodiments, the graphene 110 disposed on the first substrate 100 (and, optionally, the additional graphene 130 disposed on the second substrate 120, if present) may be substantially comprised of a single monolayer of graphene. In other embodiments, the graphene 110 disposed on the first substrate 100 (and, optionally, the additional graphene 130 disposed on the second substrate 120, if present) may comprise multiple monolayers of graphene. In some embodiments, one or both of the graphene 110 and the graphene 130 may include one or more impurities (e.g., dopants) comprising one or more elements other than carbon, which may alter physical, adhesive, electrical, and/or thermal characteristics thereof.

[0055] The semiconductor structure shown in FIG. 2 may, in some embodiments, be further processed, such as by forming additional features on or in the first substrate 100 and/or the second substrate 120, by removing one or more portions of the first substrate 100 and/or the second substrate 120 (e.g., by an etching process, a polishing process, etc.), by subsequently de-bonding the first substrate 100 from the second substrate 120 at an interface between the graphene 110 and the second substrate 120, etc. Thus, the semiconductor structure shown in FIG. 2 may be used in a variety of applications and for a variety of different purposes.

[0056] In some embodiments, methods as described above with reference to FIGS. 1 and 2 above may be employed to form composite semiconductor substrates, and/or to form semiconductor devices. Non-limiting examples of such methods are described below with reference to FIGS. 3 through 10.

[0057] Referring briefly to FIG. 6, in some embodiments, a thin layer of semiconductor material 108 may be formed from the first substrate 100 after bonding the first major surface 104 of the first substrate 100 to the major surface 124 of the second substrate 120. The thin layer of semiconductor material 108 may remain bonded to the second substrate 120 with the graphene 110 and/or the graphene 130 disposed between the thin layer of semiconductor material 108 and the major surface 124 of the second substrate 120.

[0058] By way of example and not limitation, the process known in the art as the SMART CUT® process may be used to form the thin layer of semiconductor material 108 from the first substrate 100. The SMART CUT® process is described in, for example, U.S. Patent No. RE39,484 to Bruel (issued February 6, 2007), U.S. Patent No. 6,303,468 to Aspar et al. (issued October 16, 2001), U.S. Patent No. 6,335,258 to Aspar et al. (issued January 1, 2002), U.S. Patent No. 6,756,286 to Moriceau et al. (issued June 29, 2004), U.S. Patent No. 6,809,044 to Aspar et al. (issued October 26, 2004), and U.S. Patent No. 6,946,365 to Aspar et al. (September 20, 2005), the disclosures of which are incorporated herein in their entireties by this reference. Such a process is described with reference to FIGS. 3 through 6.

[0059] Referring to FIG. 3, ions (e.g. , one or more of hydrogen, helium, and inert gas ions) may be implanted into the first substrate 100 along an ion implant plane 102 (as shown by dashed lines) prior to bonding the first major surface 104 of the first substrate 100 to the major surface 124 of the second substrate 120. The implantation of ions is represented in FIG. 3 by directional arrows 105. The implanted ions along the ion implant plane 102 define a weakened ion implant plane within the first substrate 100, along which the first substrate 100 subsequently may be cleaved or otherwise fractured. As is known in the art, the depth at which the ions are implanted into the first substrate 100 is at least partially a function of the energy with which the ions are implanted into the first substrate 100. Generally, ions implanted with less energy will be implanted at relatively shallower depths, while ions implanted with higher energy will be implanted at relatively deeper depths.

[0060] FIG. 4 is substantially similar to FIG. 2, and illustrates the first substrate 100 with the ions implanted therein along the ion implant plane 102 bonded to the second substrate 120. As previously discussed, the graphene 1 10 may be disposed on the first major surface 104 of the first substrate 100 (which is proximate the ion implant plane 102). Additionally, additional graphene 130 comprising a single monolayer of graphene or multiple monolayers of graphene optionally may be disposed over the major surface 124 of the second substrate 120, as previously discussed with reference to FIG. 2. Of course, the additional graphene 130 may be omitted, or the graphene 130 may be used and the graphene 110 omitted, as previously mentioned.

[0061] In the process described above, the ion implant plane 102 is formed prior to disposing the graphene 110 over the first substrate 100. In additional embodiments of the present disclosure, ions may be implanted into the first substrate 100 to form the ion implant plane 102 after disposing the graphene 110 over the first substrate 100.

[0062] After bonding the first major surface 104 of the first substrate 100 to the major surface 124 of the second substrate 200 with the graphene 110, 130 disposed between the first major surface 104 of the first substrate 100 and the major surface 124 of the second substrate 120, the first substrate 100 may be cleaved or otherwise fractured along the ion implant plane 102 to form the structure shown in FIG. 5.

[0063] Referring to FIG. 5 in conjunction with FIG. 4, the first substrate 100 may be cleaved or otherwise fractured along the ion implant plane 102. For example, the first substrate 100 (with the second substrate 120 bonded thereto using the graphene 1 10 and the additional graphene 130) may be heated to cause the first substrate 100 to fracture along the ion implant plane 102. Alternatively or additionally, mechanical forces may be applied to the first substrate 100 and, optionally, to the second substrate 120 to assist in the cleaving of the first substrate 100 along the ion implant plane 102.

[0064] As shown in FIG. 5, after the first substrate 100 has been cleaved or otherwise fractured along the ion implant plane 102, a portion of the first substrate 100 remains bonded to the second substrate 120 by the graphene 1 10, 130, which portion defines a thin layer of semiconductor material 108. A remainder of the first substrate 100 may be reused in further SMART CUT® processes to transfer additional portions of the first substrate 100 to additional substrates. Thus, the first substrate 100 may comprise what is often referred to in the art as a "donor" substrate.

[0065] After fracturing the first substrate 100 along the ion implant plane 102 to separate the thin layer of semiconductor material 108 from a remainder of the first substrate 100, an exposed major surface 109 of the thin layer of semiconductor material 108 comprises a fractured surface of the first substrate 100, and may include ion impurities, crystallographic imperfections, and other defects in the crystal lattice of the thin layer of semiconductor material 108.

[0066] Referring to FIG. 6, the exposed major surface 109 of the thin layer of

semiconductor material 108 may be treated in an effort to reduce impurity levels, improve the P T/IB2013/001721

quality of a crystal lattice {i.e., reduce the number of defects in the crystal lattice proximate the exposed major surface 109) in the thin layer of semiconductor material 108, and/or improve the planarity of the exposed major surface 109 (as is illustrated in FIG. 6). Such treatments may involve one or more of grinding, polishing, etching, and thermal annealing.

[0067] The thin layer of semiconductor material 108 shown in FIG. 6 may have an average layer thickness of between about five nanometers (5 nm) and about twenty microns (20 μιη), between about five nanometers (5 nm) and about two microns (2 μιη), or even between about five nanometers (5 nm) and about one micron (1 μηι). In additional embodiments, the structure shown in FIG. 6 may be formed from a structure like that of FIG. 2 using methods other than the SMART CUT® process. For example, the first substrate 100 in the structure of FIG. 2 may be thinned by removing material from the second major surface 106 of the first substrate 100 (which is opposite the first major surface 104 of the first substrate 100) after bonding the first major surface 104 of the first substrate 100 to the major surface 124 of the second substrate 120. For example, one or more of a grinding process, a polishing process, and an etching process (e.g., a chemical-mechanical polishing (CMP) process) may be used to thin the first substrate 100 and form the thin layer of semiconductor material 108. In comparison, the first substrate 100 shown in FIG. 2 may have an average layer thickness of between about five nanometers (5 nm) and about seven hundred fifty microns (750 μιιη), between about five nanometers (5 nm) and about two hundred microns (200 μιη), or even between about five nanometers (5 nm) and about ten microns (10 μπι).

[0068] The structure shown in FIG. 6 comprises a composite semiconductor substrate 125, and may be used as a substrate and/or further processed to form a semiconductor device. In some embodiments, the all or a portion of the composite semiconductor substrate 125 may be present within a fully processed semiconductor structure or semiconductor device. For example, the second substrate 120 may comprise a thermally conductive material and may, therefore, be used as a heat dissipation layer of a final semiconductor structure and/or device. In such a case, the graphene 1 10, 130 may provide adhesion and thermal conductivity between the thin layer of semiconductor material 108 and the second substrate 120. In some embodiments, the second substrate 120 may comprise an electrically conductive material, such as a metal material, and may form an electrode or other conductive component of a semiconductor device, and the graphene 1 10, 130 may provide adhesion and electrical conductivity between the thin layer of semiconductor material 108 and the second substrate 120. [0069] Alternatively, the second substrate 120 may be a temporaiy carrier that is to be removed in a subsequent process in the formation of a final semiconductor structure and/or semiconductor device. In such cases, the second substrate 120 may be removed. The graphene 110, 130 also may optionally be removed.

[0070] FIGS. 7 through 10 illustrate examples of embodiments of methods that may be used to further process the composite semiconductor substrate 125 of FIG. 6 to form additional semiconductor structures and semiconductor devices.

[0071] Referring to FIG. 7, at least one active device may be formed using at least a portion of the thin layer of semiconductor material 108. In some embodiments, the active device may comprise at least one of a switching device (e.g., a transistor), a light-emitting device (e.g., a light-emitting diode, a laser diode), and a light-absorbing device (e.g., a solar cell, portions of a solar cell, a photodetector). In some embodiments, at least a portion of an integrated circuit may be formed on and/or in the exposed major surface 109 of the thin layer of semiconductor material 108.

[0072] For example, FIG. 7 illustrates an active layer 140 formed on the major surface 109 that includes a plurality of transistors 142 formed in and over the thin layer of semiconductor material 108. The transistors 142 may include doped regions 144 (e.g., source and drain regions) formed in the thin layer of semiconductor material 108. Thus, the major surface 109 of the thin layer of semiconductor material 108 may comprise what is often referred to in the art as an "active surface" of the thin layer of semiconductor material 108. The transistors 142 may be formed in, on, and/or over the major surface 109 of the thin layer of semiconductor material 108 using processes known in the art. As a non-limiting example, the transistors 142 may comprise metal oxide semiconductor field effect transistors (MOSFETs), and may embody complementary metal oxide semiconductor (CMOS) technology. Processes often employed in the art to fabricate such transistors 142 are often referred to in the art as "front-end-of-line" (FEOL) processes, and often involve processes carried out at temperatures greater than about 400° C. Thus, in some

embodiments, the material of the second substrate 120 may be selected to be able to withstand such temperatures.

[0073] After forming the transistors 142, one or more additional layers of electrically conductive features used to electrically interconnect various features of the transistors 142 (e.g., the doped regions 144 and gates of the transistors 142) may be formed. Such electrically conductive features may be disposed at least partially within a dielectric material 146. The conductive features may comprise one or more of laterally extending conductive lines 148 (e.g. , traces) and vertically extending conductive vias 150. The conductive features may comprise electrically conductive material regions (e.g., copper, aluminum, tungsten, titanium, etc.) that are at least partially embedded in the dielectric material 146. The conductive features and surrounding dielectric material 146 may be formed in a layer-by-layer lithographic process. In such processes, layers of dielectric material and layers of conductive material may be deposited and selectively patterned in an alternating manner to form the various conductive features and the dielectric material 146. The processes often employed in the art to fabricate these electrically conductive features are often referred to in the art as "back-end-of-line" (BEOL) processes, and often involve processes carried out at temperatures of about 400° C or less (although, in some embodiments, one or more initial layers of metal deposited as part of the BEOL processes may comprise tungsten, which may be deposited at temperatures up to about nine hundred degrees Celsius (900° C)).

[0074] One or more of the conductive features formed in the active layer 140 (e.g., one or more of the conductive lines 148 and conductive vias 150) may be electrically coupled with one or more of a doped region 144 (e.g., a source or a drain region), a gate of the transistors 142, a contact pad, another conductive via, a capacitor, and a digit line (e.g., a word line, a bit line), for example.

[0075] The transistors 142 and the conductive features formed in the active layer 140 (e.g., one or more of the conductive lines 148 and conductive vias 150) may form at least a portion of an integrated circuit. After the FEOL processing and BEOL processing, the structure of FIG. 7 may be further processed as needed or desirable to form a final semiconductor device.

[0076] Although the processes described above with reference to FIG. 7 involve the formation of an active layer 140 on the thin layer of semiconductor material 108, in additional embodiments, at least portions of the active layer 140 may be formed separately from the thin layer of semiconductor material 108 and subsequently bonded over the thin layer of semiconductor material 108. For example, such a separately formed active layer 140 may be bonded to the thin layer of semiconductor material 108 using a direct bonding process similar to the direct bonding process described above with reference to FIG. 2.

[0077] In some embodiments, the second substrate 120 optionally may be removed from the thin layer of semiconductor material 108 and the active layer 140. For example, referring to FIG. 8, a carrier substrate 160 may be attached to the active layer 140 on a side of the active layer 140 opposite the thin layer of semiconductor material 108 prior to removing the second substrate 120 from the thin layer of semiconductor material 108.

[0078] The carrier substrate 160 may ultimately become a portion of a final

semiconductor structure or device, or it may be later removed. For example, in some embodiments, the carrier substrate 160 may ultimately function as a heat dissipation layer and may comprise a material having a relatively high thermal conductivity, such as a metal material. In some embodiments, the carrier substrate 160 may function as an electrical isolation layer and may comprise a dielectric material. In some embodiments, the carrier substrate 160 may function as an electrical conduction layer and may comprise a conductive material. The carrier substrate 160 may be formed separately and attached to the active layer 140, such as by using a direct bonding process similar to the bonding process described above with reference to FIG. 2. Alternatively, the carrier substrate 160 may be formed over the active layer 140 by one or more of a sputtering process, an electrolytic plating process, an electroless plating process, a CVD process, and a physical vapor deposition (PVD) process, for example.

[0079] Referring to FIG. 9, the second substrate 120 may be removed from the thin layer of semiconductor material 108, the active layer 140, and the carrier substrate 160 by initiating fracture along the graphene 110, 130 between the thin layer of semiconductor material 108 and the second substrate 120.

[0080] In some embodiments, the second substrate 120 may be removed by applying a mechanical force to one or more of the thin layer of semiconductor material 108, the active layer 140, the carrier substrate 160, and the second substrate 120. Such a mechanical force may cause cleavage of the structure along the graphene 110, 130 between the second substrate 120 and the thin layer of semiconductor material 108.

[0081] In some embodiments, the second substrate 120 may be removed using a so-called "laser lift-off (LLO) process, as is known in the art. In an LLO process, the second substrate 120 may be transparent to laser radiation, and the graphene 110, 130 may be irradiated with laser radiation through the transparent second substrate 120. For example, the second substrate 120 may comprise sapphire (A1₂0₃) in such embodiments. The graphene 110, 130 may absorb at least some energy from the laser radiation, resulting in localized heating of the graphene 110, 130 and thermal detachment of the second substrate 120. [0082] In another embodiment, the second substrate 120 may be removed using a chemical etching process. For example, the additional graphene 130 may act as a chemical etch stop material and may, therefore, be at least somewhat resistant to a chemical etchant that removes (e.g., dissolves) the second substrate 120. As a non-limiting example, if the second substrate 120 is substantially comprised of copper or molybdenum, the second substrate 120 may be removed by a chemical etching process, as described above with respect to FIG. 1 and Bae.

[0083] Referring to FIG. 10 in conjunction with FIG. 9, in some embodiments, if graphene 110, 130 remains on the thin layer of semiconductor material 108 after removing the second substrate 120, at least a portion of the remaining graphene 110, 130, optionally, may be removed from the surface of the thin layer of semiconductor material 108. For example, the remaining graphene 110, 130 may be removed by at least one of an etching process, a grinding process, and a polishing process (e.g., a CMP process). In such embodiments, a portion of the thin layer of semiconductor material 108j optionally, may be removed along with the graphene 110, 130. Thus, a semiconductor structure or device formed in this manner may include at least a portion of the thin layer of semiconductor material 108, the active layer 140, and the carrier substrate 160.

[0084] Although the process described with reference to FIG. 10 includes removal of the graphene 110, 130, in other embodiments, at least a portion of the graphene 110, 130 may be left on the thin layer of semiconductor material 108, such as for providing one or more of a heat dissipation layer, an adhesion layer for adhering to another structure (e.g., a printed circuit board, an interposer, a lead frame, etc.), and a low resistance electrical contact to a final structure, device, or system.

[0085] Additional non-limiting example embodiments of the present disclosure are set forth below.

[0086] Embodiment 1 : A method of forming a semiconductor structure, comprising: disposing graphene over at least one of a major surface of a first substrate and a major surface of a second substrate, at least the first substrate comprising a semiconductor material; and bonding the major surface of the first substrate to the major surface of the second substrate with the graphene disposed between the major surface of the first substrate and the major surface of the second substrate.

[0087] Embodiment 2: The method of Embodiment 1, wherein disposing the graphene over at least one of the major surface of the first substrate and the major surface of the second substrate comprises: disposing at least one graphene monolayer over the major surface of the first substrate; and disposing at least one graphene monolayer over the major surface of the second substrate.

[0088] Embodiment 3: The method of Embodiment 2, wherein bonding the major surface of the first substrate to the major surface of the second substrate comprises bonding the at least one graphene monolayer over the major surface of the first substrate directly to the at least one graphene monolayer over the major surface of the second substrate.

[0089] Embodiment 4: The method of any one of Embodiments 1 through 3, further comprising establishing inter-atomic bonds directly between the graphene and each of the major surface of the first substrate and the major surface of the second substrate.

[0090] Embodiment 5: The method of any one of Embodiments 1 through 4, wherein disposing the graphene over at least one of the major surface of the first substrate and the major surface of the second substrate comprises growing the graphene directly on the at least one of the major surface of the first substrate and the major surface of the second substrate.

[0091] Embodiment 6: The method of any one of Embodiments 1 through 4, wherein disposing the graphene over at least one of the major surface of the first substrate and the major surface of the second substrate comprises: growing the graphene on a growth substrate; and transferring the graphene grown on the growth substrate to the at least one of the major surface of the first substrate and the major surface of the second substrate.

[0092] Embodiment 7: The method of any one of Embodiments 1 through 6, further comprising forming a thin layer of semiconductor material from the first substrate after bonding the major surface of the first substrate to the major surface of the second substrate, the thin layer of semiconductor material bonded to the second substrate with the graphene disposed between the thin layer of semiconductor material and the major surface of the second substrate.

[0093] Embodiment 8: The method of Embodiment 7, wherein forming the thin layer of semiconductor material from the first substrate comprises fracturing the first substrate along a plane to separate the thin layer of semiconductor material from a remainder of the first substrate.

[0094] Embodiment 9: The method of Embodiment 8, further comprising implanting ions into the first substrate prior to bonding the major surface of the first substrate to the major surface of the second substrate and forming a generally planar zone of weakness within the first substrate along the plane along which the first substrate is subsequently fractured to separate the thin layer of semiconductor material from the remainder of the first substrate. [0095] Embodiment 10: The method of Embodiment 7, wherein forming the thin layer of semiconductor material from the first substrate comprises thinning the first substrate by removing material from a side of the first substrate opposite the major surface of the first substrate after bonding the major surface of the first substrate to the major surface of the second substrate.

[0096] Embodiment 11 : The method of any one of Embodiments 7 through 10, further comprising forming at least one active device using at least a portion of the thin layer of semiconductor material.

[0097] Embodiment 12: The method of Embodiment 11, wherein forming at least one active device comprises forming at least one of a switching device, a light-emitting device, and a light-absorbing device.

[0098] Embodiment 13: The method of any one of Embodiments 7 through 12, further comprising removing the second substrate from the thin layer of semiconductor material.

[0099] Embodiment 14: The method of Embodiment 13, further comprising attaching a carrier substrate to the thin layer of semiconductor material over a side thereof opposite the second substrate prior to removing the second substrate from the thin layer of semiconductor material.

[00100] Embodiment 15: The method of Embodiment 13 or Embodiment 14, wherein removing the second substrate from the thin layer of semiconductor material comprises initiating fracture along the graphene to remove the second substrate from the thin layer of semiconductor material.

[00101] Embodiment 16: The method of Embodiment 13 or Embodiment 14, wherein removing the second substrate from the thin layer of semiconductor material comprises etching the second substrate.

[00102] Embodiment 17: The method of any one of Embodiments 13 through 16, further comprising removing at least a portion of the graphene from the thin layer of semiconductor material after removing the second substrate from the thin layer of semiconductor material.

[00103] Embodiment 18: A semiconductor structure, comprising: a first substrate comprising a semiconductor material and having a major surface; a second substrate having a major surface; and at least one graphene monolayer disposed between the major surface of the first substrate and the major surface of the second substrate, the at least one graphene monolayer bonding the major surface of the first substrate to the major surface of the second substrate. [00104] Embodiment 19: The semiconductor structure of Embodiment 18, wherein the at least one graphene monolayer comprises a plurality of graphene monolayers.

[00105] Embodiment 20: The semiconductor structure of Embodiment 18 or Embodiment 19, further comprising direct inter-atomic bonds between the at least one graphene monolayer and the major surface of the first substrate and direct inter-atomic bonds between the at least one graphene monolayer and the major surface of the second substrate.

[00106] Embodiment 21 : The semiconductor structure of any one of Embodiments 18 through 20, further comprising at least one active device formed on the first substrate on a side thereof opposite the at least one graphene monolayer, the at least one active device including at least one of a switching device, a light-emitting device, and a light-absorbing device.

[00107] Embodiment 22: A composite semiconductor substrate, comprising: a base substrate; a thin layer of semiconductor material disposed over the base substrate; and at least one graphene monolayer disposed between the thin layer of semiconductor material and the base substrate.

[00108] Embodiment 23: The composite semiconductor substrate of Embodiment 22, wherein the thin layer of semiconductor material is bonded to the base substrate by the at least one graphene monolayer.

[00109] Embodiment 24: The composite semiconductor substrate of Embodiment 22 or Embodiment 23, wherein the at least one graphene monolayer comprises a plurality of graphene monolayers.

[00110] Embodiment 25: The composite semiconductor substrate of any one of

Embodiments 22 through 24, further comprising direct inter-atomic bonds between the at least one graphene monolayer and the thin layer of semiconductor material and direct inter-atomic bonds between the at least one graphene monolayer and the base substrate.

[00111] Embodiment 26: The composite semiconductor substrate of any one of

Embodiments 22 through 25, further comprising at least one active device formed on the thin layer of semiconductor material on a side thereof opposite the at least one graphene monolayer, the at least one active layer including at least one of a switching device, a light-emitting device, and a light-absorbing device.

[00112] The example embodiments of the disclosure described above do not limit the scope of the invention, since these embodiments are merely examples of embodiments of the invention, which is defined by the scope of the appended claims and their legal equivalents. Any equivalent embodiments are intended to be within the scope of this invention. Indeed, various modifications of the disclosure, in addition to those shown and described herein, such as alternate useful combinations of the elements described, will become apparent to those skilled in the art from the description. Such modifications and embodiments are also intended to fall within the scope of the appended claims.

Claims

CLAIMS What is claimed is:

1. A method of forming a semiconductor structure, comprising:

disposing graphene over at least one of a major surface of a first substrate and a major surface of a second substrate, at least the first substrate comprising a semiconductor material; and bonding the major surface of the first substrate to the major surface of the second substrate with the graphene disposed between the major surface of the first substrate and the major surface of the second substrate.

2. The method of claim 1, wherein disposing the graphene over at least one of the major surface of the first substrate and the major surface of the second substrate comprises: disposing at least one graphene monolayer over the major surface of the first substrate; and disposing at least one graphene monolayer over the major surface of the second substrate.

3. The method of claim 2, wherein bonding the major surface of the first substrate to the major surface of the second substrate comprises bonding the at least one graphene monolayer over the major surface of the first substrate directly to the at least one graphene monolayer over the major surface of the second substrate.

4. The method of claim 1, further comprising establishing inter-atomic bonds directly between the graphene and each of the major surface of the first substrate and the major surface of the second substrate.

5. The method of claim 1, wherein disposing the graphene over at least one of the major surface of the first substrate and the major surface of the second substrate comprises growing the graphene directly on the at least one of the major surface of the first substrate and the major surface of the second substrate.

6. The method of claim 1, wherein disposing the graphene over at least one of the major surface of the first substrate and the major surface of the second substrate comprises: growing the graphene on a growth substrate; and

transferring the graphene grown on the growth substrate to the at least one of the major surface of the first substrate and the major surface of the second substrate.

7. The method of claim 1, further comprising forming a thin layer of semiconductor material from the first substrate after bonding the major surface of the first substrate to the major surface of the second substrate, the thin layer of semiconductor material bonded to the second substrate with the graphene disposed between the thin layer of semiconductor material and the major surface of the second substrate.

8. The method of claim 7, wherein forming the thin layer of semiconductor material from the first substrate comprises fracturing the first substrate along a plane to separate the thin layer of semiconductor material from a remainder of the first substrate.

9. The method of claim 8, further comprising implanting ions into the first substrate prior to bonding the major surface of the first substrate to the major surface of the second substrate and forming a generally planar zone of weakness within the first substrate along the plane along which the first substrate is subsequently fractured to separate the thin layer of semiconductor material from the remainder of the first substrate.

10. The method of claim 7, further comprising forming at least one active device using at least a portion of the thin layer of semiconductor material.

11. The method of claim 7, further comprising removing the second substrate from the thin layer of semiconductor material.

12. The method of claim 1 1, further comprising attaching a carrier substrate to the thin layer of semiconductor material over a side thereof opposite the second substrate prior to removing the second substrate from the thin layer of semiconductor material.

13. The method of claim 11, wherein removing the second substrate from the thin layer of semiconductor material comprises initiating fracture along the graphene to remove the second substrate from the thin layer of semiconductor material.

14. The method of claim 11 , wherein removing the second substrate from the thin layer of semiconductor material comprises etching the second substrate.

15. The method of claim 11, further comprising removing at least a portion of the graphene from the thin layer of semiconductor material after removing the second substrate from the thin layer of semiconductor material.

16. A composite semiconductor substrate, comprising:

a base substrate;

a thin layer of semiconductor material disposed over the base substrate; and

at least one graphene monolayer disposed between the thin layer of semiconductor material and the base substrate.

17. The composite semiconductor substrate of claim 16, wherein the thin layer of semiconductor material is bonded to the base substrate by the at least one graphene monolayer.

18. The composite semiconductor substrate of claim 16, wherein the at least one graphene monolayer comprises a plurality of graphene monolayers.

19. The composite semiconductor substrate of claim 16, further comprising direct inter-atomic bonds between the at least one graphene monolayer and the thin layer of semiconductor material and direct inter-atomic bonds between the at least one graphene monolayer and the base substrate.

20. The composite semiconductor substrate of claim 16, further comprising at least one active device formed on the thin layer of semiconductor material on a side thereof opposite the at least one graphene monolayer, the at least one active device including at least one of a switching device, a light-emitting device, and a light-absorbing device.